Resistance anode single-photon camera based on triangle-trapezoid double-channel shaping algorithm

Abstract

The invention provides a resistance anode single-photon camera based on a triangle-trapezoid double-channel shaping algorithm, which is used for solving the problem that a signal superposition phenomenon can occur in a trapezoid shaping signal flat top part of an existing resistance anode single-photon camera based on a trapezoid filter shaping algorithm. The technical problem that the imaging resolution of the resistance anode single-photon camera is reduced due to the fact that the amplitude of the next pulse is affected by the tail wave of the previous pulse and even amplitude extraction and position signal calculation are affected when excessive signals are superposed is solved. According to the resistance anode single-photon camera provided by the invention, a simulation part in traditional electronics is digitalized, a triangular shaping algorithm is introduced on the basis of a traditional trapezoidal shaping algorithm, the pulse position is determined through the triangular shaping algorithm, and then the pulse amplitude is determined through the trapezoidal shaping algorithm, so that the accuracy of the resistance anode single-photon camera is improved. The effective pulse peak value under the condition of pulse superposition can be identified more accurately, and the spatial resolution of the resistance anode single-photon camera is greatly improved.

Description

Technical Field

[0001] The invention relates to a single-photon camera, and in particular to a resistor anode single-photon camera based on a triangle-trapezoidal dual-channel shaping algorithm. Background Art

[0002] In the research fields of high-energy particle tracking, space exploration, and biomedical development, the optical signal carrying event information contains only a limited number of photons. Therefore, single-photon cameras with photon counting capabilities have become a research hotspot and are widely used in nuclear and particle physics experiments and particle position measurement in the field of radiographic imaging. Single-photon cameras are mainly composed of an anode detector and an electronic readout system. The anode detector mainly includes a photocathode, a microchannel plate (MCP), and a position sensitive detector (PSD). The principle is that the photocathode converts a single photon signal into an electrical signal. When the electron hits the surface of the MCP, the signal is multiplied to produce an electron cloud. The position sensitive detector obtains the position information of the electron cloud.

[0003] Position sensitive detectors can be delay line anodes, wedge strip anodes or resistor anodes, etc. Different forms of anodes use different technologies to determine the position of the incident particle. Among them, the resistor anode has been widely used in the field of low-light imaging because it can provide good spatial resolution and reduce the number of electronic channels required. However, the performance of the existing single-photon camera based on the resistor anode is limited by the resistor anode plate at the front end and the electronic readout system at the back end. The resistor anode plate has been developed for a long time, and the design structure tends to be stable. It is difficult to have a better improvement plan. Therefore, the current research focus of the resistor anode single-photon camera is mainly on the improvement of the electronic readout system. Compared with the resistor anode plate, the development of the electronic readout system is relatively slow. The early electronic readout system directly reads the detector output signal and extracts the peak value, and then performs position decoding. With the development of analog circuit technology, discrete components are now mainly used to construct the filter shaping circuit in the electronic readout system to improve the position calculation accuracy of the output signal. However, when a large number of single-photon signals reach the resistor anode plate, pulse accumulation will occur in the output signal of the analog shaping circuit, resulting in a decrease in the system count rate, which in turn reduces the image resolution and cannot meet the growing detection needs.

[0004] In 2001, Cosimo Imperiale proposed a Z-domain-based trapezoidal filter shaping algorithm, which uses the Z-domain expressions of the input and output signals to calculate the system function to suppress high-frequency noise and achieve system filtering. The pulse signal collected by the ADC has the characteristics of short rise time, long fall time, and small ballistic loss. Compared with the traditional analog shaping circuit, the trapezoidal shaping algorithm has better energy resolution and higher counting rate. However, due to the randomness of the single-photon signal, the output of the preamplifier circuit will produce a tailing effect, resulting in signal superposition in the flat-top part of the trapezoidal shaping signal. When this signal superposition phenomenon occurs, the tail wave of the previous pulse will affect the amplitude of the next pulse, and even when the signal is superimposed too much, it will affect the amplitude extraction and calculation of the position signal, thereby reducing the imaging resolution of the resistor anode single-photon camera. Summary of the invention

[0005] The purpose of the present invention is to solve the technical problem that the flat-top part of the trapezoidal shaping signal of the existing resistive anode single-photon camera based on the trapezoidal filter shaping algorithm will have a signal superposition phenomenon, resulting in the tail wave of the previous pulse affecting the amplitude of the next pulse, and even affecting the amplitude extraction and the calculation of the position signal when the signal is superimposed too much, thereby reducing the imaging resolution of the resistive anode single-photon camera, and provide a resistive anode single-photon camera based on a triangle-trapezoidal dual-channel shaping algorithm.

[0006] In order to achieve the above purpose, the technical solution of the present invention is as follows:

[0007] A resistor anode single-photon camera based on a triangle-trapezoidal dual-channel shaping algorithm is special in that it includes a resistor anode detector, an electronic readout system and a host computer; the electronic readout system includes four charge-sensitive amplifier circuits, an ADC module and a signal processing unit;

[0008] The input ends of the four charge-sensitive amplifier circuits are respectively connected to the output ends of the resistor anode detector, and are used to convert the four charge signals output by the resistor anode detector into corresponding voltage signals and amplify them;

[0009] The four input ends of the ADC module are respectively connected to the output ends of four charge-sensitive amplifier circuits, so as to collect four amplified voltage signals and convert them into corresponding digital signals for output respectively;

[0010] The signal processing unit includes four identical signal processing modules and a position calculation module; the signal processing module includes a trapezoidal shaping module, a triangular shaping module, a baseline recovery module, a trapezoidal peak finding module, a triangular peak finding module, a signal delay module and a peak output channel;

[0011] The input ends of the trapezoidal shaping module and the triangular shaping module in each signal processing module are connected to an output end of the ADC module, respectively, for performing trapezoidal shaping and triangular shaping on the digital signal output by the ADC module, and obtaining corresponding trapezoidal shaping signals and triangular shaping signals;

[0012] The two input ends of the baseline recovery module are respectively connected to the output ends of the trapezoidal shaping module and the triangular shaping module, and are used to perform baseline deviation recovery on the trapezoidal shaping signal and the triangular shaping signal;

[0013] The input end of the triangular peak-finding module is connected to the first output end of the baseline recovery module, and is used to extract the peak value and position of the triangular shaped signal; the first input end of the trapezoidal peak-finding module is connected to the second output end of the baseline recovery module, and the second input end is connected to the position output end of the triangular peak-finding module, and is used to extract the peak value of the trapezoidal shaped signal according to the position information of the triangular shaped signal;

[0014] The three input ends of the signal delay module are respectively connected to the position output end, the peak output end and the peak output end of the triangle peak search module and the trapezoidal peak search module for signal synchronization;

[0015] The three input ends of the peak output channel are respectively connected to the peak output end, the position output end and the peak output end of the trapezoidal shaping signal in the signal delay module, and are used to judge the pulse accumulation situation according to the position information of the triangular shaping signal, and select to output the peak value of the triangular shaping signal or the peak value of the trapezoidal shaping signal or abandon the current signal according to the pulse accumulation situation;

[0016] The four input ends of the position calculation module are respectively connected to the output ends of four peak output channels, so as to calculate the position coordinates of single photons according to the four peak values; the input end of the host computer is connected to the output end of the position calculation module, so as to complete single photon imaging according to the position coordinates of single photons.

[0017] Furthermore, the peak output channel includes a pulse interval calculation module, a first comparison module, a second comparison module and a decision output module;

[0018] The input end of the pulse interval calculation module is connected to the position output end of the triangle shaped signal of the signal delay module, and is used to calculate the adjacent pulse interval ΔT according to the position information of two adjacent triangle shaped pulses;

[0019] The first input end of the first comparison module is connected to the output end of the pulse interval calculation module, and the second input end is used to input the sum of the rise time and the flat top time of the set trapezoidal shaping signal t b ;

[0020] The first input terminal of the second comparison module is connected to the first output terminal of the first comparison module, and the second input terminal is used to input the set rise time t of the trapezoidal shaping signal. a ;

[0021] The four input ends of the judgment output module are respectively connected to the peak output end of the triangle shaping signal of the signal delay module, the peak output end of the trapezoidal shaping signal, the second output end of the first comparison module and the output end of the second comparison module, so as to b When the peak value of the trapezoidal shaped signal is output, at t a ≤ΔT<t b When ΔT<t a When , the current signal is discarded;

[0022] The four input ends of the position calculation module are respectively connected to the output ends of the corresponding decision output modules in the four signal processing modules.

[0023] Further, the four peak output channels corresponding to the four signal processing modules are defined as channel A, channel B, channel C and channel D, and channel A is located at the upper left position of the signal processing unit, and channel B, channel C and channel D are arranged clockwise at intervals of 90 degrees.

[0024] The position calculation module calculates the position coordinates (x, y) of a single photon using the following formula:

[0025]

[0026] In the above formula, V A 、V B 、V C 、V D Respectively represent the peak values ​​of the outputs of channel A, channel B, channel C, and channel D.

[0027] Furthermore, the trapezoidal shaping module is a high-order IIR filter, and its system function H(z) based on the Z domain is:

[0028]

[0029] in, Indicates that the signal is delayed by n a Sampling period, Indicates that the signal is delayed by n b Sampling period, z -1 Indicates that the signal is delayed by one sampling period, n a =t a / T s , n b =t b / T s , Ts is the sampling period; τ1 is the fast time constant, τ2 is the slow time constant;

[0030] The triangular shaping module is a high-order IIR filter, and its system function H(z)′ based on the Z domain is:

[0031]

[0032] Furthermore, the high-order IIR filter of the trapezoidal shaping module is constructed by a four-stage cascade method, including a first-stage subsystem H1(z), a second-stage subsystem H2(z), a third-stage subsystem H3(z) and a fourth-stage subsystem H4(z), and the expressions thereof are as follows:

[0033]

[0034] Among them, n c =t c / T s , t c Indicates the duration of the pulse signal;

[0035] The high-order IIR filter of the triangular shaping module is constructed by a four-stage cascade method, including a first-stage subsystem H1(z)′, a second-stage subsystem H2(z)′, a third-stage subsystem H3(z)′ and a fourth-stage subsystem H4(z)′, and their expressions are as follows:

[0036]

[0037] Further, the first-level subsystem H1(z) includes a delayer delay1, a delayer delay2, a delayer delay3, a subtractor sub1, a subtractor sub2, and an adder add1;

[0038] The input ends of the delayer delay1, delayer delay2, and delayer delay3 are all connected to the corresponding output ends of the ADC module, and are used to delay the digital signal output by the ADC module by n. a 、n b 、n c The first input end of the subtractor sub1 is connected to the corresponding output end of the ADC module, and the second input end thereof is connected to the output end of the delay device delay1. The first input end of the subtractor sub2 is connected to the output end of the subtractor sub1, and the second input end thereof is connected to the output end of the delay device delay2. The first input end of the adder add1 is connected to the output end of the subtractor sub2, and the second input end thereof is connected to the output end of the delay device delay3, so as to make the first-level subsystem

[0039] The second-level subsystem H2(z) includes a multiplier mux1, a delayer delay4 and a subtractor sub3;

[0040] The input end of the multiplier mux1 is connected to the first output end of the adder add1, and the output end of the multiplier mux1 is connected to the input end of the delayer delay4. The output end of the delayer delay4 is connected to the first input end of the subtractor sub3, and the second input end of the subtractor sub3 is connected to the second output end of the adder add1, so that the second-level subsystem H2(z)=1-α1 -1 ;

[0041] The third-level subsystem H3(z) includes a multiplier mux2, a delayer delay5 and a subtractor sub4;

[0042] The input end of the multiplier mux2 is connected to the first output end of the subtractor sub3, and the output end of the multiplier mux2 is connected to the input end of the delayer delay5. The output end of the delayer delay5 is connected to the first input end of the subtractor sub4, and the second input end of the subtractor sub4 is connected to the second output end of the subtractor sub3, so as to make the third-level subsystem H3(z)=1-α2 -1 ;

[0043] The fourth-level subsystem H4(z) includes an adder add2, an adder add3, a multiplier mux3, a delayer delay6 and a delayer delay7;

[0044] The adder add2, adder add3, and multiplier mux3 are connected in sequence in the order of input and output. One input end of the adder add2 is connected to the output end of the subtractor sub4. The input end of the delayer delay6 is connected to the other output end of the adder add2, and its output end is connected to the other input end of the adder add2. The input end of the delayer delay7 is connected to the other output end of the adder add3, and its output end is connected to the other input end of the adder add3, so as to make the fourth-level subsystem

[0045] The first-level subsystem H1(z)′ includes a delayer delay1′, a delayer delay2′, a delayer delay3′, a subtractor sub1′, a subtractor sub2′, and an adder add1′;

[0046] The input ends of the delayer delay1′, the delayer delay2′ and the delayer delay3′ are connected to the corresponding output ends of the ADC module, and are used to delay the digital signal output by the ADC module by n. a 、n a 、n cThe first input end of the subtractor sub1′ is connected to the corresponding output end of the ADC module, and the second input end thereof is connected to the output end of the delay device delay1′. The first input end of the subtractor sub2′ is connected to the output end of the subtractor sub1′, and the second input end thereof is connected to the output end of the delay device delay2′. The first input end of the adder add1′ is connected to the output end of the subtractor sub2′, and the second input end thereof is connected to the output end of the delay device delay3′, so as to make the first-level subsystem

[0047] The second-stage subsystem H2(z)′ includes a multiplier mux1′, a delayer delay4′ and a subtractor sub3′;

[0048] The input end of the multiplier mux1′ is connected to the first output end of the adder add1′, and the output end of the multiplier mux1′ is connected to the input end of the delayer delay4′. The output end of the delayer delay4′ is connected to the first input end of the subtractor sub3′, and the second input end of the subtractor sub3′ is connected to the second output end of the adder add1′, so that the second-level subsystem H2(z)′=1-α1 -1 ;

[0049] The third-level subsystem H3(z)′ includes a multiplier mux2′, a delayer delay5′ and a subtractor sub4′;

[0050] The input end of the multiplier mux2′ is connected to the first output end of the subtractor sub3′, and the output end of the multiplier mux2′ is connected to the input end of the delayer delay5′. The output end of the delayer delay5′ is connected to the first input end of the subtractor sub4′, and the second input end of the subtractor sub4′ is connected to the second output end of the subtractor sub3′, so as to make the third-level subsystem H3(z)′=1-α2 -1 ;

[0051] The fourth-level subsystem H4(z)′ includes an adder add2′, an adder add3′, a multiplier mux3′, a delayer delay6′ and a delayer delay7′;

[0052] The adder add2′, adder add3′, and multiplier mux3′ are connected in sequence in the order of input and output. The input end of the adder add2′ is connected to the output end of the subtractor sub4′, the input end of the delayer delay6′ is connected to the other output end of the adder add2′, and the output end thereof is connected to the other input end of the adder add2′. The input end of the delayer delay7′ is connected to the other output end of the adder add3′, and the output end thereof is connected to the other input end of the adder add3′, so as to make the fourth-level subsystem

[0053] Furthermore, the ADC module includes two ADC acquisition circuits;

[0054] Two input ends of an ADC acquisition circuit are respectively connected to the output ends of two charge-sensitive amplifier circuits, a first output end thereof is respectively connected to the input ends of delayer delay1, delayer delay2, delayer delay3, subtractor sub1, delayer delay1′, delayer delay2′, delayer delay3′, and subtractor sub1′ in the first signal processing module, and a second output end thereof is respectively connected to the input ends of delayer delay1, delayer delay2, delayer delay3, subtractor sub1, delayer delay1′, delayer delay2′, delayer delay3′, and subtractor sub1′ in the second signal processing module;

[0055] The two input ends of another ADC acquisition circuit are respectively connected to the output ends of the other two charge-sensitive amplifier circuits, and its first output end is respectively connected to the input ends of delayer delay1, delayer delay2, delayer delay3, subtractor sub1, delayer delay1′, delayer delay2′, delayer delay3′, and subtractor sub1′ in the third signal processing module, and its second output end is respectively connected to the input ends of delayer delay1, delayer delay2, delayer delay3, subtractor sub1, delayer delay1′, delayer delay2′, delayer delay3′, and subtractor sub1′ in the fourth signal processing module.

[0056] Furthermore, the signal processing unit is constructed based on FPGA.

[0057] Furthermore, the trapezoidal shaping module and the triangular shaping module are both implemented by algorithms using System Generator software.

[0058] Compared with the prior art, the present invention has the following beneficial effects:

[0059] 1. The present invention provides a resistive anode single-photon camera based on a triangle-trapezoidal dual-channel shaping algorithm, which digitizes the analog part of traditional electronics and introduces a triangle shaping algorithm based on the traditional trapezoidal shaping algorithm to form a triangle-trapezoidal dual-channel shaping algorithm. The algorithm first uses a triangle shaping algorithm to determine the pulse position, and then uses a trapezoidal shaping algorithm to determine the pulse amplitude. It can more accurately identify the effective pulse peak value under pulse superposition, that is, more accurately retain a large number of effective pulse values ​​under pulse superposition, alleviate the decrease in counting rate caused by pulse accumulation, greatly improve the spatial resolution of the resistive anode single-photon camera, and improve the image quality.

[0060] 2. The triangle-trapezoidal dual-channel shaping algorithm proposed in the present invention has good real-time performance, can reduce system delay, and improve imaging speed. It can be applied to other electronic readout systems to improve the performance of corresponding detectors.

[0061] 3. The signal processing unit of the present invention is constructed based on FPGA, which can effectively improve the stability of the system and reduce the size of the single-photon camera. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 It is a structural block diagram of an embodiment of a resistor anode single-photon camera based on a triangle-trapezoidal dual-channel shaping algorithm of the present invention;

[0063] Figure 2 is a structural block diagram of a signal processing module in an embodiment of the present invention;

[0064] Figure 3 The waveform diagram of the signal before and after shaping using the trapezoidal shaping algorithm, where (a) is the input signal waveform diagram, and (b) is the output trapezoidal shaping signal waveform diagram;

[0065] Figure 4 A circuit topology diagram of four subsystems of a trapezoidal shaping module constructed by a cascade method in an embodiment of the present invention;

[0066] Figure 5 It is a structural block diagram of a peak output channel in an embodiment of the present invention;

[0067] Figure 6 Figure 1 is a waveform diagram of the data processing process of the signal processing module based on the triangle-trapezoidal dual-channel shaping algorithm in the embodiment of the present invention, wherein (a) is a waveform diagram of the input signal when pulses are piled up, (b) is a waveform diagram of the signal after the pulses are piled up using the triangle-trapezoidal dual-channel shaping algorithm, and (c) is a waveform diagram of the extracted peak signal;

[0068] Figure 7 The test image input during the test experiment;

[0069] Figure 8 The input signal waveform diagram of channel A, channel B, channel C and channel D during the test experiment;

[0070] Fig. 9 The original input image during the test experiment and the imaging results processed by different algorithms, where (a) is the original input image, (b) is the imaging result of the original input signal, (c) is the imaging result after being shaped by the traditional trapezoidal shaping algorithm, and (d) is the imaging result after being shaped by the triangle-trapezoidal dual-channel shaping algorithm of the present invention;

[0071] Fig.10The figures are schematic diagrams comparing the imaging of a conventional electronic readout system and the electronic readout system based on a triangular-trapezoidal dual-channel shaping algorithm of the present invention, wherein the left side of (a) is a schematic diagram of the imaging of a conventional electronic readout system, and the right side is a corresponding grayscale curve diagram, and the left side of (b) is a schematic diagram of the imaging of an electronic readout system based on a triangular-trapezoidal dual-channel shaping algorithm, and the right side is a corresponding grayscale curve diagram.

[0072] The specific reference numerals are as follows:

[0073] 1-resistance anode detector; 2-electronic readout system, 21-charge sensitive amplifier circuit, 22-ADC acquisition circuit, 23-signal processing module, 231-trapezoidal shaping module, 232-triangular shaping module, 233-baseline recovery module, 234-trapezoidal peak search module, 235-triangular peak search module, 236-signal delay module, 237-peak output channel, 2371-pulse interval calculation module, 2372-first comparison module, 2373-second comparison module, 2374-judgment output module, 238-oscilloscope, 24-position calculation module; 3-host computer. DETAILED DESCRIPTION

[0074] In order to make the advantages and features of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0075] like Figure 1 As shown, a resistor anode single-photon camera based on a triangle-trapezoidal dual-channel shaping algorithm includes a resistor anode detector 1, an electronic readout system 2, and a host computer 3. The electronic readout system 2 includes four charge-sensitive amplifier circuits 21, an ADC module, and a signal processing unit. The input ends of the four charge-sensitive amplifier circuits 21 are respectively connected to the output ends of the resistor anode detector 1, and are used to convert the four charge signals output by the resistor anode detector 1 into corresponding voltage signals and amplify them.

[0076] The four input ends of the ADC module are respectively connected to the output ends of the four charge-sensitive amplifier circuits 21, and are used to collect four amplified voltage signals and convert them into corresponding digital signals for output respectively. In this embodiment, the ADC module includes two ADC acquisition circuits 22. Specifically, the two input ends of one ADC acquisition circuit 22 are respectively connected to the output ends of two of the charge-sensitive amplifier circuits 21, and the two input ends of the other ADC acquisition circuit 22 are respectively connected to the output ends of the other two charge-sensitive amplifier circuits 21. In other embodiments of the present invention, the ADC module can also be set to four ADC acquisition circuits, each ADC acquisition circuit corresponding to a charge-sensitive amplifier circuit.

[0077] The signal processing unit is the core of the single-photon camera, and includes four identical signal processing modules 23 and a position calculation module 24. Considering that the flat-top part of the trapezoidal shaping signal may have a signal superposition phenomenon, resulting in the tail wave of the previous pulse affecting the amplitude of the next pulse, and even affecting the amplitude extraction and calculation of the position signal when the signal is superimposed too much, and the triangular shaping algorithm can better determine the position of the pulse amplitude when the pulse accumulates, the present invention proposes a new triangular-trapezoidal dual-channel shaping algorithm, which divides the input signal into two paths for processing: one path executes the trapezoidal shaping algorithm, and the other path executes the triangular shaping algorithm.

[0078] like Figure 2 As shown, each signal processing module 23 includes a trapezoidal shaping module 231 , a triangular shaping module 232 , a baseline recovery module 233 , a trapezoidal peak finding module 234 , a triangular peak finding module 235 , a signal delay module 236 and a peak output channel 237 .

[0079] The trapezoidal shaping module 231 and the triangular shaping module 232 are used to make a digital signal inputted from the corresponding ADC acquisition circuit 22 pass through two channels, namely, respectively through a trapezoidal shaping channel and a triangular shaping channel for shaping, to obtain corresponding trapezoidal shaping signals and triangular shaping signals.

[0080] The trapezoidal shaping module 231 calculates the system function of the trapezoidal shaping algorithm using the Z-domain expressions of the input and output signals. A is defined as the pulse height of the charge-sensitive amplifier circuit 21, which is proportional to the energy of the input signal. τ1 is the fast time constant and τ2 is the slow time constant. The time constant is affected by the charge-sensitive amplifier circuit 21. The specific value is averaged by curve fitting of multiple acquisition signals. s Sampling is performed for the sampling period and Z transform is implemented, where

[0081] like Figure 3 As shown in the figure, it is the signal waveform diagram before and after shaping using the trapezoidal shaping algorithm. Figure 3 (a) is the input signal waveform. The input signal is a double-sided negative exponential signal. Figure 3 (b) is the output trapezoidal shaped signal waveform. Then the Z-domain expression of the input signal is:

[0082]

[0083] The time domain expression of the output trapezoidal shaped signal is:

[0084]

[0085] Where A is the amplitude of the trapezoidal shaping signal, Indicates that the signal is delayed by na Sampling period, Indicates that the signal is delayed by n b Sampling period, z -1 Indicates that the signal is delayed by one sampling period, t c Indicates the duration of the pulse signal, n a =t a / T s , n b =t b / T s , t a Indicates the rise time of the trapezoidal shaped signal, t b It represents the sum of the rise time and the flat top time of the shaped signal.

[0086] The system function of the trapezoidal shaping algorithm can be obtained by H(z)=V out (z) / V in (z) is calculated to obtain formula (3):

[0087]

[0088] The essence of the trapezoidal shaping algorithm is a high-order IIR filter, which can effectively suppress high-frequency noise and realize the engineering of system filtering. This embodiment adopts a four-stage cascade method to construct a high-order IIR filter of the trapezoidal shaping module 231, that is, it is decomposed into four subsystems in a cascade manner, including a first-level subsystem H1(z), a second-level subsystem H2(z), a third-level subsystem H3(z) and a fourth-level subsystem H4(z), and their expressions are as follows:

[0089]

[0090] Among them, n c =t c / T s , t c Indicates the flat-top time of the trapezoidal shaped signal.

[0091] The signal processing unit of the present invention is constructed based on FPGA, which uses Xilinx's Artix7 FPGA to design the trapezoidal overall algorithm and the triangular shaping algorithm, and uses System Generator software to implement the trapezoidal overall algorithm and the triangular shaping algorithm. Figure 4As shown in FIG. 1 , it is a circuit topology diagram of the four subsystems of the trapezoidal shaping module constructed by the cascade method. The first-level subsystem H1(z) includes delayer delay1, delayer delay2, delayer delay3, subtractor sub1, subtractor sub2 and adder add1; the input ends of delayer delay1, delayer delay2 and delayer delay3 are all connected to the corresponding output ends of the corresponding ADC sampling circuit, which are used to delay the digital signal output by the ADC sampling circuit by n. a 、n b 、n c The first input end of the subtractor sub1 is connected to the corresponding output end of the ADC sampling circuit, and the second input end thereof is connected to the output end of the delay device delay1. The first input end of the subtractor sub2 is connected to the output end of the subtractor sub1, and the second input end thereof is connected to the output end of the delay device delay2. The first input end of the adder add1 is connected to the output end of the subtractor sub2, and the second input end thereof is connected to the output end of the delay device delay3, so as to make the first-level subsystem The second-level subsystem H2(z) includes a multiplier mux1, a delayer delay4, and a subtractor sub3; the input end of the multiplier mux1 is connected to the first output end of the adder add1, the output end of the multiplier mux1 is connected to the input end of the delayer delay4, the output end of the delayer delay4 is connected to the first input end of the subtractor sub3, and the second input end of the subtractor sub3 is connected to the second output end of the adder add1, so that the second-level subsystem H2(z)=1-α1 -1 The third-level subsystem H3(z) includes a multiplier mux2, a delayer delay5, and a subtractor sub4; the input end of the multiplier mux2 is connected to the first output end of the subtractor sub3, the output end of the multiplier mux2 is connected to the input end of the delayer delay5, the output end of the delayer delay5 is connected to the first input end of the subtractor sub4, and the second input end of the subtractor sub4 is connected to the second output end of the subtractor sub3, so that the third-level subsystem H3(z)=1-α2 -1 The fourth-level subsystem H4(z) includes an adder add2, an adder add3, a multiplier mux3, a delayer delay6, and a delayer delay7; the adder add2, the adder add3, and the multiplier mux3 are connected in sequence in the order of input and output, one input end of the adder add2 is connected to the output end of the subtractor sub4, the input end of the delayer delay6 is connected to the other output end of the adder add2, and the output end thereof is connected to the other input end of the adder add2, the input end of the delayer delay7 is connected to the other output end of the adder add3, and the output end thereof is connected to the other input end of the adder add3, so as to make the fourth-level subsystem Finally, the input signal is trapezoidally shaped to obtain a corresponding trapezoidally shaped signal.

[0092] The construction idea of ​​the triangle shaping module 232 is similar to that of the trapezoidal shaping module 231. a =t b When , the output is a triangular shaping signal (a special trapezoidal shaping signal). Correspondingly, the triangular shaping module 232 is a high-order IIR filter, and its system function H(z)′ based on the Z domain is:

[0093]

[0094] The triangular shaping module 232 is decomposed into four subsystems for a high-order IIR filter in a cascade manner, namely, a first-level subsystem H1(z)′, a second-level subsystem H2(z)′, a third-level subsystem H3(z)′ and a fourth-level subsystem H4(z)′, and their expressions are as follows:

[0095]

[0096] The circuit topology of the four subsystems of the triangle shaping module is different from that of the four subsystems of the trapezoidal shaping module only in the first-level subsystem H1(z)′. Specifically, the first-level subsystem H1(z)′ of the triangle shaping module includes a delayer delay1′, a delayer delay2′, a delayer delay3′, a subtractor sub1′, a subtractor sub2′, and an adder add1′; the input ends of the delayers delay1′, delay2′, and delay3′ are all connected to the corresponding output ends of the ADC module, and are used to delay one digital signal output by the ADC module by n. a 、n a 、n c The first input end of the subtractor sub1′ is connected to the corresponding output end of the ADC module, and the second input end thereof is connected to the output end of the delay device delay1′. The first input end of the subtractor sub2′ is connected to the output end of the subtractor sub1′, and the second input end thereof is connected to the output end of the delay device delay2′. The first input end of the adder add1′ is connected to the output end of the subtractor sub2′, and the second input end thereof is connected to the output end of the delay device delay3′, so as to make the first-level subsystem

[0097] The first input end of the baseline recovery module 233 is connected to the output end of the trapezoidal shaping module 231 , and the second input end thereof is connected to the output end of the triangle shaping module 232 , and is used to recover the baseline deviation of the trapezoidal shaping signal and the triangle shaping signal.

[0098] The input end of the triangular peak-finding module 235 is connected to the first output end of the baseline recovery module 233, and is used to extract the peak value and position of the triangular shaped signal. The first input end of the trapezoidal peak-finding module 234 is connected to the second output end of the baseline recovery module 233, and the second input end thereof is connected to the position output end of the triangular peak-finding module 235, and is used to extract the peak value of the trapezoidal shaped signal according to the position information of the triangular shaped signal input by the triangular peak-finding module 235.

[0099] The three input terminals of the signal delay module 236 are respectively connected to the position output terminal and the peak output terminal of the triangular peak-finding module 235 and the peak output terminal of the trapezoidal peak-finding module 234 for signal synchronization of the triangular shaping signal and the trapezoidal shaping signal.

[0100] The peak output channel 237 is used to determine the pulse accumulation situation according to the position information of the triangular shaped signal, and to select the peak value of the triangular shaped signal or the peak value of the trapezoidal shaped signal to be output or the current signal to be discarded according to the pulse accumulation situation. Figure 5 As shown, the peak output channel 237 includes a pulse interval calculation module 2371, a first comparison module 2372, a second comparison module 2373 and a decision output module 2374. The input end of the pulse interval calculation module 2371 is connected to the position output end of the triangle shaping signal of the signal delay module 236, and is used to calculate the adjacent pulse interval ΔT according to the position information of two adjacent triangle shaping pulses. The first input end of the first comparison module 2372 is connected to the output end of the pulse interval calculation module 2371, and the second input end is used to input the sum of the rise time and the flat top time t of the set trapezoidal shaping signal. b The first input terminal of the second comparison module 2373 is connected to the first output terminal of the first comparison module 2372, and the second input terminal is used to input the rise time t of the set trapezoidal shaping signal a The four input terminals of the decision output module 2374 are respectively connected to the peak output terminal of the triangle shaping signal of the signal delay module 236, the peak output terminal of the trapezoidal shaping signal, the second output terminal of the first comparison module 2372 and the output terminal of the second comparison module 2373, for determining the value of the decision output module 2374 when ΔT≥t b When the peak value of the output trapezoidal shaped signal is a ≤ΔT<t b When ΔT<t a When , the current signal is discarded.

[0101] like Figure 6 As shown, it is a schematic diagram of the principle of a signal processing module based on a triangle-trapezoidal dual-channel shaping algorithm, where Figure 6 (a) is the waveform of the input signal when pulses are piled up. Figure 6(b) is the signal waveform after the pulse accumulation is processed by the triangle-trapezoidal dual-channel shaping algorithm. Figure 6 (c) in the figure is the extracted peak signal waveform.

[0102] For the convenience of observation, this embodiment also provides a built-in oscilloscope 238 in each signal processing module for respectively collecting the output signals of the ADC sampling circuit, the baseline recovery module 233 and the peak output channel 237.

[0103] The four input ends of the position calculation module 24 are respectively connected to the output ends of the corresponding judgment output modules 2374 in the four signal processing modules, and are used to calculate the position coordinates of the single photon according to the four peak values. The four corresponding peak output channels 237 in the four signal processing modules 23 are defined as channel A, channel B, channel C and channel D, and channel A is located at the upper left position of the signal processing unit, and channel B, channel C and channel D are arranged clockwise at intervals of 90 degrees. The calculation formula of the single photon position coordinate (x, y) is as follows:

[0104]

[0105]

[0106] In the above formula, V A 、V B 、V C 、V D Respectively represent the peak values ​​of the outputs of channel A, channel B, channel C, and channel D.

[0107] The single photon position coordinates (x, y) output by the position calculation module 24 are stored in DDR3 (double-data-rate three synchronous dynamic random access memory) via the AXI (Advanced Extensible Interface) bus. The single photon position coordinate information stored in DDR3 is then transmitted to the host computer 3 via Ethernet, where the coordinates are visualized to complete single photon imaging.

[0108] The shaping effect of the triangle-trapezoidal dual-channel shaping algorithm of the present invention is further illustrated by specific tests below. Figure 7 As shown in the figure, the input test image is a grayscale image of 256*256 pixels. The input grayscale image is converted into a matrix for data storage, and then the data is binarized. The image in the white area is the valid area, and its pixels are 1, and the pixels in the black area are 0. The position information of the pixel 1 is recorded (x i ,y i ).

[0109] The electronic readout system determines the position coordinates of single photons through the peak information of four channels, and converts the position coordinates of single photons into amplitude data of four channels A, B, C, and D. When the algorithm is tested, the position coordinates of single photons are known, and the amplitude information corresponding to the position coordinates of each single photon is inferred by the calculation formula of the position coordinates of single photons. The input test image consists of 2551 effective pixels, such as Figure 8 As shown, the input signal waveforms of channel A, channel B, channel C, and channel D include 2551 double-sided negative exponential signals in each channel. The double-sided negative exponential signals in each channel are then randomly superimposed to construct the input signals of the four channels based on the amplitude information.

[0110] In order to evaluate the applicability of the triangle-trapezoidal dual-channel shaping algorithm based on the present invention in processing pulse pileup, the signal with pulse pileup phenomenon is shaped by the traditional trapezoidal shaping algorithm and the triangle-trapezoidal dual-channel shaping algorithm respectively, and the peak values ​​of the unprocessed original input signal, the trapezoidal shaping signal shaped by the traditional trapezoidal shaping algorithm, and the triangle-trapezoidal shaping signal shaped by the triangle-trapezoidal dual-channel shaping algorithm are extracted. The number of peak signals extracted from each group of signals is shown in Table 1.

[0111] Table 1 Peak extraction comparison table

[0112]

[0113] It can be seen that due to pulse accumulation, the number of peak signals extracted from the unprocessed original input signal is small, and only 69.38% of the peak signals are identified. A large number of pulses carrying position information are not identified and discarded, and the final image quality is seriously damaged. The extraction rates of the traditional trapezoidal shaping algorithm and the triangle-trapezoidal dual-channel shaping algorithm of the present invention are 77.81% and 83.38% respectively. The triangle-trapezoidal dual-channel shaping algorithm effectively improves the counting rate of the piled pulses. Compared with not using any algorithm or relying only on the trapezoidal shaping algorithm, the counting rate of the triangle-trapezoidal dual-channel shaping algorithm is increased by 12.15% and 20.17% respectively, which effectively shortens the imaging time and improves the image quality.

[0114] Fig. 9 (a) is the original input image, Fig. 9 (b) is the imaging result of the original input signal. Fig. 9 (c) is the imaging result after shaping by the traditional trapezoidal shaping algorithm. Fig. 9(d) is the imaging result after shaping by the triangle-trapezoidal dual-channel shaping algorithm of the present invention. It can be seen that the original input signal can restore 1216 pixels, accounting for 47% of the total pixels, and the imaging effect is not ideal. The traditional trapezoidal shaping algorithm effectively improves the counting rate, but there are errors in amplitude extraction when the trapezoidal shaping signal is accumulated. Therefore, a large number of noise points appear in the image, and only 1472 pixels (accounting for 57% of the total pixels) are restored, resulting in unsatisfactory imaging quality. The triangle-trapezoidal shaping algorithm of the present invention effectively improves the counting rate and reduces the positioning error while accurately extracting the peak data, and finally restores 1852 pixels, accounting for 72.6% of the total pixels. Compared with the unprocessed signal and the signal processed by the trapezoidal shaping algorithm alone, the pixel recovery of the triangle-trapezoidal shaping algorithm is increased by 52.3% and 20.5%, respectively, achieving excellent image restoration effect and significantly improving image quality.

[0115] like Fig.10 As shown, the imaging diagram of the conventional electronic readout system is compared with that of the electronic readout system based on the triangle-trapezoidal dual-channel shaping algorithm of the present invention. The imaging resolution of the single-photon camera is measured using the currently commonly used USAF 1951 resolution test target. The imaging resolution of the single-photon camera of the conventional electronic readout system can reach 12.7 Line Pairs / mm. The electronic readout circuit of the present invention can effectively improve the imaging resolution of the single-photon camera to 20.1 Line Pairs / mm. Fig.10 The curve on the right side of the middle is an analysis of the image contrast by drawing a grayscale distribution diagram of a specific area (row 221, columns 137-159). The contrast of the traditional electronic readout system is low, with a measured value of 61.5%. The contrast of the electronic readout circuit of the present invention is significantly improved, reaching 90.9%, which enhances the visual effect and detail display of the image. In summary, adding the triangle-trapezoidal dual-channel shaping algorithm to the electronic readout system can effectively improve the resolution and contrast of the final image, thereby improving the image quality.

[0116] The above description is only used to illustrate the technical solution of the present invention rather than to limit it. For ordinary professional and technical personnel in the field, the specific technical solution recorded in the above embodiment can be modified, or some of the technical features therein can be replaced by equivalents, and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution protected by the present invention.

Claims

1. A resistor anode single-photon camera based on a triangle-trapezoidal dual-channel shaping algorithm, characterized in that: It comprises a resistor anode detector (1), an electronic readout system (2) and a host computer (3); the electronic readout system (2) comprises four charge-sensitive amplifier circuits (21), an ADC module and a signal processing unit; The input ends of the four charge-sensitive amplifier circuits (21) are respectively connected to the output ends of the resistor anode detector (1), and are used to convert the four charge signals output by the resistor anode detector (1) into corresponding voltage signals and amplify them; The four input ends of the ADC module are respectively connected to the output ends of four charge-sensitive amplifier circuits (21), and are used to collect four amplified voltage signals and convert them into corresponding digital signals for output respectively; The signal processing unit comprises four identical signal processing modules (23) and a position calculation module (24); the signal processing module (23) comprises a trapezoidal shaping module (231), a triangular shaping module (232), a baseline recovery module (233), a trapezoidal peak finding module (234), a triangular peak finding module (235), a signal delay module (236) and a peak output channel (237); The input ends of the trapezoidal shaping module (231) and the triangular shaping module (232) in each signal processing module (23) are correspondingly connected to an output end of the ADC module, so as to respectively perform trapezoidal shaping and triangular shaping on the digital signal output by the ADC module, and obtain corresponding trapezoidal shaping signals and triangular shaping signals; The two input ends of the baseline recovery module (233) are respectively connected to the output ends of the trapezoidal shaping module (231) and the triangular shaping module (232), and are used to perform baseline deviation recovery on the trapezoidal shaping signal and the triangular shaping signal; The input end of the triangular peak-finding module (235) is connected to the first output end of the baseline recovery module (233) and is used to extract the peak value and position of the triangular shaped signal; the first input end of the trapezoidal peak-finding module (234) is connected to the second output end of the baseline recovery module (233), and the second input end is connected to the position output end of the triangular peak-finding module (235) and is used to extract the peak value of the trapezoidal shaped signal according to the position information of the triangular shaped signal; The three input ends of the signal delay module (236) are respectively connected to the position output end and the peak output end of the triangle peak search module (235) and the peak output end of the trapezoidal peak search module (234) for signal synchronization; The three input ends of the peak output channel (237) are respectively connected to the peak output end of the triangular shaped signal, the position output end and the peak output end of the trapezoidal shaped signal in the signal delay module (236), and are used to judge the pulse accumulation situation according to the position information of the triangular shaped signal, and select to output the peak value of the triangular shaped signal or the peak value of the trapezoidal shaped signal or discard the current signal according to the pulse accumulation situation; The four input ends of the position calculation module (24) are respectively connected to the output ends of the four peak output channels (237) for calculating the position coordinates of the single photon according to the four peak values; the input end of the host computer (3) is connected to the output end of the position calculation module (24) for completing single photon imaging according to the position coordinates of the single photon.

2. The resistor anode single-photon camera based on the triangle-trapezoidal dual-channel shaping algorithm according to claim 1, characterized in that: The peak output channel (237) comprises a pulse interval calculation module (2371), a first comparison module (2372), a second comparison module (2373) and a decision output module (2374); The input end of the pulse interval calculation module (2371) is connected to the position output end of the triangular shaped signal of the signal delay module (236), and is used to calculate the adjacent pulse interval ΔT according to the position information of two adjacent triangular shaped pulses; The first input end of the first comparison module (2372) is connected to the output end of the pulse interval calculation module (2371), and the second input end is used to input the sum of the rise time and the flat top time t of the set trapezoidal shaping signal. b ; The first input terminal of the second comparison module (2373) is connected to the first output terminal of the first comparison module (2372), and the second input terminal is used to input the set rise time t of the trapezoidal shaping signal. a ; The four input ends of the judgment output module (2374) are respectively connected to the peak output end of the triangle shaping signal of the signal delay module (236), the peak output end of the trapezoidal shaping signal, the second output end of the first comparison module (2372) and the output end of the second comparison module (2373), and are used to determine the value of the judgment output module (2374) when ΔT≥t b When the peak value of the output trapezoidal shaped signal is a ≤ΔT<t b When ΔT<t a When , the current signal is discarded; The four input ends of the position calculation module (24) are respectively connected to the output ends of the corresponding decision output modules (2374) in the four signal processing modules (23).

3. The resistor anode single-photon camera based on the triangle-trapezoidal dual-channel shaping algorithm according to claim 2, characterized in that: The four peak output channels (237) corresponding to the four signal processing modules (23) are defined as channel A, channel B, channel C and channel D, and channel A is located at the upper left position of the signal processing unit, and channel B, channel C and channel D are arranged clockwise at intervals of 90 degrees. The position calculation module (24) calculates the position coordinates (x, y) of a single photon using the following formula: In the above formula, V A 、V B 、V C 、V D Respectively represent the peak values ​​of the outputs of channel A, channel B, channel C, and channel D.

4. The resistor anode single-photon camera based on the triangle-trapezoidal dual-channel shaping algorithm according to claim 3, characterized in that: The trapezoidal shaping module (231) is a high-order IIR filter, and its system function H(z) based on the Z domain is: in, Indicates that the signal is delayed by n a Sampling period, Indicates that the signal is delayed by n b Sampling period, z -1 Indicates that the signal is delayed by one sampling period, n a =t a / T s , n b =t b / T s , T s is the sampling period; τ1 is the fast time constant, τ2 is the slow time constant; The triangular shaping module (232) is a high-order IIR filter, and its system function H(z)′ based on the Z domain is:

5. The resistor anode single-photon camera based on the triangle-trapezoidal dual-channel shaping algorithm according to claim 4, characterized in that: The high-order IIR filter of the trapezoidal shaping module (231) is constructed by a four-stage cascade method, including a first-stage subsystem H1(z), a second-stage subsystem H2(z), a third-stage subsystem H3(z) and a fourth-stage subsystem H4(z), and the expressions thereof are as follows: Among them, n c =t c / T s , t c Indicates the duration of the pulse signal; The high-order IIR filter of the triangular shaping module (232) is constructed by a four-stage cascade method, including a first-stage subsystem H1(z)′, a second-stage subsystem H2(z)′, a third-stage subsystem H3(z)′ and a fourth-stage subsystem H4(z)′, and the expressions thereof are as follows:

6. The resistor anode single-photon camera based on the triangle-trapezoidal dual-channel shaping algorithm according to claim 5, characterized in that: The first-level subsystem H1(z) includes a delayer delay1, a delayer delay2, a delayer delay3, a subtractor sub1, a subtractor sub2, and an adder add1; The input ends of the delayer delay1, delayer delay2, and delayer delay3 are all connected to the corresponding output ends of the ADC module, and are used to delay the digital signal output by the ADC module by n. a 、n b 、n c The first input end of the subtractor sub1 is connected to the corresponding output end of the ADC module, and the second input end thereof is connected to the output end of the delay device delay1. The first input end of the subtractor sub2 is connected to the output end of the subtractor sub1, and the second input end thereof is connected to the output end of the delay device delay2. The first input end of the adder add1 is connected to the output end of the subtractor sub2, and the second input end thereof is connected to the output end of the delay device delay3, so as to make the first-level subsystem The second-level subsystem H2(z) includes a multiplier mux1, a delayer delay4 and a subtractor sub3; The input end of the multiplier mux1 is connected to the first output end of the adder add1, and the output end of the multiplier mux1 is connected to the input end of the delayer delay4. The output end of the delayer delay4 is connected to the first input end of the subtractor sub3, and the second input end of the subtractor sub3 is connected to the second output end of the adder add1, so that the second-level subsystem H2(z)=1-α1 -1 ; The third-level subsystem H3(z) includes a multiplier mux2, a delayer delay5 and a subtractor sub4; The input end of the multiplier mux2 is connected to the first output end of the subtractor sub3, and the output end of the multiplier mux2 is connected to the input end of the delayer delay5. The output end of the delayer delay5 is connected to the first input end of the subtractor sub4, and the second input end of the subtractor sub4 is connected to the second output end of the subtractor sub3, so as to make the third-level subsystem H3(z)=1-α2 -1 ; The fourth-level subsystem H4(z) includes an adder add2, an adder add3, a multiplier mux3, a delayer delay6 and a delayer delay7; The adder add2, adder add3, and multiplier mux3 are connected in sequence in the order of input and output. One input end of the adder add2 is connected to the output end of the subtractor sub4. The input end of the delayer delay6 is connected to the other output end of the adder add2, and its output end is connected to the other input end of the adder add2. The input end of the delayer delay7 is connected to the other output end of the adder add3, and its output end is connected to the other input end of the adder add3, so as to make the fourth-level subsystem The first-level subsystem H1(z)′ includes a delayer delay1′, a delayer delay2′, a delayer delay3′, a subtractor sub1′, a subtractor sub2′, and an adder add1′; The input ends of the delayer delay1′, the delayer delay2′ and the delayer delay3′ are all connected to the corresponding output ends of the ADC module, and are used to delay the digital signal output by the ADC module by n. a 、n a 、n c The first input end of the subtractor sub1′ is connected to the corresponding output end of the ADC module, and the second input end thereof is connected to the output end of the delay device delay1′. The first input end of the subtractor sub2′ is connected to the output end of the subtractor sub1′, and the second input end thereof is connected to the output end of the delay device delay2′. The first input end of the adder add1′ is connected to the output end of the subtractor sub2′, and the second input end thereof is connected to the output end of the delay device delay3′, so as to make the first-level subsystem The second-stage subsystem H2(z)′ includes a multiplier mux1′, a delayer delay4′ and a subtractor sub3′; The input end of the multiplier mux1′ is connected to the first output end of the adder add1′, and the output end of the multiplier mux1′ is connected to the input end of the delayer delay4′. The output end of the delayer delay4′ is connected to the first input end of the subtractor sub3′, and the second input end of the subtractor sub3′ is connected to the second output end of the adder add1′, so that the second-level subsystem H2(z)′=1-α1 -1 ; The third-level subsystem H3(z)′ includes a multiplier mux2′, a delayer delay5′ and a subtractor sub4′; The input end of the multiplier mux2′ is connected to the first output end of the subtractor sub3′, and the output end of the multiplier mux2′ is connected to the input end of the delayer delay5′. The output end of the delayer delay5′ is connected to the first input end of the subtractor sub4′, and the second input end of the subtractor sub4′ is connected to the second output end of the subtractor sub3′, so as to make the third-level subsystem H3(z)′=1-α2 -1 ; The fourth-level subsystem H4(z)′ includes an adder add2′, an adder add3′, a multiplier mux3′, a delayer delay6′ and a delayer delay7′; The adder add2′, adder add3′, and multiplier mux3′ are connected in sequence in the order of input and output. The input end of the adder add2′ is connected to the output end of the subtractor sub4′, the input end of the delayer delay6′ is connected to the other output end of the adder add2′, and the output end thereof is connected to the other input end of the adder add2′. The input end of the delayer delay7′ is connected to the other output end of the adder add3′, and the output end thereof is connected to the other input end of the adder add3′, so as to make the fourth-level subsystem 7. The resistor anode single-photon camera based on the triangle-trapezoidal dual-channel shaping algorithm according to claim 6, characterized in that: The ADC module includes two ADC acquisition circuits (22); Two input ends of an ADC acquisition circuit (22) are respectively connected to the output ends of two charge-sensitive amplifier circuits (21); a first output end is respectively connected to the input ends of a delayer delay1, a delayer delay2, a delayer delay3, a subtractor sub1, a delayer delay1′, a delayer delay2′, a delayer delay3′, and a subtractor sub1′ in a first signal processing module (23); and a second output end is respectively connected to the input ends of a delayer delay1, a delayer delay2, a delayer delay3, a subtractor sub1, a delayer delay1′, a delayer delay2′, a delayer delay3′, and a subtractor sub1′ in a second signal processing module; The two input ends of another ADC acquisition circuit (22) are respectively connected to the output ends of the other two charge-sensitive amplifier circuits (21); the first output end is respectively connected to the input ends of the delay device delay1, delay device delay2, delay device delay3, subtractor sub1, delay device delay1′, delay device delay2′, delay device delay3′, and subtractor sub1′ in the third signal processing module (23); and the second output end is respectively connected to the input ends of the delay device delay1, delay device delay2, delay device delay3, subtractor sub1, delay device delay1′, delay device delay2′, delay device delay3′, and subtractor sub1′ in the fourth signal processing module.

8. The resistor anode single-photon camera based on the triangle-trapezoidal dual-channel shaping algorithm according to claim 1, characterized in that: The signal processing unit is constructed based on FPGA.

9. The resistor anode single-photon camera based on the triangle-trapezoidal dual-channel shaping algorithm according to claim 8, characterized in that: The trapezoidal shaping module (231) and the triangular shaping module (232) are both implemented by algorithms using System Generator software.

Images