Bonding structure and manufacturing method of bonding structure
By arranging a smaller first bonding pad on the conductive pillar, the size of the conductive pillar is at least three times the size of the first bonding pad, which solves the problem of the pulling force of the expansion of the metal pillar on the bonding pad, and improves the Bond strength and quality of semiconductor structures.
Patent Information
- Application Number
- CN202411412015.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-10
- Publication Date
- 2025-01-24
- Estimated Expiration
- 2044-10-10
AI Technical Summary
During semiconductor manufacturing, during the bonding process between metal columns and pads, the expansion of the metal columns is large, resulting in a large tension on the edge of the pad, which in turn causes the pad to deform or crack, affecting the bonding surface rate and circuit reliability.
By setting up a small first -button pad on the conductive column, the size of the electrical column is at least three times the size of the first -button pad. During the bonding process, the stress is concentrated in the center of the pad to reduce the pull on the edge of the pad.
It improves the key concentration and key quality between the first semiconductor structure and other semiconductor structures, reducing the risk of pad deformation and cracking, and reducing the manufacturing cost.
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Figure CN119361440A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a bonding structure and a method for manufacturing the bonding structure. Background Art
[0002] In the related art, 3D stacking between wafers needs to be achieved through the bonding of the metal pillar in the silicon through via in one wafer and the pad on another wafer. However, during the bonding process of the metal pillar and the pad, the metal pillar expands significantly. Moreover, since the size of the pad is basically the same as that of the metal pillar, the stress distribution of the metal pillar on the pad is uniform, resulting in a large tensile force on the edge of the pad, which causes the pad to deform or even crack, thereby affecting the yield of the bonding surface and the reliability of the circuit. Summary of the invention
[0003] In view of this, embodiments of the present disclosure provide a bonding structure and a method for manufacturing the bonding structure.
[0004] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:
[0005] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a bonding structure, the method comprising: providing a first semiconductor structure, the first semiconductor structure comprising a conductive column extending inward from a bonding surface of a first semiconductor layer; forming a first bonding layer on the bonding surface of the first semiconductor layer; the first bonding layer comprising a first bonding pad, the first bonding pad being in direct contact with the conductive column, and a size of the conductive column being at least three times a size of the first bonding pad.
[0006] In some embodiments, the first bonding layer also includes: a first dummy pad extending from the surface of the first bonding layer into the first bonding layer; the orthographic projection of the first dummy pad in the thickness direction of the first semiconductor structure and the orthographic projection of the conductive column in the thickness direction of the first semiconductor structure do not overlap.
[0007] In some embodiments, the surface of the conductive column close to the first bonding layer includes a first region and a second region, the thermal expansion rate of the first region is greater than the thermal expansion rate of the second region; and the first bonding pad is located on the second region.
[0008] In some embodiments, a plurality of the first bonding pads are disposed on the second region, and the plurality of the first bonding pads are distributed at equal intervals along the circumference of the conductive pillar.
[0009] In some embodiments, a plurality of the first bonding pads are disposed on the second region, and the plurality of the first bonding pads have different sizes.
[0010] In some embodiments, a first dielectric layer is further included between the first semiconductor layer and the first bonding layer; and the conductive pillar also penetrates the first dielectric layer.
[0011] In a second aspect, an embodiment of the present disclosure provides a bonding structure, comprising a first bonding structure and a second bonding structure; the first bonding structure comprises a first semiconductor structure and a first bonding layer; the first semiconductor structure comprises a conductive column extending inward from a bonding surface of the first semiconductor layer, the first bonding layer comprises a first bonding pad, the first bonding pad is in direct contact with the conductive column, and a size of the conductive column is at least three times a size of the first bonding pad; the second bonding structure comprises a second semiconductor structure and a second bonding layer, the second bonding layer comprises a second bonding pad; the first bonding pad is bonded to the second bonding pad.
[0012] In some embodiments, the first bonding layer also includes: a first dummy pad extending from the surface of the first bonding layer to the first bonding layer; the second bonding layer also includes: a second dummy pad extending from the surface of the second bonding layer to the second bonding layer, the first dummy pad is bonded to the second dummy pad; the orthographic projection of the first dummy pad in the thickness direction of the first semiconductor structure and the orthographic projection of the conductive column in the thickness direction of the first semiconductor structure do not overlap.
[0013] In some embodiments, the surface of the conductive column close to the first bonding layer includes a first region and a second region, the thermal expansion rate of the first region is greater than the thermal expansion rate of the second region; and the first bonding pad is in direct contact with the second region.
[0014] In some embodiments, a plurality of the first bonding pads are disposed on the second region, and the plurality of the first bonding pads are distributed at equal intervals along the circumference of the conductive column.
[0015] In some embodiments, a plurality of the first bonding pads are disposed on the second region, and the plurality of the first bonding pads have different sizes.
[0016] In some embodiments, a size of the first bonding pad is smaller than a size of the second bonding pad.
[0017] The embodiment of the present disclosure provides a bonding structure and a manufacturing method of the bonding structure, the manufacturing method comprising: providing a first semiconductor structure, the first semiconductor structure comprising a conductive column extending inward from a bonding surface of a first semiconductor layer; forming a first bonding layer on the bonding surface of the first semiconductor layer; the first bonding layer comprising a first bonding pad, the first bonding pad being in direct contact with the conductive column, and the size of the conductive column being at least three times the size of the first bonding pad. The embodiment of the present disclosure provides a first bonding pad with a smaller size on the conductive column, so that the first semiconductor structure can be bonded to other semiconductor structures through the first bonding pad, and the conductive column expands during the bonding process to generate stress on the first bonding pad, but because the size of the first bonding pad is smaller, the first bonding pad has a higher stability, and the stress of the conductive column on the first bonding pad can be concentrated at the center of the first bonding pad, thereby reducing the pulling of the stress on the edge of the first bonding pad, so that the first bonding pad is not easily deformed during the bonding process, which is conducive to improving the bonding strength and bonding quality between the first semiconductor structure and the other semiconductor structure, and the manufacturing method of the bonding structure provided by the embodiment of the present disclosure has simple steps and can reduce the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 A schematic structural diagram of a bonding structure in a related technology provided by the present disclosure;
[0019] Figure 2 A schematic diagram of the steps of a method for manufacturing a bonding structure provided in an embodiment of the present disclosure;
[0020] Figure 3a to Figure 3b A schematic diagram of the structure during the manufacturing process of the bonding structure provided in the embodiment of the present disclosure;
[0021] Figure 4 A top view of a conductive column provided in an embodiment of the present disclosure;
[0022] Figure 5a A top view of a first bonding pad and a conductive column provided in an embodiment of the present disclosure Figure 1 ;
[0023] Figure 5b A top view of a first bonding pad and a conductive column provided in an embodiment of the present disclosure Figure 2 ;
[0024] Figure 5c A third top view of a first bonding pad and a conductive column provided in an embodiment of the present disclosure;
[0025] Figure 5d A top view of a first bonding pad and a conductive column provided in an embodiment of the present disclosure Figure 4 ;
[0026] Figure 5e A top view 5 of a first bonding pad and a conductive column provided in an embodiment of the present disclosure;
[0027] Figure 6 A structural schematic diagram of a bonding structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0028] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.
[0029] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.
[0030] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.
[0031] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.
[0032] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0034] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.
[0035] Figure 1 The schematic diagram of the bonding structure in the related art provided by the present disclosure is shown in FIG. Figure 1As shown, the bonding structure includes a first semiconductor device 110 and a second semiconductor device 120. The first semiconductor device 110 includes a metal column 111 disposed therethrough. A first insulating layer 130 is further disposed on the first semiconductor device 110. The first insulating layer 130 includes a metal wiring 131 electrically connected to the metal column 111 and a first pad 132 electrically connected to the first metal wiring 131. The first pad 132 is exposed on the surface of the first insulating layer 130. A second insulating layer 140 is disposed on the second semiconductor device 120. The second insulating layer 140 includes a second metal wiring 141 and a second pad 142 electrically connected to the second metal wiring 141. The second pad 142 is exposed on the surface of the second insulating layer 140. The first pad 132 and the second pad 142 are bonded together by hybrid bonding. It can be understood that when the metal column and the second pad are directly hybrid bonded, the second pad is lifted due to the thermal expansion of the metal column, resulting in low strength of the bonding surface between the first semiconductor device and the second semiconductor device, and even an open circuit between the first semiconductor device and the second semiconductor device. For this reason, the related art solves the problem caused by direct hybrid bonding between the metal column and the second pad by arranging the first metal wiring 131 and the first pad 132 on the metal column 111 and bonding the first pad 132 and the second pad 142 together. However, this method still has the following problems, specifically:
[0036] See also Figure 1 The enlarged view of the local area between the first metal wiring 131 and the metal pillar 111 is shown. During the hybrid bonding process, the metal pillar 111 expands and bulges due to heat, causing stress concentration at the connection position 151 between the first metal wiring 131 and the metal pillar 111, which may cause damage to the first insulating layer 130 and the first metal wiring 131, and affect the communication speed between the first semiconductor device 110 and the second semiconductor device 120.
[0037] See also Figure 1 As shown in the enlarged view of the part between the first pad 132 and the second pad 142, during the hybrid bonding process, the first pad 132 and the second pad 142 expand due to heat and metal extrusion phenomenon 152 occurs, which affects the bonding quality and causes insufficient bonding strength; if the pad density is high, the metal extrusion phenomenon may also cause the connection between adjacent pads to cause a short circuit problem.
[0038] In view of this, an embodiment of the present disclosure provides a method for manufacturing a bonding structure, the method comprising: providing a first semiconductor structure, the first semiconductor structure comprising a conductive column extending inward from a bonding surface of a first semiconductor layer; forming a first bonding layer on the bonding surface of the first semiconductor layer; the first bonding layer comprising a first bonding pad, the first bonding pad being in direct contact with the conductive column, and a size of the conductive column being at least three times a size of the first bonding pad.
[0039] In the method for preparing the bonding structure provided by the embodiment of the present disclosure, a hard mask (HM) is only required when forming the conductive pillar and the first bonding pad. Figure 1 The related technology shown can save two hard masks for forming metal wiring, which can effectively reduce the manufacturing cost; and because the size of the conductive column is at least three times the size of the first bonding pad, that is, the size of the first bonding pad is smaller, the stability of the first bonding pad is higher, and the stress of the conductive column on the first bonding pad can be concentrated at the center of the first bonding pad, thereby reducing the pulling of the stress on the edge of the first bonding pad, so that the first bonding pad is not easy to deform during the bonding process, which is conducive to improving the bonding strength and bonding quality between the first semiconductor structure and the other semiconductor structure. In addition, when the first bonding pad is bonded to the pads on the other semiconductor structures, due to the smaller size of the first bonding pad, the metal extrusion phenomenon between the first bonding pad and the pads on the other semiconductor structures is also significantly improved.
[0040] It should be noted that the first semiconductor structure may be a wafer, a package or other semiconductor devices.
[0041] Figure 2 A schematic diagram of the steps of a method for manufacturing a bonding structure provided in an embodiment of the present disclosure. Figure 2 As shown, the method for manufacturing the bonding structure includes the following steps:
[0042] Step 210: Provide a first semiconductor structure, wherein the first semiconductor structure includes a conductive pillar extending inwardly from a bonding surface of a first semiconductor layer.
[0043] Step 220: forming a first bonding layer on the bonding surface of the first semiconductor layer; the first bonding layer includes a first bonding pad, the first bonding pad is in direct contact with the conductive column, and the size of the conductive column is at least three times the size of the first bonding pad.
[0044] It should be understood that Figure 2 The steps shown are not exclusive, and other steps may be performed before, after, or between any steps in the shown operations.
[0045] Figure 3a to Figure 3b This is a schematic diagram of the structure of the bonding structure provided in the embodiment of the present disclosure during the manufacturing process. It should be noted that: Figure 3a to Figure 3b This is a complete schematic diagram of the manufacturing method of the bonding structure. The unmarked parts in some figures can be shared with each other. Figure 2 as well as Figure 3a to Figure 3b , the manufacturing method of the bonding structure provided by the embodiment of the present disclosure is described in detail.
[0046] It should be noted that, for the convenience of description, various directions that may be used in the following description are first defined. The thickness direction of the first semiconductor structure is defined as a vertical direction (i.e., the Z direction in the figure). In a plane perpendicular to the Z direction, intersecting X and Y directions are defined, and the X, Y, and Z directions may be perpendicular to each other.
[0047] In some embodiments, a first dielectric layer is further included between the first semiconductor layer and the first bonding layer; and the conductive pillar further penetrates the first dielectric layer.
[0048] See also Figure 3a to Figure 3b , the preparation process of the bonding structure 300 is as follows:
[0049] See also Figure 3a The preparation process of the first semiconductor structure includes: providing an initial first semiconductor structure, the initial first semiconductor structure includes a first semiconductor layer 311, and depositing a dielectric material on the first semiconductor layer 311 to form a first dielectric layer 312. It should be noted that the dielectric material includes but is not limited to silicon-based materials, polymer materials and other high dielectric constant materials, such as silicon oxide, epoxy resin or polyimide.
[0050] A first mask layer (not shown in the figure) is formed on the first dielectric layer 312, and the first dielectric layer 312 and the first semiconductor layer 311 are etched in sequence using the first mask layer to form a through hole that penetrates the first dielectric layer 312 and extends to the inside of the first semiconductor layer 311, and then the first mask layer is removed and a conductive material is deposited in the through hole to form a conductive pillar 313. It should be noted that the first semiconductor layer 311 may include a device structure and / or an interconnection structure, and the conductive pillar 313 extends inward from the bonding surface of the first semiconductor layer 311 and is connected to the device structure and / or the interconnection structure.
[0051] The conductive material includes but is not limited to tungsten, cobalt, copper, aluminum, doped polysilicon, doped monocrystalline silicon, silicide and any combination thereof. The first mask layer includes a mask material, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or any combination thereof.
[0052] In some embodiments, a first dielectric layer and / or an unremoved first mask layer may be included between the first semiconductor layer and the first bonding layer, and the conductive pillar may penetrate the first mask layer and / or the first dielectric layer.
[0053] In some embodiments, the first bonding layer 320 also includes: a first dummy pad 322 extending from the surface of the first bonding layer 320 to the first bonding layer 320; the orthographic projection of the first dummy pad 322 in the thickness direction of the first semiconductor structure and the orthographic projection of the conductive column 313 in the thickness direction of the first semiconductor structure do not overlap.
[0054] See also Figure 3b The preparation process of the first bonding layer 320 includes: depositing an insulating material on the first semiconductor structure, and forming a second mask layer (not shown in the figure) on the insulating material, etching the insulating material using the second mask layer to form a first groove and a second groove, wherein the first groove exposes the surface of the conductive column 313, and the orthographic projection of the second groove in the Z direction does not overlap with the orthographic projection of the conductive column 313 in the Z direction, and the second groove may not penetrate the insulating material; then removing the second mask layer and depositing a conductive material in the first groove and the second groove to form a first bonding pad 321 and a first dummy pad 322, so that the orthographic projection of the first bonding pad 321 in the Z direction overlaps with the orthographic projection of the conductive column 313 in the Z direction, and the orthographic projection of the first dummy pad 322 in the Z direction does not overlap with the orthographic projection of the conductive column 313 in the Z direction. The insulating material includes but is not limited to silicon-based materials, polymer materials and other high dielectric constant materials, such as silicon oxide, epoxy resin or polyimide.
[0055] In some embodiments, when the first dielectric layer 312 includes a rewiring structure, the first bonding layer 320 may further include other pads electrically connected to the rewiring structure, and the rewiring structure in the first dielectric layer 312 may be connected to the device structure in the first semiconductor layer 311, so that signal transmission between the first semiconductor structure and other semiconductor structures can be achieved through the rewiring structure in the first dielectric layer 312 and the other pads in the first bonding layer 320.
[0056] In some embodiments, when the conductive pillar 313 is connected to the device structure in the first semiconductor layer 311 , signal transmission between the first semiconductor structure and other semiconductor structures can be achieved through the first bonding pad 321 and the conductive pillar 313 .
[0057] In some embodiments, the first dummy pad is disposed in the first bonding layer, and the first dummy pad can be distributed in the first bonding layer at a similar spacing to the first bonding pad on the conductive pillar to improve the uniformity of the first bonding layer, and can reduce bonding defects such as cracks, cavities or delamination caused by local stress concentration or uneven thermal stress in the first bonding layer, so as to achieve the effect of improving the bonding strength and bonding quality between the first semiconductor structure and other semiconductor structures. It should be noted that the first dummy pad is not used to transmit signals.
[0058] It should be noted that the first dielectric layer, the first semiconductor layer and the insulating material can be etched by a plasma dry etching process, a gas reaction dry etching process or a wet etching process. The first dielectric layer, the conductive pillar and the first bonding layer can be formed by a physical vapor deposition (PVD, Physical Vapor Deposition) process, a chemical vapor deposition (CVD, Chemical Vapor Deposition) process or an atomic layer deposition (ALD, Atomic Layer Deposition) process.
[0059] It should be noted that the dielectric material and the insulating material may be the same or different.
[0060] In some embodiments, the surface of the conductive column close to the first bonding layer includes a first region and a second region, the thermal expansion rate of the first region is greater than the thermal expansion rate of the second region; and the first bonding pad is located on the second region.
[0061] Figure 4 FIG. 1 is a top view of a conductive column provided in an embodiment of the present disclosure. Figure 4 As shown, the surface of the conductive column close to the first bonding layer includes a first region 314 and a second region 315. Since the heat of the conductive column is dissipated from the center to the outside along its radial direction, the heat of the first region 314 is dissipated slower than the heat of the second region 315. Therefore, the thermal expansion rate of the first region 314 is greater than the thermal expansion rate of the second region 315, and thus the stress of the second region 315 on the first bonding pad is smaller. Therefore, setting the first bonding pad on the second region 315 can further reduce the influence of stress on the first bonding pad, which is beneficial to improving the bonding strength and bonding quality between the first semiconductor structure and other semiconductor structures.
[0062] It should be noted that the orthographic projection of the conductive pillar in the thickness direction of the first semiconductor structure may be any shape, such as a circle or a rectangle, and the embodiment of the present disclosure does not impose any limitation on the number of the conductive pillars.
[0063] In some embodiments, when the first semiconductor structure includes a plurality of conductive pillars, the number, shape, and size of the first bonding pads on each conductive pillar may be the same or different.
[0064] In some embodiments, a plurality of first bonding pads are disposed on the second region, and the plurality of first bonding pads are distributed at equal intervals along the circumference of the conductive pillar.
[0065] Figure 5a A top view of a first bonding pad and a conductive column provided in an embodiment of the present disclosure Figure 1 ; Figure 5b A top view of a first bonding pad and a conductive column provided in an embodiment of the present disclosure Figure 2 ; Figure 5c A third top view of a first bonding pad and a conductive column provided in an embodiment of the present disclosure; Figure 5d A top view of a first bonding pad and a conductive column provided in an embodiment of the present disclosure Figure 4 ; Figure 5e FIG5 is a top view of a first bonding pad and a conductive column provided in an embodiment of the present disclosure.
[0066] like Figure 5a As shown, two first bonding pads 3211 are disposed on the second region 315, and the distance between the two first bonding pads 3211 and the edge of the first region 314 is equal. Figure 5b As shown, three first bonding pads 3212 are disposed on the second region 315, and the three first bonding pads 3212 can be respectively located at three corners of an equilateral triangle, so that the three first bonding pads 3212 are distributed in the second region 315 at equal intervals. Figure 5c As shown, four first bonding pads 3213 are disposed on the second region 315 , and the four first bonding pads 3213 may be respectively located at four corners of a square, so that the four first bonding pads 3213 are distributed on the second region 315 at equal intervals.
[0067] In some embodiments, at least one group of first bonding pads distributed at equal intervals along the circumference of the conductive pillar may be disposed on the second region.
[0068] like Figure 5d As shown, four first bonding pads 3214a and four first bonding pads 3214b are arranged on the second region 315, the distance between the first bonding pad 3214a and the edge of the first region 314 is d1, and the four first bonding pads 3214a are arranged on the four corners of the square; the distance between the first bonding pad 3214b and the edge of the first region 314 is d2, and the four first bonding pads 3214b are arranged on the four corners of the square, and d1 is smaller than d2 and the first bonding pad 3214a and the first bonding pad 3214b do not overlap, so that two groups of first bonding pads 3214a and 3214b distributed at equal intervals along the circumference of the conductive column can be arranged on the second region 315. Figure 5eAs shown, eight first bonding pads 3215a and four first bonding pads 3215b are arranged on the second area 315, the spacing between the first bonding pad 3215a and the edge of the first area 314 is d3, and the eight first bonding pads 3215a are arranged on the eight corners of a regular octagon; the spacing between the first bonding pad 3215b and the edge of the first area 314 is d4, and the four first bonding pads 3215b are arranged on the four corners of a square, in addition, d3 is smaller than d4 and the first bonding pad 3215a does not overlap with the first bonding pad 3215b, so that two groups of first bonding pads 3215a and 3215b distributed at equal intervals along the circumference of the conductive column can be arranged on the second area 315.
[0069] In some embodiments, the first bonding pads do not need to be strictly distributed at equal intervals along the circumference of the conductive pillar, that is, the intervals between the multiple first bonding pads on the conductive pillar only need to be substantially the same.
[0070] It should be noted that the embodiment of the present disclosure does not impose any restriction on the number of first bonding pads on the second region.
[0071] In some embodiments, a plurality of first bonding pads are disposed on the second region, and the plurality of first bonding pads have different sizes.
[0072] In some embodiments, the shapes and / or areas of the orthographic projections of the plurality of first bonding pads on the second region in the Z direction may be the same or different.
[0073] It should be noted that the orthographic projection of the first bonding pad in the Z direction may be any shape, such as a circle or a rectangle.
[0074] Figure 6 A structural schematic diagram of a bonding structure provided in an embodiment of the present disclosure. Figure 6 Taking the bonding structure including two second bonding structures as an example, the bonding structure includes a first bonding structure 61 and a second bonding structure 63; the first bonding structure 61 includes a first semiconductor structure and a first bonding layer 620; the first semiconductor structure includes a conductive column 613 extending inward from the bonding surface of the first semiconductor layer 611, the first bonding layer 620 includes a first bonding pad 621, the first bonding pad 621 is in direct contact with the conductive column 613, and the size of the conductive column 613 is at least three times the size of the first bonding pad 621; the second bonding structure 63 includes a second semiconductor structure and a second bonding layer 640, the second bonding layer 640 includes a second bonding pad 641; the first bonding pad 621 is bonded to the second bonding pad 641.
[0075] The bonding structure provided in the embodiment of the present disclosure bonds the first bonding structure and the second bonding structure together through a first bonding pad and a second bonding pad of smaller size, thereby avoiding the influence of the expansion of the conductive column on the bonding surface during the hybrid bonding process, and realizing a bonding structure with good bonding strength and bonding quality.
[0076] It should be noted that the first semiconductor structure and the second semiconductor structure may be wafers, packages or other semiconductor devices. The present disclosure does not impose any restriction on the number of the second bonding structures.
[0077] In some embodiments, the first semiconductor structure may further include a first dielectric layer 612, the first dielectric layer 612 is disposed between the first semiconductor layer 611 and the first bonding layer 620, and the conductive pillar 613 penetrates the first dielectric layer 612 and extends into the first semiconductor layer 611. It should be noted that the first semiconductor layer 611 may include a device structure and / or an interconnection structure, and the conductive pillar 613 extends inward from the bonding surface of the first semiconductor layer 611 and is connected to the device structure and / or the interconnection structure.
[0078] In some embodiments, the second semiconductor structure includes a second semiconductor layer 631, a second dielectric layer 632, and a second bonding layer 640. The second semiconductor layer 631 may include a device structure and / or an interconnection structure. The second dielectric layer 632 may include a rewiring structure. The second dielectric layer 632 is disposed between the second semiconductor layer 631 and the second bonding layer 640. The second bonding pad 641 may be connected to the device structure and / or the interconnection structure in the second semiconductor layer 631 through the rewiring structure in the second dielectric layer 632. It should be noted that the second bonding layer 640 includes an insulating material and a pad disposed in the insulating material.
[0079] In some embodiments, when the first dielectric layer 612 includes a rewiring structure, the first bonding layer 620 may also include other pads electrically connected to the rewiring structure, and the rewiring structure in the first dielectric layer 612 may be connected to the device structure in the first semiconductor layer 611, so that signal transmission between the first bonding structure and the second bonding structure can be achieved through the rewiring structure in the first dielectric layer 612 and the other pads in the first bonding layer 620.
[0080] In some embodiments, when the conductive pillar 613 is connected to the device structure in the first semiconductor layer 611 , signal transmission between the first bonding structure and the second bonding structure can be achieved through the first bonding pad 621 and the conductive pillar 613 .
[0081] It should be noted that the materials of the first dielectric layer, the second dielectric layer, the first bonding layer and the second bonding layer include but are not limited to silicon-based materials, polymer materials and other high dielectric constant materials, such as silicon oxide, epoxy resin or polyimide. The materials of the conductive pillar, the first bonding pad and the second bonding pad include but are not limited to tungsten, cobalt, copper, aluminum, doped polysilicon, doped single crystal silicon, silicide and any combination thereof.
[0082] In some embodiments, the first bonding layer 620 also includes: a first dummy pad 622 extending from the surface of the first bonding layer 620 to the first bonding layer 620; the second bonding layer 640 also includes: a second dummy pad 642 extending from the surface of the second bonding layer 640 to the second bonding layer 640, and the first dummy pad 622 is bonded to the second dummy pad 642; the orthographic projection of the first dummy pad 622 in the thickness direction of the first semiconductor structure and the orthographic projection of the conductive column 613 in the thickness direction of the first semiconductor structure do not overlap.
[0083] In some embodiments, a first dummy pad 622 is disposed in the first bonding layer 620, and a second dummy pad 642 is disposed in the second bonding layer 640, and the orthographic projection of the first dummy pad 622 in the Z direction overlaps with the orthographic projection of the second dummy pad in the Z direction. The first dummy pad 622 is bonded to the second dummy pad 642.
[0084] In the disclosed embodiment, the first dummy pad can be distributed in the first bonding layer at a similar spacing to the first bonding pad on the conductive column, and the second dummy pad can be distributed in the second bonding layer at a similar spacing to the second bonding pad, so as to improve the uniformity of the first bonding layer and the second bonding layer, and reduce bonding defects such as cracks, cavities or delamination caused by local stress concentration or uneven thermal stress in the bonding surface, so as to improve the bonding strength and bonding quality between the first bonding structure and the second bonding structure. It should be noted that the first dummy pad and the second dummy pad are not used to transmit signals.
[0085] If necessary, the materials of the first dummy pad and the second dummy pad include but are not limited to tungsten, cobalt, copper, aluminum, doped polysilicon, doped monocrystalline silicon, silicide and any combination thereof. The disclosed embodiment does not impose any restriction on the number of the first dummy pad and the second dummy pad.
[0086] In some embodiments, the surface of the conductive column close to the first bonding layer includes a first region and a second region, the thermal expansion rate of the first region is greater than the thermal expansion rate of the second region; and the first bonding pad is in direct contact with the second region.
[0087] The surface of the conductive column close to the first bonding layer includes a first area and a second area. Since the heat of the conductive column is dissipated from the center to the outside along its radial direction, the heat of the first area is dissipated slower than the heat of the second area. Therefore, the thermal expansion rate of the first area is greater than the thermal expansion rate of the second area. Therefore, the stress of the second area on the first bonding pad is smaller. Therefore, setting the first bonding pad on the second area can further reduce the influence of stress on the first bonding pad, which is beneficial to improving the bonding strength and bonding quality between the first bonding structure and the second bonding structure.
[0088] It should be noted that the orthographic projection of the conductive pillar in the Z direction may be any shape, such as a circle or a rectangle, and the embodiment of the present disclosure does not impose any limitation on the number of the conductive pillars.
[0089] In some embodiments, when the first bonding structure includes a plurality of conductive pillars, the number, shape, and size of the first bonding pads on each conductive pillar may be the same or different.
[0090] In some embodiments, a plurality of first bonding pads are disposed on the second region, and the plurality of first bonding pads are distributed at equal intervals along the circumference of the conductive pillar.
[0091] In some embodiments, the first bonding pads do not need to be strictly distributed at equal intervals along the circumference of the conductive pillar, that is, the intervals between the multiple first bonding pads on the conductive pillar only need to be substantially the same.
[0092] It should be noted that the embodiment of the present disclosure does not impose any restriction on the number of first bonding pads on the second region.
[0093] In some embodiments, a plurality of first bonding pads 621 are disposed on the second region, and the plurality of first bonding pads 621 have different sizes.
[0094] In some embodiments, the shapes and / or areas of the orthographic projections of the plurality of first bonding pads on the second region in the Z direction may be the same or different.
[0095] It should be noted that the orthographic projection of the first bonding pad in the Z direction may be any shape, such as a circle or a rectangle.
[0096] In some embodiments, a size of the first bonding pad 621 is smaller than a size of the second bonding pad 641 .
[0097] In some embodiments, the size of the second bonding pad 641 is at least three times that of the first bonding pad 621 , and the size of the second bonding pad 641 is substantially the same as that of the conductive pillar 613 .
[0098] In some embodiments, the second bonding pad and the second dummy pad in the second bonding layer may have similar sizes and shapes. The surface of the pad in the second bonding layer (including the second bonding pad and the second dummy pad) close to the first bonding layer includes a third region and a fourth region, and the thermal expansion rate of the third region is greater than the thermal expansion rate of the fourth region. Since the heat of the pad is dissipated from the center to the outside along its radial direction, the heat of the third region is dissipated slower than the heat of the fourth region, so the thermal expansion rate of the third region is greater than the thermal expansion rate of the fourth region. In order to avoid the metal extrusion phenomenon caused by the excessive expansion rate of the third region, the first bonding pad is bonded to the fourth region of the second bonding pad, and the first dummy pad is bonded to the fourth region of the second dummy pad.
[0099] In some embodiments, the second dummy pad may be in direct contact with the plurality of first dummy pads, and the plurality of first dummy pads may be distributed at similar intervals along a circumference of the second dummy pad.
[0100] It should be noted here that the description of the above bonding structure is similar to the description of the embodiment of the manufacturing method of the above bonding structure, and has similar beneficial effects as the embodiment of the manufacturing method of the bonding structure. For technical details not disclosed in the embodiment of the bonding structure disclosed in the present invention, please refer to the description of the embodiment of the manufacturing method of the bonding structure disclosed in the present invention for understanding.
[0101] The embodiment of the present disclosure provides a bonding structure and a manufacturing method of the bonding structure, the manufacturing method comprising: providing a first semiconductor structure, the first semiconductor structure comprising a conductive column extending inward from a bonding surface of a first semiconductor layer; forming a first bonding layer on the bonding surface of the first semiconductor layer; the first bonding layer comprising a first bonding pad, the first bonding pad being in direct contact with the conductive column, and the size of the conductive column being at least three times the size of the first bonding pad. The embodiment of the present disclosure provides a first bonding pad with a smaller size on the conductive column, and the first semiconductor structure can be bonded to other semiconductor structures through the first bonding pad. The conductive column expands during the bonding process to generate stress on the first bonding pad, but because the size of the first bonding pad is smaller, the stability of the first bonding pad is higher, and the stress of the conductive column on the first bonding pad can be concentrated at the center of the first bonding pad, thereby reducing the pulling of the stress on the edge of the first bonding pad, so that the first bonding pad is not easily deformed during the bonding process, which is conducive to improving the bonding strength and bonding quality between the first semiconductor structure and the other semiconductor structure, and the manufacturing method of the bonding structure provided by the embodiment of the present disclosure has simple steps and can reduce the manufacturing cost. In addition, when the first bonding pad is bonded to pads on other semiconductor structures, the metal extrusion phenomenon between the first bonding pad and pads on other semiconductor structures is also significantly improved due to the small size of the first bonding pad.
[0102] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.
[0103] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.
Claims
1. A method for manufacturing a bonding structure, characterized in that: The method comprises: providing a first semiconductor structure comprising a conductive pillar extending inwardly from a bonding surface of a first semiconductor layer; forming a first bonding layer on the bonding surface of the first semiconductor layer; The first bonding layer includes a first bonding pad, the first bonding pad is in direct contact with the conductive pillar, and a size of the conductive pillar is at least three times a size of the first bonding pad.
2. The manufacturing method according to claim 1, characterized in that: The first bonding layer also includes: a first dummy pad extending from the surface of the first bonding layer into the first bonding layer; the orthographic projection of the first dummy pad in the thickness direction of the first semiconductor structure and the orthographic projection of the conductive column in the thickness direction of the first semiconductor structure do not overlap.
3. The manufacturing method according to claim 1, characterized in that: The surface of the conductive pillar close to the first bonding layer includes a first region and a second region, and the thermal expansion rate of the first region is greater than the thermal expansion rate of the second region; The first bonding pad is located on the second region.
4. The manufacturing method according to claim 3, characterized in that: A plurality of the first bonding pads are disposed on the second region, and the plurality of the first bonding pads are distributed at equal intervals along the circumference of the conductive column.
5. The manufacturing method according to claim 3, characterized in that: A plurality of the first bonding pads are disposed on the second region, and the plurality of the first bonding pads have different sizes.
6. The manufacturing method according to claim 1, characterized in that: A first dielectric layer is further provided between the first semiconductor layer and the first bonding layer; and the conductive pillar also penetrates the first dielectric layer.
7. A bonding structure, characterized in that: comprising a first bonding structure and a second bonding structure; The first bonding structure includes a first semiconductor structure and a first bonding layer; The first semiconductor structure includes a conductive pillar extending inwardly from a bonding surface of the first semiconductor layer, the first bonding layer includes a first bonding pad, the first bonding pad is in direct contact with the conductive pillar, and a size of the conductive pillar is at least three times a size of the first bonding pad; The second bonding structure includes a second semiconductor structure and a second bonding layer, and the second bonding layer includes a second bonding pad; The first bonding pad is bonded to the second bonding pad.
8. The bonding structure according to claim 7, characterized in that: The first bonding layer also includes: a first dummy pad extending from a surface of the first bonding layer into the first bonding layer; The second bonding layer further includes: a second dummy pad extending from a surface of the second bonding layer into the second bonding layer, the first dummy pad being bonded to the second dummy pad; An orthographic projection of the first dummy pad in the thickness direction of the first semiconductor structure and an orthographic projection of the conductive column in the thickness direction of the first semiconductor structure do not overlap.
9. The bonding structure according to claim 7, characterized in that: The surface of the conductive pillar close to the first bonding layer includes a first region and a second region, and the thermal expansion rate of the first region is greater than the thermal expansion rate of the second region; The first bonding pad is in direct contact with the second region.
10. The bonding structure according to claim 9, characterized in that: A plurality of the first bonding pads are disposed on the second region, and the plurality of the first bonding pads are distributed at equal intervals along the circumference of the conductive column.
11. The bonding structure according to claim 9, characterized in that: A plurality of the first bonding pads are disposed on the second region, and the plurality of the first bonding pads have different sizes.
12. The bonding structure according to claim 7, characterized in that: A size of the first bonding pad is smaller than a size of the second bonding pad.
Citation Information
Patent Citations
Package Having Substrate With Embedded Metal Trace Overlapped By Landing Pad
CN104037143A
Semiconductor device, manufacturing method thereof and storage system
CN116230628A
Semiconductor structure and manufacturing method thereof
CN117712065A
Bonding surfaces for direct bonding of semiconductor structures
US20130020704A1
Flip chip device having soldered metal posts by surface mounting
US7902666B1