WAT test method and system

Abstract

The invention provides a WAT test method and system, and the method comprises the steps: carrying out the initial wafer test based on a WAT test file to obtain an initial test result of a tested parameter, judging whether the initial test result of the tested parameter is in a control line range or not based on a control line file, if yes, judging the tested parameter as a pass parameter, and if not, judging the tested parameter as a pass parameter; if not, the tested parameter is judged to be a failure parameter, the failure parameter is recorded in a failure parameter recording module, then a failure action is triggered for the failure parameter recorded in the failure parameter recording module, and the failure action comprises in-situ retest or ectopic retest. According to the WAT test method and system, when the data is judged to be abnormal, failure parameters can be automatically recorded, measures are taken for the failure parameters, and the links of waiting for an engineer to check data, selecting the failure parameters by the engineer, establishing a test program by the WAT engineer and waiting for a test wafer are omitted; therefore, the test and data analysis efficiency can be effectively improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology and relates to a WAT ​​testing method and system. Background Art

[0002] The purpose of Wafer Acceptance Test (WAT) is to monitor whether there are any abnormalities in the process by evaluating the electrical properties of the test devices (DUT) distributed in the test structure (Testkey). There are many products on the production line, and tens of thousands of wafers can be taped out every month. Each wafer needs to be tested by WAT before leaving the factory. Therefore, in order to achieve effective monitoring and catch unqualified products in time, there is usually professional data analysis software. By comparing the values ​​of test parameters with the established control lines, the parameters that exceed the control lines are marked as failures (Fail) for engineers to analyze. After the engineer analyzes, it is usually necessary to test the Fail parameters to determine whether it is a test problem or a process problem. After the additional test is completed, the engineer will analyze the data again. This process needs to be repeated: wafer test-wait for engineers to check the data-engineer selects the Fail parameters-WAT engineers establish additional test procedures-wait for additional wafers-additional wafers-wait for engineers to check the data again, which takes a long time. And if the test data is generated at night, it is necessary to wait until the next working day for engineers to check the data. If additional tests are required, it may be necessary to wait until there is an idle machine before testing again.

[0003] Therefore, how to provide a WAT ​​testing method and system to improve the efficiency of testing and data analysis has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a WAT ​​testing method and system for solving the problem that the existing WAT testing method has many steps and low testing and data analysis efficiency.

[0006] To achieve the above object and other related objects, the present invention provides a WAT ​​testing method, comprising the following steps:

[0007] Perform initial wafer testing based on the WAT test file to obtain initial test results of the tested parameters;

[0008] Based on the control line file, determine whether the initial test result of the measured parameter is within the control line range. If so, the measured parameter is determined as a passed parameter; if not, the measured parameter is determined as a failed parameter;

[0009] Recording the failure parameters in a failure parameter recording module;

[0010] A failure action is triggered for the failure parameter recorded in the failure parameter recording module, wherein the failure action includes an in-situ retest or an ex-situ retest.

[0011] Optionally, according to the wafer product name or the test program name, a test position coordinate file used when triggering the failure action is set in advance, and in-situ retesting or ex-situ retesting is performed based on the test position coordinate file, wherein, during in-situ retesting, the test position coordinates when the failure parameters are generated are used, and during ex-situ retesting, the test position coordinates + / -N when the failure parameters are generated are used, where N is the number of exposure units moved relative to the initial test position coordinates.

[0012] Optionally, the retest includes retesting all failed parameters, or only testing the current-voltage curve.

[0013] Optionally, a failure parameter type file is set in advance, the failure parameter type file includes a test parameter number related to the transistor, and after determining the position of the retest, the failure parameter type file is read, and the number of the failure parameter is compared with the test parameter number in the failure parameter type file, wherein:

[0014] If the match fails, the invalid parameters will be automatically retested;

[0015] If the match is successful, the current-voltage curve test program file is read, and the failure parameter number is compared with the output parameter number in the current-voltage test program file. If the match is successful, the current-voltage curve program is tested on the transistor corresponding to the successfully matched failure parameter.

[0016] Optionally, the WAT test file includes a test program file, a control line file, a test structure coordinate file and a test position coordinate file, the test program file includes the name of the test structure, the name of the test device, the name of the test algorithm, the test conditions, the device pin information and the parameter number; the control line file includes the parameter number, the parameter name, the upper limit of the parameter control line and the lower limit of the parameter control line; the test structure coordinate file includes the names and coordinate information of all test structures; the test position coordinate file includes the test structure coordinate file name, wherein the test program file is associated with the test structure coordinate file through the name of the test structure, the test structure coordinate file is associated with the test position coordinate file through the test structure coordinate file name, and the test program file is associated with the control line file through the parameter number.

[0017] Optionally, when performing an initial wafer test, the testing device obtains the name and coordinate position of the test structure by reading the test structure coordinate file, and then performs the test according to the test method corresponding to the test structure name in the test program file.

[0018] Optionally, after the initial wafer test, the test results of all parameters are stored under the corresponding parameter numbers, recorded together with the tested wafer number and test position coordinates in a test data file and stored in a specified path. The test data file includes the test wafer number, test position number, parameter number, test results, the X-direction coordinate of the test position, and the Y-direction coordinate of the test position. The test data file is associated with the control line file through the parameter number to obtain the control line of each parameter.

[0019] Optionally, when the test system detects that there is a test data file under the specified path, the test data file is captured to the judgment module, and the parameter number in the test data file is compared with the parameter number in the control line file. If the match is successful, the upper control limit and the lower control limit of the corresponding parameter are obtained, and the parameters that are not within the control line range are judged as failed parameters, and the parameter number of the failed parameter and the corresponding test position coordinates are recorded in the failure parameter recording module.

[0020] The present invention also provides a WAT ​​testing system, comprising:

[0021] A judgment module is used to judge whether the initial test result of the measured parameter is within the control line range based on the control line file. If so, the measured parameter is judged as a passed parameter; if not, the measured parameter is judged as a failed parameter;

[0022] A failure parameter recording module, used to record failure parameters;

[0023] A failure action triggering module is used to trigger a failure action on the failure parameters recorded in the failure parameter recording module, wherein the failure action includes an in-situ retest or an out-of-situ retest.

[0024] Optionally, the failure action trigger module includes a test position coordinate file and a failure parameter type file; the test position coordinate file includes the test position coordinates when the failure parameter is generated for in-situ retesting, or the test position coordinate file includes the test position coordinates + / -N when the failure parameter is generated for ex-situ retesting, N is the number of exposure units moved relative to the initial test position coordinates; the failure parameter type file includes transistor-related test parameter numbers, when the failure parameter number matches the test parameter number in the failure parameter type file, the failure action is to test only the current-voltage curve, when the failure parameter number does not match the test parameter number in the failure parameter type file, the failure action is to retest the failure parameter.

[0025] As described above, the WAT test method and system of the present invention perform initial wafer testing based on the WAT test file to obtain the initial test results of the measured parameters, and determine whether the initial test results of the measured parameters are within the control line range based on the control line file. If so, the measured parameters are determined to be passed parameters, if not, the measured parameters are determined to be failure parameters, and the failure parameters are recorded in the failure parameter recording module, and then the failure action is triggered for the failure parameters recorded in the failure parameter recording module, and the failure action includes in-situ retesting or ex-situ retesting. When the WAT test method and system of the present invention determine that the data is abnormal, it can automatically record the failure parameters and take measures for the failure parameters, saving the link of "waiting for engineers to check data-engineers to select failure parameters-WAT engineers to establish additional test procedures-waiting for additional wafers", thereby effectively improving the efficiency of testing and data analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a flow chart of the WAT testing method of the present invention.

[0027] Figure 2 A schematic diagram showing a scribe line and a test structure disposed thereon is shown.

[0028] Figure 3 Shown is an example diagram of a test program file.

[0029] Figure 4 Shown is an example diagram of a control line file.

[0030] Figure 5 Shown is an example of a test structure coordinate file.

[0031] Figure 6 Shown is an example of a test location coordinate file.

[0032] Figure 7 Shown is a sample graph of a test data file.

[0033] Figure 8 The figure shows an example of a test procedure for transistor-related parameters during initial testing.

[0034] Fig. 9 The diagram shows a comparison between the failure parameter number and the number in the current and voltage test program file after determining that the failure parameter is a transistor-related parameter.

[0035] Fig.10 Shown is a flow chart of performing a WAT ​​test using the WAT system of the present invention.

[0036] Description of Reference Numerals

[0037] Steps S1 to S4

[0038] 1 Cutting path

[0039] 2 First test structure

[0040] 201 First Test Device

[0041] 202 First test pad

[0042] 3 Second test structure

[0043] 301 Second test device

[0044] 302 Second test pad DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0047] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0048] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0049] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0050] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0051] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0052] The present invention provides a WAT ​​testing method, please refer to Figure 1 , shown as a flow chart of the method, comprising the following steps:

[0053] S1: Perform initial wafer testing based on the WAT test file to obtain initial test results of the measured parameters;

[0054] S2: judging whether the initial test result of the measured parameter is within the control line range based on the control line file, if so, judging the measured parameter as a passing parameter, if not, judging the measured parameter as a failure parameter;

[0055] S3: Record the failure parameters in a failure parameter recording module;

[0056] S4: triggering a failure action for the failure parameter recorded in the failure parameter recording module, wherein the failure action includes an in-situ retest or an ex-situ retest.

[0057] Specifically, the purpose of WAT testing is to perform electrical evaluation on the device under test (DUT) of the test structure (Testkey) on the wafer to monitor whether there are any abnormalities during the manufacturing process. The test structure is usually set in the cutting path area of ​​the wafer, and the test devices distributed in different test structures are different.

[0058] As an example, see Figure 2 , showing a schematic diagram of a cutting path 1 and a test structure arranged thereon, wherein a first test structure 2 includes an electrically connected first test device 201 and a first test pad 202, and a second test structure 3 includes an electrically connected second test device 301 and a second test pad 302. During testing, an electrical signal is applied to the corresponding test device through the corresponding test pad.

[0059] Specifically, in the step S1, the initial wafer test is performed based on the WAT test file. In some embodiments, the WAT test file includes a test program file, a control line file, a test structure coordinate file, and a test position coordinate file.

[0060] As an example, see Figure 3 , showing an example diagram of the test program file, including the name of the test structure (Testkey name), the name of the test device (Device name), the name of the test algorithm (algorithmname), the test condition (test condition), the device pin information (PAD) and the parameter number (output).

[0061] As an example, see Figure 4 , which is displayed as an example diagram of the control line file, including a parameter number (parameter ID), a parameter name, an upper limit of the parameter control line, and a lower limit of the parameter control line.

[0062] As an example, see Figure 5 , which shows an example diagram of the test structure coordinate file, including the names (Testkey name) and coordinate information (X, Y) of all test structures.

[0063] As an example, see Figure 6 , which is shown as an example diagram of the test position coordinate file, wherein the test position coordinate file includes X-direction coordinate and Y-direction coordinate information of the test position.

[0064] Specifically, due to the large area of ​​a whole wafer, some processes in the manufacturing process cannot be completed on the entire wafer at one time, so it is artificially divided into dozens of completely identical areas (repeated areas). Each area corresponds to a minimum exposure unit (shot), and is processed shot by shot during production.

[0065] Specifically, during the WAT test, only some units are tested. The test position coordinate file is a file that defines the test position coordinates. The test position can be accurately located through the coordinates in the X and Y directions. At the same time, the test position coordinate file includes the test structure coordinate file name to achieve the association between the test position coordinate file and the test structure coordinate file.

[0066] Furthermore, in the present invention, the test program file and the test structure coordinate file are associated with each other through the name of the test structure, the test structure coordinate file and the test position coordinate file are associated with each other through the name of the test structure coordinate file, and the test program file and the control line file are associated with each other through the parameter number, so that when performing the initial wafer test, the test equipment can obtain the name and coordinate position of the test structure by reading the test structure coordinate file, and then perform the test according to the test method corresponding to the test structure name in the test program file.

[0067] As an example, after the initial wafer test, the test results of all parameters are stored under the corresponding parameter number, recorded together with the tested wafer number and the test position coordinates in the test data file and stored in the specified path.

[0068] As an example, see Figure 7 , showing an example diagram of the test data file, which includes the test wafer number (wafer number), the test position number, the parameter number (R1, R2, R3), the test result, the X-direction coordinate (X) of the test position and the Y-direction coordinate (Y) of the test position. The test data file is associated with the control line file through the parameter number to obtain the control line of each parameter.

[0069] As an example, in step S2, when the test system detects that there is a test data file under the specified path, the test data file is captured to the judgment module, and the parameter number in the test data file is compared with the parameter number in the control line file. If the match is successful, the upper control limit and the lower control limit of the corresponding parameter are obtained, and the parameters that are not within the control line range are judged as failed parameters.

[0070] As an example, in the step S3: the parameter number of the failure parameter and the corresponding test position coordinates are recorded in the failure parameter recording module.

[0071] As an example, in step S4, the test position coordinate file used when triggering the failure action is set in advance according to the wafer product name or the test program name, and in-situ retesting or ex-situ retesting is performed based on the test position coordinate file, wherein, during the in-situ retesting, the test position coordinates when the failure parameters are generated are used, and during the ex-situ retesting, the test position coordinates + / -N when the failure parameters are generated are used, where N is the number of exposure units (shots) moved relative to the initial test position coordinates.

[0072] Specifically, the purpose of setting the test position coordinate file used when triggering the failure action in advance is to deal with two situations: because the test devices at different test positions may be in different conditions, when it is necessary to verify whether the test position that failed in the first test is indeed a device failure, it is necessary to retest the original position; and when some test devices (DUT) have the characteristic of being able to withstand only one test process, the test position needs to be changed for the second test.

[0073] As an example, the retest includes retesting all failed parameters, or only testing the current-voltage curve. This is also because when the test device is a transistor, the same test device (DUT) usually has multiple test items, such as the linear region turn-on voltage VTL, the saturation region turn-on voltage VTS, the linear region turn-on current IDL, the saturation region turn-on current IDS, the transistor turn-off leakage current IOFF, the transistor breakdown voltage BVDS, etc. If the test device is a failed device caused by process abnormalities, the relevant data of all test items have been obtained during the initial wafer test, and it is unnecessary to test all test items again after judging it as a failure parameter. However, in order to provide data to help engineers confirm whether the process of the device itself is abnormal, the curve of current versus voltage is tested for this failed test device. If the result of the curve analysis is also judged as a failed device, it means that the initial wafer test result is accurate.

[0074] As an example, in step S4, a failure parameter type file is set in advance, the failure parameter type file includes a test parameter number related to the transistor, and after determining the position of the retest, that is, after selecting the test position target file, the failure parameter type file is read, and the number of the failure parameter is compared with the test parameter number in the failure parameter type file, wherein:

[0075] If the match fails, the invalid parameters will be automatically retested;

[0076] If the match is successful, the current-voltage curve test program file is read, and the failure parameter number is compared with the output parameter number in the current-voltage test program file. If the match is successful, the current-voltage curve program is tested on the transistor corresponding to the successfully matched failure parameter.

[0077] Specifically, the current and voltage test program includes the voltage and current curve test conditions and test parameter numbers of all transistors, and the failure parameter type file includes all test parameter numbers related to all transistors. During comparison, all failure parameter numbers are first compared one by one with the numbers in the failure parameter type file. If the match is successful, the current and voltage curve test program file is read. In this file, the test parameter numbers of multiple test items of a transistor correspond to a test curve program, which can avoid repeated testing of current and voltage curves for multiple failure parameters of a transistor.

[0078] As an example, see Figure 8 and Fig. 9 ,in, Figure 8 The following is an example of a test procedure for transistor-related parameters during initial testing. Fig. 9 The diagram shows a comparison of the failure parameter number with the number in the current and voltage test program file after determining that the failure parameter is a transistor-related parameter, wherein multiple parameter numbers correspond to one test curve program.

[0079] The WAT test method of the present invention performs electrical evaluation on the test devices (DUT) distributed in the test structure (Testkey) to monitor whether there are any abnormalities during the process. During the uninterrupted production of the production line, the WAT test results can be automatically monitored and actions can be automatically executed according to the test results to achieve efficient capture of abnormal wafers.

[0080] The present invention also provides a WAT ​​test system, including a judgment module, a failure parameter recording module and a failure action triggering module, wherein the judgment module is used to judge whether the initial test result of the measured parameter is within the control line range based on the control line file, if so, the measured parameter is judged as a passing parameter, if not, the measured parameter is judged as a failure parameter; the failure parameter recording module is used to record the failure parameter, and the failure action triggering module is used to trigger the corresponding failure action based on the type of the failure parameter, and the failure action includes retesting the failure parameter or only testing the current-voltage curve.

[0081] As an example, the failure action trigger module includes a failure parameter type file and a test position coordinate file, the failure parameter type file includes a test parameter number related to the transistor, when the failure parameter number matches the test parameter number in the failure parameter type file, the failure action is to only test the current-voltage curve, when the failure parameter number does not match the test parameter number in the failure parameter type file, the failure action is to retest the failure parameter; the test position coordinate file includes the test position coordinates when the failure parameter is generated for in-situ retesting, or the test position coordinate file includes the test position coordinates + / -N when the failure parameter is generated for out-of-situ retesting, wherein N is the number of exposure units moved relative to the initial test position coordinates.

[0082] As an example, see Fig.10 , showing a flow chart of WAT testing using the WAT system of the present invention. The WAT test system of the present invention compares the test results with the control line file through the judgment module, makes a Pass or Fail judgment on the wafer test data, and records the parameters judged as Fail in the failure parameter recording module, and then triggers the failure action trigger module to retest the parameters in the failure parameter recording module, wherein the test position file is pre-set before the test, and the original position retest or other position retest can be performed, which can meet the verification of the quality of the test device at the original test position, and is also suitable for situations where the test cannot be repeated at the original position. In addition, for transistor test devices, when there are many test items for the same test device, in order to save the time of retesting all parameters and provide data to prove whether it is an abnormal problem in the device process, only the current and voltage change curve is tested.

[0083] In summary, the WAT test method and system of the present invention conducts initial wafer testing based on the WAT test file to obtain the initial test results of the measured parameters, and determines whether the initial test results of the measured parameters are within the control line range based on the control line file. If so, the measured parameters are determined to be passed parameters, if not, the measured parameters are determined to be failure parameters, and the failure parameters are recorded in the failure parameter recording module, and then the failure action is triggered for the failure parameters recorded in the failure parameter recording module, and the failure action includes in-situ retesting or out-of-situ retesting. When the WAT test method and system of the present invention judge that the data is abnormal, it can realize automatic recording of failure parameters and take measures for failure parameters, saving the link of "waiting for engineers to check data-engineers to select failure parameters-WAT engineers to establish additional test procedures-waiting for additional wafers", thereby effectively improving the efficiency of testing and data analysis. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A WAT testing method, characterized in that: The following steps are involved: Perform initial wafer testing based on the WAT test file to obtain initial test results of the tested parameters; Based on the control line file, determine whether the initial test result of the measured parameter is within the control line range. If so, the measured parameter is determined as a passed parameter; if not, the measured parameter is determined as a failed parameter; Recording the failure parameters in a failure parameter recording module; A failure action is triggered for the failure parameter recorded in the failure parameter recording module, wherein the failure action includes an in-situ retest or an ex-situ retest.

2. The WAT testing method according to claim 1, characterized in that: According to the wafer product name or the test program name, the test position coordinate file used when triggering the failure action is set in advance, and in-situ retesting or ex-situ retesting is performed based on the test position coordinate file. In the case of in-situ retesting, the test position coordinates when the failure parameters are generated are used, and in the case of ex-situ retesting, the test position coordinates + / -N when the failure parameters are generated are used, where N is the number of exposure units moved relative to the initial test position coordinates.

3. The WAT testing method according to claim 1, characterized in that: The retest includes retesting all failed parameters, or only testing the current-voltage curve.

4. The WAT testing method according to claim 3, characterized in that: A failure parameter type file is set in advance, the failure parameter type file includes a test parameter number related to the transistor, and after determining the position of the retest, the failure parameter type file is read, and the number of the failure parameter is compared with the test parameter number in the failure parameter type file, wherein: If the match fails, the invalid parameters will be automatically retested; If the match is successful, the current-voltage curve test program file is read, and the failure parameter number is compared with the output parameter number in the current-voltage test program file. If the match is successful, the current-voltage curve program is tested on the transistor corresponding to the successfully matched failure parameter.

5. The WAT testing method according to claim 1, characterized in that: The WAT test file includes a test program file, a control line file, a test structure coordinate file and a test position coordinate file, wherein the test program file includes the name of the test structure, the name of the test device, the name of the test algorithm, the test conditions, the device pin information and the parameter number; the control line file includes the parameter number, the parameter name, the upper limit of the parameter control line and the lower limit of the parameter control line; the test structure coordinate file includes the names and coordinate information of all test structures; the test position coordinate file includes the test structure coordinate file name, wherein the test program file is associated with the test structure coordinate file through the name of the test structure, the test structure coordinate file is associated with the test position coordinate file through the test structure coordinate file name, and the test program file is associated with the control line file through the parameter number.

6. The WAT testing method according to claim 5, characterized in that: When performing the initial wafer test, the test equipment obtains the name and coordinate position of the test structure by reading the test structure coordinate file, and then performs the test according to the test method corresponding to the test structure name in the test program file.

7. The WAT testing method according to claim 6, characterized in that: After the initial wafer test, the test results of all parameters are stored under the corresponding parameter numbers, recorded together with the tested wafer number and test position coordinates in a test data file and stored in a specified path. The test data file includes the test wafer number, test position number, parameter number, test results, the X-direction coordinate of the test position, and the Y-direction coordinate of the test position. The test data file is associated with the control line file through the parameter number to obtain the control line of each parameter.

8. The WAT testing method according to claim 7, characterized in that: When the test system detects that there is a test data file under the specified path, the test data file is captured to the judgment module, and the parameter number in the test data file is compared with the parameter number in the control line file. If the match is successful, the control upper limit and control lower limit of the corresponding parameter are obtained, and the parameters that are not within the control line range are judged as failure parameters, and the parameter number of the failure parameter and the corresponding test position coordinates are recorded in the failure parameter recording module.

9. A WAT testing system, characterized in that: include: A judgment module is used to judge whether the initial test result of the measured parameter is within the control line range based on the control line file. If so, the measured parameter is judged as a passed parameter; if not, the measured parameter is judged as a failed parameter; A failure parameter recording module, used to record failure parameters; A failure action triggering module is used to trigger a failure action on the failure parameters recorded in the failure parameter recording module, wherein the failure action includes an in-situ retest or an out-of-situ retest.

10. The WAT testing system according to claim 9, characterized in that: The failure action trigger module includes a test position coordinate file and a failure parameter type file; the test position coordinate file includes the test position coordinate when the failure parameter is generated for in-situ retesting, or the test position coordinate file includes the test position coordinate + / -N when the failure parameter is generated for out-of-situ retesting, where N is the number of exposure units moved relative to the initial test position coordinate; The failure parameter type file includes transistor-related test parameter numbers. When the failure parameter number matches the test parameter number in the failure parameter type file, the failure action is to test only the current-voltage curve. When the failure parameter number does not match the test parameter number in the failure parameter type file, the failure action is to retest the failure parameter.

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