Dynamic comparator with low power consumption and low transmission delay

Abstract

The invention discloses a low-power-consumption low-transmission-delay dynamic comparator, and belongs to the technical field of analog integrated circuits. Comprising an external bias small current input circuit used for continuously providing static bias current for the pre-amplifier; a two-stage differential input single-ended output pre-amplifier, wherein the positive / negative input end of differential input is respectively connected with a power supply voltage and an output point voltage of an external rectification circuit; the preamplifier provides driving voltage for a dynamic bias inverter in the dynamic bias circuit; the dynamic bias circuit is formed by connecting a dynamic bias inverter and an NMOS (N-channel Metal Oxide Semiconductor) tube connected with a diode in series, and is used for selectively providing dynamic bias current for the pre-amplifier according to a difference value of differential input of the pre-amplifier; and a driving circuit. According to the continuous time comparator, a static bias and dynamic bias combined mode is adopted, bias current can be increased through dynamic bias when the input signal difference of the comparator is small, and the low-power-consumption and low-transmission-delay continuous time comparator is achieved.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits and relates to a low-power consumption and low-transmission delay dynamic comparator. Background Art

[0002] There is a phase difference between the output current and voltage of the piezoelectric energy capture sensor, so its rectifier circuit will face the situation where the current and voltage are in opposite directions. Suppose at a certain moment the voltage is positive and the current is reversed. At this time, since the voltage is positive, the rectifier circuit is turned on, but since the current is negative, the piezoelectric energy capture sensor not only cannot provide energy to the subsequent circuit, but will extract energy from the subsequent interface circuit, which will lead to a decrease in energy capture efficiency. In order to prevent this from happening, when the current and voltage are in opposite directions, a zero-crossing comparison circuit is generally required to disconnect the interface circuit and the piezoelectric energy capture sensor.

[0003] The comparison speed of the zero-crossing detection two-stage comparator is directly related to the bias current and the input voltage difference of the differential pair. Under the same bias current, the larger the input voltage difference of the differential pair, the faster the comparison speed; the smaller the input voltage difference of the differential pair, the slower the comparison speed.

[0004] For the piezoelectric vibration energy capture sensor system, zero-crossing detection happens to be an application scenario where the comparator needs to quickly give a comparison result when the differential pair input voltage difference is very small. In order to achieve the comparator to quickly give a comparison result, it is often necessary to give M N21 A larger bias current is used to enhance the transconductance of the two-stage amplifier. However, since the piezoelectric vibration energy capture sensor system is an energy supply module (depending on the sensor, the capture power is generally several hundred μW to several mW), it is necessary to maximize the output of the captured energy to the subsequent sensing, computing and communication modules. Therefore, it is obviously inappropriate to increase the static bias current of the zero-crossing detection comparator to reduce the comparison time. Summary of the invention

[0005] In view of the problem that the comparison time of the traditional zero-crossing detection comparator is long when the input voltage difference is small, the present invention proposes a low-power and low-transmission delay dynamic comparator, which adopts a combination of static bias and dynamic bias. When the comparator input signal difference is small, the bias current can be increased through dynamic bias, thereby realizing a low-power, low-transmission delay continuous time comparator.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] In a first aspect, the present invention provides a low-power consumption and low-transmission delay dynamic comparator, comprising:

[0008] An external bias low current input circuit is used to continuously provide a static bias current for the pre-amplifier;

[0009] A two-stage differential input single-ended output preamplifier comprises a first-stage amplifier and a second-stage amplifier connected in series, wherein the positive input terminal and the negative input terminal of the differential input are respectively connected to the power supply voltage and the output point voltage of the external rectifier circuit; the preamplifier provides a driving voltage for a dynamic bias inverter in a dynamic bias circuit;

[0010] A dynamic bias circuit, composed of a dynamic bias inverter and a diode-connected NMOS tube connected in series, for selectively providing a dynamic bias current to the preamplifier according to the difference of the differential input of the preamplifier;

[0011] When the differential input phase difference of the preamplifier is greater than a threshold value, the driving voltage provided by the preamplifier is far away from the inversion threshold value of the dynamic bias inverter, the dynamic bias inverter is in a stable output state, no dynamic bias current is provided, and the preamplifier is biased only by a static bias current; when the differential input phase difference of the preamplifier is less than or equal to the threshold value, the driving voltage provided by the preamplifier is close to the inversion threshold value of the dynamic bias inverter, the dynamic bias inverter is in an inversion state, and the current flowing through the dynamic bias inverter provides a dynamic bias current for the preamplifier through a diode-connected NMOS tube, and the preamplifier is biased by both the static bias current and the dynamic bias current;

[0012] The driving circuit is composed of two inverters connected in series, and the dynamic bias circuit provides input signals and transmits them to the downstream load circuit.

[0013] Preferably, the external bias low current input circuit is a diode-connected NMOS tube M N31 , the diode connection refers to M N31 The gate and drain terminals are short-circuited, M N31 The drain end of M is connected to an external bias current, and the external bias current is a static bias current. N31 The source end of the ground, M N31 The gate end of the circuit serves as the output end of the external bias small current input circuit and is respectively connected to the first-stage amplifier and the second-stage amplifier in the pre-amplifier to provide a static bias current.

[0014] Preferably, the first stage amplifier in the pre-amplifier comprises an NMOS tube M N32 、NMOS tube M N33 、NMOS tube M N34 、NMOS tube M N35 、PMOS tube M P31 And PMOS tube M P32 ;

[0015] The MP31 The source end of M is used as the negative input end of the first stage amplifier, and is connected to the output point voltage of the external rectifier circuit; P32 The source end of M is used as the positive input end of the first stage amplifier and connected to the power supply voltage; P31 The gate and drain terminals are short-circuited and connected to M P32 The gate terminal is connected to N32 、M N33 With M P31 The drain end is connected to N34 、M N35 With M P32 The drain end is connected to the output end of the first stage amplifier; M N32 With M N34 The gate terminal is connected to the external bias small current input circuit, M N33 With M N35 The gate terminal is connected to the dynamic bias circuit, M N32 、M N33 、M N34 With M N35 The source terminal is grounded.

[0016] Preferably, the second stage amplifier in the pre-amplifier is a common source amplifier.

[0017] Preferably, the common source amplifier is composed of NMOS tube M N36 、NMOS tube M N37 And PMOS tube M P33 constitute;

[0018] The M P33 The gate end is connected to the output end of the first stage amplifier, M P33 The source end of the power supply voltage is connected, M P33 、M N36 With M N37 The drain end is connected to the output end of the second stage amplifier, M N36 The gate terminal is connected to an external bias low current input circuit, M N37 The gate terminal is connected to the dynamic bias circuit, M N36 With M N37 The source terminal is grounded.

[0019] Preferably, the dynamic bias circuit includes an NMOS tube M N39 With PMOS tube M P34 The dynamic bias inverter and a diode-connected NMOS tube M N38 ;

[0020] The M N39 With M P34The drain end of M is connected to the voltage output end of the dynamic bias circuit to provide an input signal for the driving circuit; N39 With M P34 The gate terminal is connected to the output terminal of the second stage amplifier, M P34 The source end of the power supply voltage is connected, M N39 The source and M N38 The drain end is connected to N38 The gate terminal and the drain terminal of M are short-circuited to form a diode connection and serve as a dynamic bias current output terminal, which is used to provide a dynamic bias current for the first stage amplifier and the second stage amplifier; N38 The source terminal is grounded.

[0021] Preferably, the width-to-length ratio of the second-stage inverters connected in series in the driving circuit is 4-5 times that of the first-stage inverters.

[0022] Preferably, the second-stage inverter has the same length as the first-stage inverter.

[0023] In a second aspect, the present invention provides an active diode, including a PMOS tube M0 and the above-mentioned low-power consumption, low transmission delay dynamic comparator, wherein the output end of the low-power consumption, low transmission delay dynamic comparator is connected to the gate end of M0, and the source end and the drain end of M0 are respectively connected to the positive input end and the negative input end of the differential input of the low-power consumption, low transmission delay dynamic comparator.

[0024] In the third aspect, the present invention provides a piezoelectric vibration energy capture sensor system, including a piezoelectric vibration energy capture sensor, a rectifier circuit, a super capacitor and the above-mentioned active diode module, the output end of the piezoelectric vibration energy capture sensor is connected to the negative input end of the comparator of the active diode module through the rectifier circuit, and the super capacitor is connected to the positive input end of the comparator of the active diode module for providing a supply voltage.

[0025] The beneficial effects of the present invention are:

[0026] The comparator provided by the present invention adopts a combination of static bias and dynamic bias. The dynamic bias inverter of the dynamic bias circuit is provided with a driving voltage by a preamplifier. When the differential input phase difference of the preamplifier is greater than a threshold value, the driving voltage provided by the preamplifier is far away from the inversion threshold of the dynamic bias inverter. The dynamic bias inverter is in a stable output state. The current flowing through the dynamic bias inverter is the leakage current of the tube. The dynamic bias current is almost zero. The preamplifier is biased only by the static bias current. When the differential input phase difference of the preamplifier is less than or equal to the threshold value, the driving voltage provided by the preamplifier is close to the inversion threshold of the dynamic bias inverter. The dynamic bias inverter is in an inversion state. The large current flowing through the dynamic bias inverter provides a dynamic bias current for the preamplifier through a diode-connected NMOS tube. The preamplifier is biased by the static bias current and the dynamic bias current. The dynamic bias circuit can selectively provide a dynamic bias current for the preamplifier according to the difference of the differential input of the preamplifier. When the difference of the comparator input signal is small, the overall bias current is increased by dynamic biasing, and it has the characteristics of low power consumption and low transmission delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of a piezoelectric vibration energy capture sensor system.

[0028] Figure 2 It is a traditional comparator for zero-crossing detection.

[0029] Figure 3 The invention provides a low-power and low-delay comparator circuit with dynamically adjusted power consumption.

[0030] Figure 4 The present invention provides a system block diagram of a low-power and low-latency comparator circuit with dynamically adjusted power consumption.

[0031] Figure 5 It is a simulation diagram of a traditional comparator and a comparator of the present invention under the same circumstances. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments in the invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0033] like Figure 2 In a conventional zero-crossing detection two-stage comparator shown in FIG. N21 The bias current I is applied to the drain terminal b2 , M N21 The gate and drain terminals are short-circuited, and the source terminal is grounded;N22 、M N23 and M N24 The gate terminal and M N21 The gate terminal is connected to the source terminal and the source terminal is grounded. P21 The source end is the negative end of the comparator, M P21 The gate and drain are short-circuited, M P21 The drain terminal and M N22 The drain end is connected to P22 The source end is the positive end of the comparator, M P22 Gate terminal and M P21 The gate terminal is connected to P22 The drain terminal and M N23 The drain terminal and M P23 The gate terminal of M P23 The source terminal is connected to a super capacitor, M P23 The drain terminal is M N24 The drain terminal and M P24 and M N25 The gate terminal. P24 The source terminal is connected to a super capacitor, M P24 The drain terminal and M N25 The drain end of M is connected as the output of the comparator. N25 The source terminal of the comparator is grounded. It can be seen that the comparison speed of the comparator is related to the bias current I b2 In addition, the comparison speed of the comparator is also directly related to the input voltage difference of the differential pair. Under the same bias current, the larger the input voltage difference of the differential pair, the faster the comparison speed; the smaller the input voltage difference of the differential pair, the slower the comparison speed. The bias current cannot be adjusted dynamically.

[0034] like Figure 3 As shown, the low-power consumption and low-transmission delay dynamic comparator proposed by the present invention includes an external bias low-current input circuit, a two-stage differential input single-ended output preamplifier, a dynamic bias circuit and a driving circuit.

[0035] Wherein, the external bias low current input circuit is used to continuously provide static bias current for the pre-amplifier;

[0036] A two-stage differential input single-ended output preamplifier comprises a first-stage amplifier and a second-stage amplifier connected in series, wherein the positive input terminal and the negative input terminal of the differential input are respectively connected to the power supply voltage and the output point voltage of the external rectifier circuit; the preamplifier provides a driving voltage for a dynamic bias inverter in a dynamic bias circuit;

[0037] A dynamic bias circuit, composed of a dynamic bias inverter and a diode-connected NMOS tube connected in series, for selectively providing a dynamic bias current to the preamplifier according to the difference of the differential input of the preamplifier;

[0038] When the differential input phase difference of the preamplifier is greater than a threshold value, the driving voltage provided by the preamplifier is far away from the inversion threshold value of the dynamic bias inverter, the dynamic bias inverter is in a stable output state, no dynamic bias current is provided, and the preamplifier is biased only by a static bias current; when the differential input phase difference of the preamplifier is less than or equal to the threshold value, the driving voltage provided by the preamplifier is close to the inversion threshold value of the dynamic bias inverter, the dynamic bias inverter is in an inversion state, and the current flowing through the dynamic bias inverter provides a dynamic bias current for the preamplifier through a diode-connected NMOS tube, and the preamplifier is biased by both the static bias current and the dynamic bias current;

[0039] The driving circuit is composed of two inverters connected in series, and the dynamic bias circuit provides an input signal and transmits it to the downstream load circuit, which can provide sufficient current to the load circuit, thereby improving the dynamic performance of the system.

[0040] by Figure 1 The piezoelectric vibration energy capture sensor system shown is taken as an example to introduce the low-power consumption and low-transmission delay dynamic comparator of the present invention. Figure 1 In the system, a piezoelectric vibration energy capture sensor 100, a rectifier circuit 110, an active diode module 120 and a super capacitor 130 are included, wherein the active diode module 120 is composed of a PMOS tube M0 and a low-power low-transmission delay dynamic comparator 122, wherein the output end of the low-power low-transmission delay dynamic comparator is connected to the gate end of M0, and the source end and the drain end of M0 are respectively connected to the positive input end and the negative input end of the differential input of the low-power low-transmission delay dynamic comparator. The output end of the piezoelectric vibration energy capture sensor is connected to the negative input end of the comparator of the active diode module through the rectifier circuit, and the super capacitor is connected to the positive input end of the comparator of the active diode module, and the super capacitor is used to provide a power supply voltage for the comparator.

[0041] The voltage of the supercapacitor 130 is recorded as V S , as the power supply of the comparator, and connected to the positive input terminal of the first stage of the two-stage pre-amplifier; the output point voltage of the rectifier circuit is recorded as V REC , connected to the negative input terminal of the first stage amplifier of the two-stage preamplifier. The external bias current is recorded as I b31 , used to provide the static bias current of the comparator.

[0042] like Figure 3 As shown, the external bias small current input circuit is a diode-connected NMOS tube M N31 , the diode connection refers to M N31 The gate and drain terminals are short-circuited, M N31 The drain terminal is biased by a small external current I b31Connection, the external bias current is the static bias current, M N31 The source end of the ground, M N31 The gate terminal is used as the output terminal of the external bias small current input circuit, denoted by M N31 The gate voltage is V b31 The gate voltage will provide a very small static bias current for the subsequent two-stage pre-amplifier, which are connected to the first-stage amplifier and the second-stage amplifier in the pre-amplifier respectively.

[0043] The first stage amplifier of the preamplifier includes the following four NMOS tubes: N32 、M N33 、M N34 、M N35 And the following two PMOS tubes: M P31 and M P32 Among them, M P31 The source end of the first stage amplifier is connected to the output voltage V of the rectifier circuit. REC Upper, M P32 The source end of the first stage amplifier is used as the positive input end, and the voltage V S . M P31 and M P32 The gate terminal is connected to M P31 The drain terminal of M N32 、M N33 With M P31 The drain end is connected to N34 、M N35 With M P32 The drain terminal of M N32 、M N34 The gate terminal and the external bias small current input circuit M N31 The gate terminal is connected; M N32 、M N33 、M N34 With M N35 The source end of M is grounded. N33 With M N35 The gate terminal is connected to the M in the dynamic bias circuit. N38 The gate terminal is connected.

[0044] The second stage amplifier of the two-stage preamplifier is composed of M P33 、M N36 and M N37 A common source amplifier is formed. P33 The gate terminal of the first stage amplifier is connected to the M P32 The drain end is connected to P33 The source end of the super capacitor is connected to the voltage V S , M P33 、M N36With M N37 The drain end is connected to N36 With M N37 The source end of the ground, M N36 The gate terminal and the external bias small current input circuit M N31 The gate terminal is connected to N37 The gate terminal and the M in the dynamic bias circuit N38 The gate terminal is connected.

[0045] The dynamic bias circuit consists of two NMOS tubes: M N38 and M N39 , and a PMOS tube M P34 Among them, M N39 With M P34 Form an inverter, M N39 With M P34 The drain end is connected to the drive circuit, M N39 With M P34 The gate terminal is connected to the second stage amplifier, M P34 The source end of the super capacitor is connected to the voltage V S , M N39 The source and M N38 The drain terminal of M N38 The gate and drain terminals are short-circuited to form a diode connection, M N38 The source end of the ground, M N38 The gate ends are also connected to two-stage pre-amplifiers.

[0046] The driving circuit is composed of NMOS tube M N310 、M N311 And PMOS tube M P35 、M P36 Composition. N310 、M P35 , forming the first stage driving circuit, M N311 、M P36 It constitutes the second stage driving circuit. N310 With M P35 The gate terminal is connected to the M in the dynamic bias circuit. N39 With M P34 The drain terminal; M N310 With M P35 The drain end is connected to the output end of the first stage driving circuit; M P35 The voltage V of the super capacitor connected to the source S , M N310 The source end of M is grounded. N311 With M P36 The gate terminal is connected to the M of the first stage drive circuit. N310 With M P35 The drain terminal; M N311 With MP36 The drain end is connected to the output end of the second stage driving circuit; M P36 The voltage V of the super capacitor connected to the source S , M N311 The source terminal is grounded.

[0047] Will Figure 3 The circuit in is divided into Figure 4 The system block diagram shown in FIG. 1 shows the circuit working principle more intuitively. 401 represents the comparator of the present invention, V S Connected to the positive input of the comparator, V REC The output terminal of the comparator is connected to the negative input terminal of the comparator, and the output terminal of the comparator is connected to the dynamic bias inverter 402 in the dynamic bias circuit. The dynamic bias inverter 402 outputs the final voltage V through the driving circuit 403. OUT The comparator has two sets of bias currents, one of which is a small current I biased by the first current mirror 404. b41 , and the other group is the current I dynamically biased by the second current mirror 405 b42 The first current mirror 404 is composed of the above-mentioned tube M N31 , M N32 , M N34 With M N36 The second current mirror 405 is composed of the above-mentioned transistor M N33 , M N35 , M N37 With M N38 constitute.

[0048] Combination Figure 1 and Figure 3 , the comparator working process proposed in the present invention is explained.

[0049] From the system level: the comparator can be applied to the active diode module 120 in the piezoelectric vibration energy capture sensor system, and a PMOS tube 121 is controlled by the comparator 122 proposed by the present invention. In this scenario, no matter whether the initial direction of the current from the piezoelectric vibration energy capture sensor 100 is positive or negative, the rectifier circuit 110 will rectify the current into a positive direction and flow into the active diode module 120.

[0050] The comparator has two working processes. One is voltage V REC Less than or equal to the voltage V on the supercapacitor S , the other is voltage V REC Greater than the voltage V on the supercapacitor S , the following will describe the work flow from two aspects.

[0051] When the current captured by the piezoelectric vibration energy capture sensor 100 begins to flow into the rectifier circuit 110, the voltage on the parasitic capacitor inside the piezoelectric vibration energy capture sensor 100 is low, resulting in the output voltage V REC Lower than the voltage of super capacitor 130 V S , the comparator 122 outputs a high level voltage to turn off the PMOS tube 121, isolating the piezoelectric vibration energy capture sensor 100 from the super capacitor 130, and preventing the current on the super capacitor 130 from flowing back to the parasitic capacitor in the piezoelectric vibration energy capture sensor 100, thereby reducing the energy that can be captured. Since the PMOS tube 121 is turned off, the current captured by the piezoelectric vibration energy capture sensor 100 begins to charge the internal parasitic capacitor, thereby causing the output voltage V REC Gradually increase.

[0052] As the output voltage V of the rectifier circuit 110 REC The voltage V of the super capacitor 130 is increased and exceeds S When V REC Higher than V S , so the charge can flow from the piezoelectric vibration energy capture sensor 100 into the super capacitor 130. At the same time, V REC The voltage is clamped to approximately V S .

[0053] When the current captured by the piezoelectric vibration energy capture sensor 100 changes from the positive direction to the negative direction, the internal parasitic capacitance of the piezoelectric vibration energy capture sensor 100 begins to discharge, so the output voltage V of the rectifier circuit 110 REC Starts to decrease gradually when V REC Still higher than V S When V REC Lower than V S After that, the comparator 122 quickly flips and outputs a high level voltage to turn off the PMOS tube 121, preventing the current from flowing back from the super capacitor 130 to the parasitic capacitor in the piezoelectric vibration energy capture sensor 100. When the internal parasitic capacitor of the piezoelectric vibration energy capture sensor 100 is discharged, the capacitor begins to be charged by the captured reverse current, so the output voltage V of the rectifier circuit 110 is REC Then it starts to rise gradually. The subsequent workflow is as described above.

[0054] From the circuit level: the comparator has two working modes, namely, the negative input terminal of the comparator gradually rises from a low voltage until it is higher than the positive input terminal of the comparator, and the negative input terminal of the comparator gradually decreases from a high voltage until it is lower than the positive input terminal of the comparator.

[0055] First, the first working mode is introduced: the negative input terminal of the comparator gradually rises from a low voltage until it is higher than the positive input terminal of the comparator. REC Much lower than V S When M in the first stage amplifier P31 The gate and drain voltages are also lower than V S , at this time M P32 The source-gate voltage difference is large, so M P32 On, M P32 The drain output voltage V O31 is a high level voltage, which acts on the M in the second stage amplifier P33 The gate terminal makes M P33 is turned off, so M P33 The drain output voltage V O32 is a low level voltage, which acts on the M in the dynamic bias circuit N39 The gate terminal makes M N39 At this time, due to M N39 is turned off, so M N38 No current flows through it. Then the M N33 and M N35 , M in the second stage amplifier N37 There is no current flowing through the comparator. N32 、M N34 and M N36 Only by M N31 The small current I b31 (tens of nA) for biasing. At the same time, since M N39 Shutdown, M P34 conduction, so the first stage M of the driving circuit N310 conduction, and M P35 Shutdown; Second stage M P36 On, M N311 Shutdown, so that the output voltage of the entire comparator V OUT is high level.

[0056] With V REC Gradually approaching V S , M in the first stage amplifier P31 The gate and drain voltages of M P32 The source-gate voltage difference is reduced, so M P32The drain output voltage V O31 starts to decrease. When V REC Very close to V S When V O31 The voltage will be close to the midpoint of the supply voltage. S With V O31 The difference is greater than the M in the second stage amplifier P33 After the threshold, M P33 Start to conduct, and then M P33 The drain output voltage V O32 starts to rise. At this time, as V O32 rise, which acts on the M in the dynamic bias circuit P34 and M N39 The gate end, at a certain moment M P34 With M N39 At this time, a large transient current (several μA to tens of μA) flows from the supercapacitor voltage V S Generates a large transient current that passes through the M in the dynamic bias circuit in turn. P34 、M N39 With M N38 Then it flows into the simulation ground. N38 The gate voltage of the amplifier is self-regulated according to the transient current. At the same time, the large transient current passes through the M in the first stage amplifier. N33 and M N35 , M in the second stage amplifier N37 The first and second amplifiers of the preamplifier are copied, so that the transconductance of the two-stage amplifier is enhanced, the amplification factor is also improved, and V O31 Rapidly decreasing V O32 Rise quickly.

[0057] When V REC Much higher than V S When M in the first stage amplifier P31 The gate and drain voltages are close to or higher than V S , at this time M P32 The source-gate voltage difference is very small or negative, so M P32 Shutdown, M P32 The drain output voltage V O31 is a low level voltage, which acts on the M in the second stage amplifier P33 The gate terminal makes M P33 conduction, so M P33 The drain output voltage V O32 is a high level voltage, which acts on the M in the dynamic bias circuit P34 The gate terminal makes M P34 At this time, due to M P34is turned off, so M N38 No current flows through it. Then the M N33 and M N35 , tube M in the second stage amplifier N37 There is no current flowing through the comparator. N31 The small current I b31 (tens of nA) for biasing. At the same time, due to M P34 Turn off and M N39 conduction, thereby making the first stage M of the driving circuit P35 M N310 Turn off; make the second stage M of the driving circuit N311 conduction, and M P36 Turn off. In this way, the output voltage of the entire comparator V OUT is low level.

[0058] The second working mode is described below: the negative input terminal of the comparator gradually decreases from a high voltage until it is lower than the positive input terminal of the comparator. REC Much higher than V S When M in the first stage amplifier P32 The drain output voltage V O31 is a low level voltage, which acts on the M in the second stage amplifier P33 The gate terminal makes M P33 conduction, so M P33 The drain output voltage V O32 is a high level voltage, which acts on the M in the dynamic bias circuit P34 The gate terminal makes M P34 At this time, due to M P34 is turned off, so M N38 No current flows through it. Then the M N33 and M N35 , tube M in the second stage amplifier N37 There is no current flowing through the comparator. N31 The small current I b31 (tens of nA) for biasing. P34 Turn off and M N39 conduction, so the first stage M of the driving circuit P35 M N310 Turn off; make the second stage M of the driving circuit N311 conduction, and M P36 Turn off. This makes the output voltage of the entire comparator V OUT is low level.

[0059] With V REC Gradually approaching V S, M in the first stage amplifier P32 The drain output voltage V O31 starts to rise. When V REC Very close to V S When V O31 The voltage will be close to the midpoint of the supply voltage. S With V O31 The difference is greater than the M in the second stage amplifier P33 After the threshold, M P33 Start shutting down, and then M P33 The drain output voltage V O32 starts to decrease. At this time, as V O32 decrease, which acts on the M in the dynamic bias circuit P34 and M N39 The gate end, at a certain moment M P34 With M N39 At this time, a large transient current (several μA to tens of μA) flows from the supercapacitor voltage V S Generates a large transient current that passes through the M in the dynamic bias circuit in turn. P34 、M N39 With M N38 Then it flows into the simulation ground. N38 The gate voltage of the amplifier is self-regulated according to the transient current. At the same time, the large transient current passes through the M in the first stage amplifier. N33 and M N35 , M in the second stage amplifier N37 The first and second amplifiers of the preamplifier are copied, so that the transconductance of the two-stage amplifier is enhanced, the amplification factor is also improved, and V O31 Rapidly rising V O32 Rapid descent.

[0060] When V REC Much lower than V S When M in the first stage amplifier P32 The drain output voltage V O31 is a high level voltage, which acts on the M in the second stage amplifier P33 The gate terminal makes M P33 is turned off, so M P33 The drain output voltage V O32 is a low level voltage, which acts on the M in the dynamic bias circuit N39 The gate terminal makes M N39 At this time, due to M N39 is turned off, so M N38 No current flows through it. Then the M N33 and M N35, M in the second stage amplifier N37 There is no current flowing through the comparator. N32 、M N34 and M N36 Only by M N31 The small current I b31 (tens of nA) for biasing. At the same time, since M N39 Shutdown, M P34 conduction, so the first stage M of the driving circuit N310 conduction, and M P35 Shutdown; Second stage M P36 On, M N311 Shutdown, so that the output voltage of the entire comparator V OUT is high level.

[0061] Figure 5 Compared Figure 2 The traditional comparator and Figure 3 The two waveforms in the first row of pictures are respectively the positive input voltage V S and the negative input voltage V REC , where V S is 2.5V, V REC Before 1.5μS and after 7.5μS, it is 2.49V, and between 1.5μS and 7.5μS, it is 2.51V. The two waveforms in the second row of pictures are the output waveforms of the comparator of the present invention and the traditional comparator. The transmission delay of the comparator of the present invention in the first working mode is about 177nS, while the transmission delay of the traditional comparator is 583nS; the transmission delay of the comparator of the present invention in the second working mode is about 170nS, while the transmission delay of the traditional comparator is 1450nS. The two waveforms in the third row of pictures are the output waveforms of the comparator of the present invention and the traditional comparator. P31 and M P32 The current flowing through M in static state P31 and M P32 The quiescent current is 60nA. P31 The dynamic bias current is about 6.5μA, and the current flowing through M P32 The dynamic bias current is about 1.5μA. The two waveforms in the fourth row are respectively V O31 and V O32 Thanks to the peak current in the third row of pictures, V O31 and V O32 It can rise or fall quickly. The two waveforms in the fifth row are respectively P21 and M P22 The current flowing through M in static state P21 and M P22The quiescent current is 60nA. P21 The maximum current flowing through M is about 110nA. P22 The maximum current is about 150nA. The two waveforms in the sixth row are V O21 and V O22 Since the current in the fifth row is smaller, V O21 and V O22 Can only ascend or descend slowly.

[0062] Contents not described in detail in the specification of the present invention belong to the well-known technologies of professionals in the field. Although the embodiments of the present invention are described in conjunction with the drawings, ordinary technicians in the field can make various modifications or changes within the scope of the attached claims.

Claims

1. A low power consumption and low transmission delay dynamic comparator, characterized in that: include: An external bias low current input circuit is used to continuously provide a static bias current for the preamplifier; A two-stage differential input single-ended output preamplifier comprises a first-stage amplifier and a second-stage amplifier connected in series, wherein the positive input terminal and the negative input terminal of the differential input are respectively connected to the power supply voltage and the output point voltage of the external rectifier circuit; the preamplifier provides a driving voltage for a dynamic bias inverter in a dynamic bias circuit; A dynamic bias circuit, composed of a dynamic bias inverter and a diode-connected NMOS tube connected in series, for selectively providing a dynamic bias current to the preamplifier according to the difference of the differential input of the preamplifier; When the differential input phase difference of the preamplifier is greater than a threshold, the driving voltage provided by the preamplifier is far away from the inversion threshold of the dynamic bias inverter, the dynamic bias inverter is in a stable output state, no dynamic bias current is provided, and the preamplifier is biased only by a static bias current; When the differential input phase difference of the preamplifier is less than or equal to the threshold, the driving voltage provided by the preamplifier is close to the inversion threshold of the dynamic bias inverter, the dynamic bias inverter is in an inversion state, and the current flowing through the dynamic bias inverter provides a dynamic bias current for the preamplifier through the NMOS tube connected by the diode, and the preamplifier is biased by the static bias current and the dynamic bias current; The driving circuit is composed of two inverters connected in series, and the dynamic bias circuit provides input signals and transmits them to the downstream load circuit.

2. The low power consumption and low transmission delay dynamic comparator according to claim 1, characterized in that: The external bias low current input circuit is a diode-connected NMOS tube M N31 , the diode connection refers to M N31 The gate and drain terminals are short-circuited, M N31 The drain end of M is connected to an external bias current, and the external bias current is a static bias current. N31 The source end of the ground, M N31 The gate end of the circuit serves as the output end of the external bias small current input circuit and is respectively connected to the first-stage amplifier and the second-stage amplifier in the pre-amplifier to provide a static bias current.

3. The low power consumption and low transmission delay dynamic comparator according to claim 1, characterized in that: The first stage amplifier in the pre-amplifier includes an NMOS tube M N32 、NMOS tube M N33 、NMOS tube M N34 、NMOS tube M N35 、PMOS tube M P31 And PMOS tube M P32 ; The M P31 The source end of M is used as the negative input end of the first stage amplifier, and is connected to the output point voltage of the external rectifier circuit; P32 The source end of is used as the positive input end of the first-stage amplifier and is connected to the supply voltage; M P31 The gate and drain terminals are short-circuited and connected to M P32 The gate terminal is connected to N32 、M N33 With M P31 The drain end is connected to N34 、M N35 With M P32 The drain end is connected to the output end of the first stage amplifier; M N32 With M N34 The gate terminal is connected to the external bias small current input circuit, M N33 With M N35 The gate terminal is connected to the dynamic bias circuit, M N32 、M N33 、M N34 With M N35 The source terminal is grounded.

4. The low power consumption and low transmission delay dynamic comparator according to claim 3, characterized in that: The second stage amplifier in the pre-amplifier is a common source amplifier.

5. The low power consumption and low transmission delay dynamic comparator according to claim 4, characterized in that: The common source amplifier is composed of NMOS tube M N36 、NMOS tube M N37 And PMOS tube M P33 constitute; The M P33 The gate end is connected to the output end of the first stage amplifier, M P33 The source end of the power supply voltage is connected, M P33 、M N36 With M N37 The drain end is connected to the output end of the second stage amplifier, M N36 The gate terminal is connected to an external bias low current input circuit, M N37 The gate terminal is connected to the dynamic bias circuit, M N36 With M N37 The source terminal is grounded.

6. The low power consumption and low transmission delay dynamic comparator according to claim 1, characterized in that: The dynamic bias circuit comprises an NMOS tube M N39 With PMOS tube M P34 The dynamic bias inverter and a diode-connected NMOS tube M N38 ; The M N39 With M P34 The drain end of M is connected to the voltage output end of the dynamic bias circuit to provide an input signal for the driving circuit; N39 With M P34 The gate terminal is connected to the output terminal of the second stage amplifier, M P34 The source end of the power supply voltage is connected, M N39 The source and M N38 The drain end is connected to N38 The gate terminal and the drain terminal of M are short-circuited to form a diode connection and serve as a dynamic bias current output terminal, which is used to provide a dynamic bias current for the first stage amplifier and the second stage amplifier; N38 The source terminal is grounded.

7. The low power consumption and low transmission delay dynamic comparator according to claim 1, characterized in that: The width-to-length ratio of the second-stage inverters connected in series in the driving circuit is 4-5 times that of the first-stage inverters.

8. The low power consumption and low transmission delay dynamic comparator according to claim 7, characterized in that: The second stage inverter has the same length as the first stage inverter.

9. An active diode, characterized in that: It comprises a PMOS tube M0 and the low-power low-transmission delay dynamic comparator as described in any one of claims 1 to 8, wherein the output end of the low-power low-transmission delay dynamic comparator is connected to the gate end of M0, and the source end and the drain end of M0 are respectively connected to the positive input end and the negative input end of the differential input of the low-power low-transmission delay dynamic comparator.

10. A piezoelectric vibration energy capture sensor system, characterized in that: It comprises a piezoelectric vibration energy capture sensor, a rectifier circuit, a super capacitor and the active diode module as described in claim 9, wherein the output end of the piezoelectric vibration energy capture sensor is connected to the negative input end of the comparator of the active diode module through the rectifier circuit, and the super capacitor is connected to the positive input end of the comparator of the active diode module to provide a power supply voltage.

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