Display device and method for manufacturing same

Abstract

The invention discloses a display device and a method for manufacturing the same. The display device includes: a substrate on which a display area and a non-display area are defined; a pixel disposed on the substrate, in which the pixel includes a pixel electrode disposed in an emission area in the display area, a light emitting layer disposed on the pixel electrode, and a common electrode disposed on the light emitting layer; an insulating layer disposed on the substrate and located in the non-display area and in the non-emission area between the emission areas of the pixels; and a conductive pattern disposed on the insulating layer to be separated from the pixel electrode of the pixel, in which the first voltage is applied to the conductive pattern. The insulating layer includes: a lower insulating layer in the display area between the pixel electrodes; and an upper insulating layer disposed on the lower insulating layer and having an area larger than an area of an upper surface of the lower insulating layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0095807, filed on Jul. 24, 2023, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0003] With the development of multimedia, the importance of display devices has gradually increased. Accordingly, various display devices such as liquid crystal display devices and organic light emitting display devices have been developed. Summary of the invention

[0004] Embodiments of the present disclosure provide a display device capable of preventing leakage current between pixels and a method for manufacturing the display device.

[0005] However, the embodiments of the present disclosure are not limited to the embodiments set forth herein. The above and other features of the embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the embodiments of the present disclosure given below.

[0006] According to an embodiment of the present disclosure, a display device includes: a substrate, on which a display area and a non-display area are defined; pixels, arranged on the substrate, wherein the pixels include pixel electrodes respectively arranged in emission areas located in the display area, light-emitting layers respectively arranged on the pixel electrodes, and a common electrode arranged on the light-emitting layers; an insulating layer, arranged on the substrate and located in the non-display area and in the non-emitting area between the emission areas of the pixels; and a conductive pattern, arranged on the insulating layer to be separated from the pixel electrode of the pixel, wherein a first voltage is applied to the conductive pattern, wherein the insulating layer includes: a lower insulating layer, located in the display area and between the pixel electrodes; and an upper insulating layer, arranged on the lower insulating layer and having an area larger than an area of ​​an upper surface of the lower insulating layer.

[0007] In an embodiment, the conductive pattern may include the same conductive material as the pixel electrode.

[0008] In an embodiment, the first voltage may be a turn-off voltage of a light emitting element including a pixel electrode, a light emitting layer, and a common electrode.

[0009] In an embodiment, the display device may further include: a first electrode located in the non-display area, disposed between the substrate and the insulating layer, and connected to the conductive pattern through a contact hole defined through the insulating layer.

[0010] In an embodiment, the display device may further include: a second electrode located in the non-emission region, disposed between the substrate and the insulating layer, and connected to the conductive pattern through a contact hole defined through the insulating layer.

[0011] In an embodiment, the upper insulating layer may completely cover an upper surface of the lower insulating layer and protrude further than the lower insulating layer toward an adjacent one of the pixels.

[0012] In an embodiment, the lower insulating layer may include an organic insulating material, and the upper insulating layer may include an inorganic insulating material.

[0013] In an embodiment, the thickness of the lower insulating layer may be greater than the thickness of the pixel electrode.

[0014] In an embodiment, the thickness of the lower insulating layer may be less than or equal to the sum of the thicknesses of the pixel electrode, the light emitting layer, and the common electrode.

[0015] In an embodiment, the common electrode of the pixel may be a common film covering the conductive pattern and is completely disposed in a display area including an emission area and a non-emission area.

[0016] In an embodiment, the thickness of the lower insulating layer may be greater than the sum of the thicknesses of the pixel electrode and the light emitting layer.

[0017] In an embodiment, the light emitting layers of the pixels may be separated from each other with a lower insulating layer interposed therebetween, and the display device may further include a dummy light emitting layer disposed in the non-emitting region, on the conductive pattern and separated from the light emitting layers of the pixels.

[0018] In an embodiment, the thickness of the lower insulating layer may be less than or equal to the sum of the thicknesses of the pixel electrode and the light emitting layer.

[0019] In an embodiment, the light emitting layer of the pixel may be a common film covering the conductive pattern, and may be completely disposed in a display area including an emission area and a non-emission area.

[0020] In an embodiment, when viewed in the thickness direction of the substrate, the conductive pattern may have a mesh shape provided with openings corresponding to emission regions of the pixels.

[0021] According to an embodiment of the present disclosure, a method for manufacturing a display device includes: forming a transistor and a connecting electrode in a display area on a substrate, and forming an auxiliary electrode in a non-display area on the substrate, wherein the display area and the non-display area located around the display area are defined on the substrate, and the connecting electrode is connected to the transistor; forming a lower insulating layer by applying an organic insulating material to the substrate on which the connecting electrode and the auxiliary electrode are formed, and etching the lower insulating layer in such a manner that a portion of the auxiliary electrode is exposed; forming an upper insulating layer by applying an inorganic insulating material to the substrate on which the lower insulating layer is formed, and etching the upper insulating layer in such a manner that the portion of the auxiliary electrode in the non-display area is exposed. The upper insulating layer is etched in such a manner that the auxiliary electrode is exposed and the portions of the lower insulating layer respectively in the emission area located in the display area are exposed; the lower insulating layer is etched using the upper insulating layer as a mask to pattern the lower insulating layer so as to be provided with openings corresponding to the portion of the auxiliary electrode and the emission area, respectively; each pixel electrode is formed in the emission area by applying a conductive material to a substrate on which the patterned lower insulating layer and upper insulating layer are formed, and a conductive pattern separated from the pixel electrode is formed on the exposed portion of the auxiliary electrode and the upper insulating layer; a light-emitting layer is formed on the substrate on which the pixel electrode and the conductive pattern are formed; and a common electrode is formed on the substrate on which the light-emitting layer is formed.

[0022] In an embodiment, in etching the lower insulating layer using the upper insulating layer as a mask, the lower insulating layer may be etched in such a manner that an upper surface of the lower insulating layer has an area smaller than that of a lower surface of the upper insulating layer.

[0023] In an embodiment, in the formation of each pixel electrode and the formation of the conductive pattern, the pixel electrode and the conductive pattern may be separated from each other by completely applying a conductive material at a height smaller than that of a lower insulating layer.

[0024] In an embodiment, in the formation of the common electrode, the common electrode may be completely formed in the display area by applying a conductive material for forming the common electrode at a height greater than or equal to a height of the lower insulating layer.

[0025] In an embodiment, the method for manufacturing a display device may further include: before the formation of the lower insulating layer, forming an inorganic insulating layer by applying an inorganic insulating material to a substrate on which a connecting electrode and an auxiliary electrode are formed, and etching the inorganic insulating layer in such a manner that a portion of the auxiliary electrode and a portion of each of the connecting electrodes are exposed.

[0026] In a display device according to an embodiment and a method for manufacturing a display device, a pixel electrode can be formed in each emission region by an insulating layer located in a non-emission region between a non-display region and an emission region of a pixel and including a lower insulating layer and an upper insulating layer to be automatically or naturally separated or disconnected from each other. In addition, through the insulating layer, a conductive pattern separated or disconnected from the pixel electrode can be formed on the insulating layer while forming the pixel electrode. Accordingly, the manufacturing process of the display device can be simplified, and if necessary, the distance between the emission regions of the pixel can be reduced or minimized.

[0027] In addition, in the display device and the method for manufacturing the display device according to the embodiment, the emission area can be defined by the insulating layer without providing a separate pixel defining layer on the pixel electrode. Accordingly, the structure and manufacturing process of the display device can be simplified, and the degree of freedom in the design of the display device can be improved.

[0028] In addition, in the display device according to the embodiment and the method for manufacturing the display device, the leakage current between pixels can be blocked, prevented or reduced by the insulating layer. In addition, the leakage current between pixels can be more effectively blocked, prevented or reduced by applying the first voltage to the conductive pattern on the insulating layer. The conductive pattern can be formed simultaneously with the pixel electrode, and can effectively block, prevent or reduce the leakage current without adding a process for forming a separate electrode or line for blocking the leakage current. Accordingly, the structure and manufacturing process of the display device can be simplified.

[0029] However, the effects according to the embodiments of the present disclosure are not limited to the above-exemplified effects, and various other effects are also included herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other features of the embodiments of the present disclosure will become more apparent by describing in detail the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is a plan view illustrating a display device according to an embodiment;

[0032] Figure 2 is a plan view illustrating a display device according to an embodiment;

[0033] Figure 3 is a schematic circuit diagram illustrating a pixel according to an embodiment;

[0034] Figure 4 The diagram shows the device Figure 1 A schematic plan view of a portion corresponding to area A1;

[0035] Figure 5 is a cross-sectional view illustrating a display device according to an embodiment;

[0036] Figure 6 is a cross-sectional view illustrating a display device according to an embodiment;

[0037] Figure 7 is a cross-sectional view illustrating a display device according to an embodiment;

[0038] Figure 8 The diagram shows the device Figure 1 A schematic plan view of a portion corresponding to area A1;

[0039] Fig. 9 is a cross-sectional view illustrating a display device according to an embodiment;

[0040] Fig.10 is a cross-sectional view illustrating a display device according to an embodiment; and

[0041] Figures 11 to 19 is a cross-sectional view illustrating a method for manufacturing the display device according to the embodiment. DETAILED DESCRIPTION

[0042] The present invention will now be described more fully below with reference to the accompanying drawings in which various embodiments of the present invention are shown. However, the present invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0043] It will also be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or intervening layers may also be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. Like reference numerals refer to like parts throughout the specification.

[0044] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present invention. Similarly, the second element may also be referred to as the first element.

[0045] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limited. As used herein, "one", "the (described)" and "at least one" do not represent quantitative restrictions, and are intended to include both singular and plural numbers, unless the context clearly indicates otherwise. Therefore, in the claim, mentioning "one" element and then mentioning "described" element includes one element and multiple elements. For example, "element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" is not interpreted as being limited to "one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the term "include" and / or its variants or "include" and / or its variants are used in this specification to indicate the presence of stated features, regions, wholes, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their groups.

[0046] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in one of the figures in the accompanying drawings is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device in one of the figures in the accompanying drawings is turned over, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, the term "below" or "below" can cover both upper and lower orientations.

[0047] The features of each of the various embodiments of the present disclosure may be partially or completely combined with each other and may be technically coordinated with each other in various ways, and the various embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined in this article.

[0049] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments. As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shapes resulting, for example, from manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the present disclosure.

[0050] Figure 1 is a plan view illustrating a display device 100 according to an embodiment. Figure 2 is a plan view illustrating a display device 100 according to an embodiment. For example, Figure 1 and Figure 2 Embodiments of the display device 100 having shapes different from each other are illustrated.

[0051] exist Figure 1 and Figure 2 , the structure of an embodiment of a display device 100 involving a display panel including a display area DA is briefly illustrated. The display device 100 may include a display panel and a driving circuit (e.g., a scan driver, a data driver, and a timing controller) for driving pixels PX. In an embodiment, at least some of the driving circuits may be formed and / or disposed inside the display panel. In another embodiment, the driving circuit may be provided outside the display panel and electrically connected to the display panel.

[0052] refer to Figure 1 and Figure 2 , the embodiment of the display device 100 can be provided in various shapes, that is, can have a shape that can be variously modified. In the embodiment, as Figure 1 As shown in , the display device 100 may be provided in the form of a panel having a rectangular shape on a plane defined by a first direction DR1 and a second direction DR2 crossing each other. Figure 1 As shown in , the display device 100 may include angular corners, but the display device 100 may also include rounded corners. Figure 2 As shown in , the display device 100 may be provided as a panel having a circular shape on a plane defined by the first direction DR1 and the second direction DR2. In addition, the display device 100 may have one of various other shapes. In an embodiment, for example, the display device 100 may have a non-rectangular polygonal shape, an elliptical shape, or other shapes.

[0053] In an embodiment, the display device 100 may be provided as a substantially flat panel having a uniform thickness in a third direction DR3 intersecting the first direction DR1 and the second direction DR2 (e.g., perpendicular to the first direction DR1 and the second direction DR2). In another embodiment, the display device 100 may be provided as a three-dimensional panel having a curved surface, etc. The display device 100 may be a substantially non-deformable rigid display device or may be a flexible display device that may be deformed (e.g., folded, bent, or curled) in at least a portion thereof.

[0054] In an embodiment, Figure 1 and Figure 2 As shown in , the display device 100 may have a rectangular shape or a circular shape on a plane defined by the first direction DR1 and the second direction DR2, and is provided to be substantially flat. Figure 1 and Figure 2 As shown in , the longitudinal direction (e.g., column direction) of the display device 100 is indicated as a first direction DR1, the transverse direction (e.g., row direction) of the display device 100 is indicated as a second direction DR2, and the thickness direction (e.g., height direction) of the display device 100 is indicated as a third direction DR3.

[0055] In an embodiment, the display device 100 may include a substrate 110 and pixels PX disposed on the substrate 110. The pixels PX may be disposed on the substrate 110 in the display area DA.

[0056] The substrate 110 is a base member for manufacturing or providing the display device 100 and may constitute a base surface of the display device 100. The substrate 110 may include a display area DA and a non-display area NA (also referred to as a "frame area") disposed or defined around the display area DA.

[0057] The display area DA is an area where an image is displayed, and may have various shapes. In an embodiment, for example, the display area DA may have various shapes including a rectangular shape, a non-rectangular polygonal shape, a circular shape, or an elliptical shape.

[0058] In an embodiment, the display area DA may have a shape corresponding to (eg, substantially similar to) the shape of the display device 100 (or the substrate 110). In an embodiment, for example, the display area DA may have a shape such as Figure 1 The rectangular shape in the embodiment of Figure 2 However, the embodiment is not limited thereto, and the display area DA may also have a shape different from that of the display device 100 (or the substrate 110).

[0059] The display area DA may include a pixel region in which the pixels PX are provided and / or arranged. In an embodiment, for example, one pixel PX may be provided in each pixel region located in the display area DA.

[0060] Each pixel area may include an emission area in which at least one light emitting element is provided or formed and emits light of a specific color (e.g., red light, green light, or blue light). In an embodiment, for example, each pixel PX may include a light emitting element disposed in each emission area. Each pixel PX may further include a pixel circuit connected to the light emitting element. The pixel area of ​​the pixel PX may include an emission area in which the light emitting element is disposed and a pixel circuit area in which the circuit element of the pixel circuit is disposed. The emission area and the pixel circuit area of ​​each pixel may overlap each other, or may not overlap each other.

[0061] The pixel PX may have various shapes. In an embodiment, the shape of each of the pixels PX may be defined based on the shape of the emission region corresponding thereto. In an embodiment, for example, each pixel PX may have a shape such as Figure 1 and Figure 2 The rectangular shape shown in the figure may have a non-rectangular polygonal shape (for example, a hexagonal shape, an octagonal shape, etc.), a circular shape, an elliptical shape, or other shapes.

[0062] The pixels PX may be arranged in the display area DA according to various arrangement structures. In an embodiment, for example, the pixels PX may be arranged in a stripe structure, a triangle structure, Structures or other arrangements are arranged in the display area DA.

[0063] The non-display area NA may be an area other than the display area DA. Lines, pads, and / or embedded circuit units connected to the pixels PX (e.g., a scan driver formed on the substrate 110 together with the pixels PX) may be disposed on the substrate 110 in the non-display area NA. In an embodiment, an integrated circuit chip including at least some of the drive circuits (e.g., a data driver) may be disposed or mounted on the substrate 110 in the non-display area NA.

[0064] Figure 3 is a schematic circuit diagram illustrating a pixel PX according to an embodiment.

[0065] remove Figure 1 and Figure 2 In addition, reference Figure 3Each pixel PX may include a light emitting element EL connected to a first power line VDL to which a first power voltage ELVDD is applied and a second power line VSL to which a second power voltage ELVSS is applied. Each pixel PX may further include a pixel circuit PXC connected to the light emitting element EL to control a driving current supplied to the light emitting element EL.

[0066] The pixel circuit PXC may be connected between the first power line VDL and the light emitting element EL. Depending on the structure and / or type of the pixel circuit PXC, the pixel circuit PXC may also be connected between the light emitting element EL and the second power line VSL.

[0067] The pixel circuit PXC may be further connected to at least one scan line SL to which at least one scan signal is applied and a data line DL to which a data signal is applied. Depending on the structure, type and / or driving method of the pixel circuit PXC, the pixel circuit PXC may be further connected to at least one other power supply line to which an initialization source voltage or a bias voltage is supplied, or an emission control line to which an emission control signal is supplied.

[0068] The pixel circuit PXC can control the driving current supplied to the light emitting element EL in response to the driving signal supplied to the pixel PX. In an embodiment, for example, the pixel circuit PXC can control the magnitude and supply timing of the driving current supplied to the light emitting element EL in response to the driving signal including the scan signal or the data signal.

[0069] The pixel circuit PXC may include a circuit element for controlling a driving current flowing to the pixel PX in response to a driving signal. In an embodiment, for example, the pixel circuit PXC may include a circuit element including a switching transistor, a capacitor, and a driving transistor, the switching transistor being used to transmit a data signal supplied to the data line DL to the pixel PX during a period in which a scanning signal of a gate-on voltage is supplied to the scanning line SL, the capacitor being used to store the data signal, and the driving transistor being used to generate a driving current corresponding to the data signal. In an embodiment, the pixel circuit PXC may further include at least one other transistor for compensating for brightness deviations between pixels PX, etc.

[0070] The light emitting element EL may be connected between the pixel circuit PXC and the second power supply line VSL. The light emitting element EL may emit light in response to a drive current supplied from the pixel circuit PXC. In an embodiment, for example, during a period in which a drive current is supplied from the pixel circuit PXC, the light emitting element EL may emit light having a brightness corresponding to the magnitude of the drive current.

[0071] Figure 4 The diagram shows the display device 100. Figure 1 A schematic plan view of a portion corresponding to area A1 of FIG. Figure 4 As shown in , the emission areas EA of the pixels PX may have substantially the same shape and / or size, but the embodiment is not limited thereto. In the embodiment, for example, the display device 100 may include pixels PX including emission areas EA having different shapes and / or sizes (e.g., first color pixels, second color pixels, and / or third color pixels including emission areas EA having different shapes and / or sizes). In addition, in Figure 4 An embodiment having a structure in which the emission areas EA are arranged in a matrix form along the first direction DR1 and the second direction DR2 is illustrated in FIG. 1 , but the arrangement structure of the emission areas EA may be variously changed or modified depending on the embodiment.

[0072] remove Figures 1 to 3 In addition, reference Figure 4 In an embodiment, the display area DA may include the emission area EA of the pixel PX. In addition, the display area DA may further include a non-emission area NEA in addition to the emission area EA. The non-emission area NEA may be disposed between and / or around the emission area EA. The non-emission area NEA may surround each emission area EA.

[0073] At least one light emitting element EL may be provided or disposed in each emission area EA. In an embodiment, for example, a first electrode ET1 (hereinafter, referred to as a “pixel electrode ET1”) of the light emitting element EL may be disposed in each emission area EA. Figure 5 ) and the second electrode ET2 (see Figure 5 ) (hereinafter, referred to as “common electrode ET2”) may be sequentially disposed and / or stacked on the pixel electrode ET1.

[0074] A conductive pattern CDP may be provided in the non-display area NA and the non-emission area NEA of the display area DA. The conductive pattern CDP may be provided with an opening OPN defined therethrough to correspond to the emission area EA. In an embodiment, for example, a grid-like conductive pattern CDP may be provided in the non-display area NA and the non-emission area NEA of the display area DA, the grid-like conductive pattern CDP being provided with an opening having a size and / or shape corresponding to the size and / or shape of the emission area EA and being disconnected or separated from the pixel electrode ET1 provided in the emission area EA. In an embodiment, for example, when observed from the top of the substrate 110, that is, when observed in a plan view or when observed in a third direction DR3, the conductive pattern CDP may have a grid shape containing an opening OPN corresponding to the emission area EA of the pixel PX.

[0075] In an embodiment, the conductive pattern CDP may overlap the pixel electrode ET1 in a region corresponding to an edge of the emission area EA. However, the conductive pattern CDP may be disconnected or separated from the pixel electrode ET1 with at least one insulating layer interposed therebetween.

[0076] The conductive pattern CDP may be connected to at least one auxiliary electrode and / or power line through at least one contact portion CNT defined or formed in the non-display area NA, etc. (e.g., at least one first contact portion CNT1 located in the non-display area NA). A first voltage may be applied to the conductive pattern CDP through the auxiliary electrode and / or the power line. In an embodiment, for example, a first voltage may be applied to the conductive pattern CDP from an auxiliary electrode and / or a power line located below the conductive pattern CDP through the contact portion CNT. Figure 4 The first voltage is applied or transmitted to the grid-like conductive pattern CDP in the direction indicated by the dotted arrow in FIG.

[0077] In an embodiment, the first voltage may be a voltage capable of blocking or preventing leakage current from flowing between the emission areas EA. In an embodiment, for example, the first voltage may be a cut-off voltage of the light emitting element EL, or may be a bias voltage or initialization voltage corresponding to the cut-off voltage. In an embodiment, the first voltage may be the second source voltage ELVSS, or may be a voltage having a level close to that of the second source voltage ELVSS (for example, a voltage having a difference corresponding to a threshold voltage below the light emitting element EL compared to the second source voltage ELVSS). The first voltage may be set to an appropriate value within a range determined to block, prevent or reduce leakage current that may occur in the display area DA.

[0078] The non-display area NA may be provided with at least one contact portion CNT (also referred to as a "first contact portion CNT1"). In the embodiment, for example, for convenience of illustration, only Figure 4 Although one contact portion CNT is illustrated in FIG. 1 , a plurality of contact portions CNT may be defined or formed in the non-display area NA surrounding the display area DA. Each contact portion CNT may include at least one contact hole and / or through hole.

[0079] Figure 5 is a cross-sectional view illustrating a display device 100 according to an embodiment. For example, Figure 5 Schematically illustrates the Figure 4 A cross section of the embodiment of the display device 100 taken along line X1 - X1 ′.

[0080] Figure 5 Schematically illustrates a cross section of a transistor Tpx, a capacitor Cst, and a light emitting element EL among the elements provided to each pixel PX. Figure 5 , among the circuit elements provided in the pixel circuit PXC, the transistor Tpx connected to the light emitting element EL and the capacitor Cst connected to the gate electrode GE of the transistor Tpx are illustrated. However, the cross section of the pixel PX may be variously changed depending on the type and structure of each pixel PX, etc. In an embodiment, for example, the capacitor Cst may be connected to one electrode (e.g., gate electrode) of another transistor provided in the pixel circuit PXC, and one electrode of the capacitor Cst may be integrated with one electrode of the other transistor.

[0081] remove Figures 1 to 4 In addition, reference Figure 5 , the display device 100 may include a substrate 110 and a circuit layer 120, a light emitting element layer 130, and an encapsulation layer 140 disposed on the substrate 110. In an embodiment, the circuit layer 120, the light emitting element layer 130, and the encapsulation layer 140 may be sequentially disposed or stacked on the substrate 110 along the third direction DR3.

[0082] exist Figure 5 100 is illustrated in the embodiment of the display device 100 having a structure in which the light emitting element layer 130 is disposed on the circuit layer 120, but the embodiment is not limited thereto. In the embodiment, for example, the light emitting element layer 130 and the circuit layer 120 may be sequentially disposed on the substrate 110, or the circuit layer 120 and the light emitting element layer 130 may be integrated with each other.

[0083] In addition, Figure 5 1 and 2 illustrate an embodiment of the display device 100 having a structure in which the light emitting element layer 130 is encapsulated using the encapsulation layer 140, but the embodiment is not limited thereto. In the embodiment, for example, the light emitting element layer 130 may also be encapsulated using a separate upper substrate.

[0084] In addition, embodiments of the display device 100 may further include additional components in addition to the circuit layer 120, the light emitting element layer 130, and / or the encapsulation layer 140. In an embodiment, for example, the display device 100 may further include a sensor layer including a touch sensor, a color filter layer including a color filter, or a color conversion layer including a wavelength conversion pattern, the wavelength conversion pattern including wavelength conversion particles.

[0085] The substrate 110 may include or be made of a material having flexible properties so as to be able to be bent, folded, or curled. The substrate 110 may include or be made of an insulating material such as a polymer resin. In an embodiment, for example, the substrate 110 may include or be made of polyimide. The substrate 110 may include a display area DA and a non-display area NA located around the display area DA, the display area DA including an emission area EA of the pixel PX and a non-emission area NEA located around the emission area EA.

[0086] The circuit layer 120 may include circuit elements constituting the pixel circuit PXC of each pixel PX. In an embodiment, for example, the circuit layer 120 may include a transistor Tpx and a capacitor Cst provided in each pixel circuit PXC. The pixel circuit PXC including the transistor Tpx may be electrically connected to the light emitting element EL of the corresponding pixel PX. The transistor Tpx may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2.

[0087] The circuit layer 120 may further include lines connected to the pixels PX. In an embodiment, for example, the circuit layer 120 may include signal lines including scan lines SL and data lines DL, and power lines including first power lines VDL and second power lines VSL.

[0088] The circuit layer 120 may include a conductive layer for forming (or defining) circuit elements and lines, at least one semiconductor layer SCL, and an insulating layer provided between the conductive layer and the semiconductor layer SCL. In an embodiment, for example, the circuit layer 120 may include a buffer layer 121, a semiconductor layer SCL, a first insulating layer 122, a first conductive layer CDL1 (e.g., a first gate conductive layer), a second insulating layer 123, a second conductive layer CDL2 (e.g., a second gate conductive layer), a third insulating layer 124, a third conductive layer CDL3 (e.g., a first source-drain conductive layer), and a fourth insulating layer 125 sequentially disposed on the substrate 110 in the third direction DR3. In an embodiment, the circuit layer 120 may further include a fourth conductive layer CDL4 (e.g., a second source-drain conductive layer) and a fifth insulating layer 126 sequentially disposed on the fourth insulating layer 125. In an embodiment, the circuit layer 120 may further include an additional conductive layer (e.g., a bridge electrode connected to each connection electrode CNE and / or a third source-drain conductive layer including at least one line, etc.) disposed on the fifth insulating layer 126 and an insulating layer covering the additional conductive layer. The structure of the circuit layer 120 is not particularly limited and may be variously changed or modified depending on the embodiment.

[0089] The buffer layer 121 may include at least one inorganic film including an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials. According to embodiments, the material of the buffer layer 121 may be variously changed or modified.

[0090] In an embodiment, an additional conductive layer may be disposed between the substrate 110 and the buffer layer 121. In an embodiment, for example, a conductive layer including a light shielding layer and / or at least one line (or a portion of at least one line) overlapping the active layer ACT of at least one transistor Tpx may be disposed between the substrate 110 and the buffer layer 121.

[0091] A semiconductor layer SCL may be provided on one surface of the substrate 110 on which the buffer layer 121 is formed. The semiconductor layer SCL may include an active layer ACT of each of the transistors Tpx. Each active layer ACT may include polycrystalline silicon (e.g., low temperature polycrystalline silicon), single crystal silicon, amorphous silicon, or an oxide semiconductor material. Each active layer ACT may include a channel region, a source region, and a drain region.

[0092] The first insulating layer 122 may cover the semiconductor layer SCL. In an embodiment, the first insulating layer 122 may include at least one inorganic film including an inorganic insulating material.

[0093] A first conductive layer CDL1 may be provided on the first insulating layer 122. The first conductive layer CDL1 may include a gate electrode GE of each of the transistors Tpx. Each gate electrode GE may include a conductive material (e.g., at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and other metals, alloys thereof, or other conductive materials), and may be a single-layer electrode or a multi-layer electrode, i.e., an electrode having a single-layer structure or a multi-layer structure.

[0094] The first conductive layer CDL1 may further include at least one line (or a portion of at least one line), a bridge pattern and / or a capacitor electrode. In an embodiment, for example, the first conductive layer CDL1 may further include a first capacitor electrode CE1 of the capacitor Cst. In an embodiment, the first capacitor electrode CE1 may be formed integrally with the gate electrode GE of the transistor Tpx connected thereto. Figure 5 1 illustrates an embodiment in which the first capacitor electrode CE1 is integrally formed with the gate electrode GE of the transistor Tpx connected to the light emitting element EL, but the embodiment is not limited thereto. In the embodiment, for example, depending on the structure of the pixel circuit PXC, the transistor Tpx whose gate electrode GE is directly connected to the first capacitor electrode CE1 may also be connected to the light emitting element EL via another transistor or the like.

[0095] The second insulating layer 123 may cover the first conductive layer CDL1. In an embodiment, the second insulating layer 123 may include at least one inorganic film including an inorganic insulating material.

[0096] A second conductive layer CDL2 may be provided on the second insulating layer 123. The second conductive layer CDL2 may further include at least one line (or a portion of at least one line), a bridge pattern, and / or a capacitor electrode. As an example, the second conductive layer CDL2 may include a second capacitor electrode CE2 of the capacitor Cst. The first capacitor electrode CE1 and the second capacitor electrode CE2 of the capacitor Cst may overlap each other in the thickness direction of the substrate 110 or in the third direction DR3. In an embodiment, when each pixel PX further includes Figure 5 When the transistor Tpx shown in the figure is formed in at least one transistor of a different layer, the second conductive layer CDL2 may further include a gate electrode (or a back gate electrode) of the at least one transistor.

[0097] The third insulating layer 124 may cover the second conductive layer CDL2. In an embodiment, the third insulating layer 124 may include at least one inorganic film including an inorganic insulating material.

[0098] A third conductive layer CDL3 may be provided on the third insulating layer 124. The third conductive layer CDL3 may include a source electrode SE and a drain electrode DE of each of the transistors Tpx. Each of the source electrode SE and the drain electrode DE may include a conductive material and may be a single-layer electrode or a multi-layer electrode. In another embodiment, the source electrode SE and / or the drain electrode DE of each of the transistors Tpx may be formed as a source region and / or a drain region of the active layer ACT (or defined by a source region and / or a drain region of the active layer ACT), and the third conductive layer CDL3 may include at least one bridge electrode connected to the source electrode SE and / or the drain electrode DE of at least one transistor Tpx, etc. In an embodiment, the third conductive layer CDL3 may further include at least one line (or a portion of at least one line), a bridge pattern and / or a capacitor electrode. In an embodiment, for example, the third conductive layer CDL3 may further include a first power line VDL (or a portion of the first power line VDL) and / or a second power line VSL (or a portion of the second power line VSL).

[0099] The fourth insulating layer 125 may cover the third conductive layer CDL3. In an embodiment, the fourth insulating layer 125 may include at least one organic film including an organic insulating material (eg, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating material) to planarize the circuit layer 120, but is not limited thereto.

[0100] A fourth conductive layer CDL4 may be provided on the fourth insulating layer 125. The fourth conductive layer CDL4 may include a connection electrode CNE (or a bridge electrode) for connecting the transistor Tpx to each light emitting element EL. Each connection electrode CNE may be provided on a corresponding transistor Tpx, and may electrically connect the transistor Tpx to the light emitting element EL of the corresponding pixel PX. Each connection electrode CNE may include a conductive material, and may be a single-layer electrode or a multi-layer electrode. In an embodiment, the fourth conductive layer CDL4 may further include at least one line (or a portion of at least one line), a bridge pattern and / or a capacitor electrode. In an embodiment, for example, the fourth conductive layer CDL4 may further include a first power line VDL (or a portion of the first power line VDL) and / or a second power line VSL (or a portion of the second power line VSL).

[0101] The fourth conductive layer CDL4 may further include at least one first electrode AXE1 (also referred to as an "auxiliary electrode" or a "first auxiliary electrode") provided at a position corresponding to the at least one contact portion CNT. In an embodiment, for example, the fourth conductive layer CDL4 may include at least one first electrode AXE1 provided at a position corresponding to the at least one contact portion CNT located in the non-display area NA. In an embodiment, for example, the fourth conductive layer CDL4 may include a plurality of first electrodes AXE1 each provided at a position corresponding to a plurality of contact portions CNT distributed in the non-display area NA.

[0102] The first electrode AXE1 may be connected to the conductive pattern CDP through a first contact hole CH1 defined or formed in each contact portion CNT. In an embodiment, for example, the conductive pattern CDP is disposed on the first electrode AXE1 exposed by the first contact hole CH1 in each contact portion CNT, so that the first electrode AXE1 and the conductive pattern CDP may be electrically connected to each other. In an embodiment, the first electrode AXE1 may be formed simultaneously with the connection electrode CNE of the display area DA through the same process.

[0103] In an embodiment, the first electrode AXE1 may be connected to a power line PL (eg, a second power line VSL) to which a first voltage is applied, or may be a part of the power line PL. Accordingly, a first voltage may be applied to the conductive pattern CDP through the first electrode AXE1. In an embodiment, the first electrode AXE1 may be provided in the non-display area NA.

[0104] exist Figure 5, an embodiment in which the first electrode AXE1 is provided at the fourth conductive layer CDL4 is illustrated, but the position of the first electrode AXE1 may be variously changed or modified depending on the embodiment. In the embodiment, for example, the first electrode AXE1 may also be provided at another conductive layer (e.g., the first conductive layer CDL1, the second conductive layer CDL2, and / or the third conductive layer CDL3) provided in the circuit layer 120.

[0105] In addition, Figure 5 , an embodiment in which the first electrode AXE1 is provided at a single conductive layer is illustrated, but the embodiment is not limited thereto. In the embodiment, for example, the first electrode AXE1 may also be a multi-layer electrode or line provided at at least two conductive layers provided in the circuit layer 120 .

[0106] In an embodiment, the display device 100 may not include the fourth conductive layer CDL4. In such an embodiment, one electrode of the transistor Tpx provided at the third conductive layer CDL3 (or a bridge electrode provided at the third conductive layer CDL3 and connected to the active layer ACT of the transistor Tpx) may be directly connected to the corresponding light emitting element EL.

[0107] The fifth insulating layer 126 may cover the conductive layer (eg, the fourth conductive layer CDL4) where the first electrode AXE1 and the like are provided. In an embodiment, the fifth insulating layer 126 may include at least one inorganic film including an inorganic insulating material, but is not limited thereto. In an embodiment, for example, the fifth insulating layer 126 may also include an organic film.

[0108] The fifth insulating layer 126 may be provided with an opening (e.g., a first contact hole CH1) defined therethrough to expose a portion of the first electrode AXE1. In an embodiment, for example, the fifth insulating layer 126 may be opened at a position corresponding to the contact portion CNT to expose a portion of the first electrode AXE1. The opening of the fifth insulating layer 126 formed on the first electrode AXE1 may define a position where the contact portion CNT is to be formed.

[0109] In addition, the fifth insulating layer 126 may be provided with an opening (e.g., a second contact hole CH2) defined therethrough to expose a portion of each connection electrode CNE. In an embodiment, for example, the fifth insulating layer 126 may be opened at a position corresponding to each connection electrode CNE to expose a portion of each connection electrode CNE. The opening of the fifth insulating layer 126 formed on each connection electrode CNE may define a position where the light emitting element EL and the pixel circuit PXC (or the connection electrode CNE) are to be connected to each other.

[0110] The light emitting element layer 130 may include an insulating layer INS defining and / or partitioning emission areas EA and contact portions CNT, light emitting elements EL located in respective emission areas EA, and a conductive pattern CDP disposed on the insulating layer INS.

[0111] The insulating layer INS may be located on the substrate 110, in the non-emission area NEA between the non-display area NA and the emission area EA. In an embodiment, for example, the insulating layer INS may be disposed on the circuit layer 120 (e.g., disposed on the fifth insulating layer 126), and may be located in the non-emission area NEA and the non-display area NA. The insulating layer INS may surround the emission area EA and define each emission area EA. The emission areas EA of two adjacent pixels PX may be spaced apart from each other by a distance corresponding to the width of the insulating layer INS located therebetween. Accordingly, the emission area EA may be appropriately defined and / or divided without forming a separate pixel defining layer, etc. on the pixel electrode ET1 of the light emitting element EL, so that the structure and manufacturing process of the display device 100 may be simplified, and the degree of freedom in the design of the display device 100 may be increased.

[0112] The insulating layer INS may define openings corresponding to the emission area EA and the contact portion CNT, respectively, and may surround the emission area EA and the contact portion CNT (e.g., the first contact hole CH1). In an embodiment, for example, when viewed from the top of the substrate 110 or when viewed in the third direction DR3, the insulating layer INS may have a thickness corresponding to the emission area EA and the contact portion CNT, respectively. Figure 4 An insulating pattern having a position and shape (eg, a mesh shape) corresponding to the position and shape of the conductive pattern CDP illustrated in FIG.

[0113] The insulating layer INS may have a shape, structure, thickness and / or height in which the respective pixel electrodes ET1 may be formed in the emission area EA to be automatically (or naturally) and / or immediately separated (e.g., disconnected) from each other while applying (e.g., depositing) a conductive material in a process in which a conductive film for forming the respective pixel electrodes ET1 (e.g., the anode electrode of the light emitting element EL) is formed in the emission area EA. Accordingly, even in a high-resolution display device in which the area of ​​each of the pixels PX and / or the distance between the pixels PX is significantly smaller or significantly reduced than a display device with a relatively low resolution, the pixel electrodes ET1 and / or the conductive pattern CDP may be easily separated from each other and / or patterned. In an embodiment, for example, instead of patterning the pixel electrodes ET1 using a high-resolution mask corresponding to the emission area EA, the respective pixel electrodes ET1 may be formed in the emission area EA to be separated from each other by applying a conductive material entirely to a substrate 110 on which an insulating layer INS or the like is formed. Accordingly, in the embodiments described above, the distance between the emission areas EA spaced apart from each other can be appropriately reduced or minimized as needed without the process difficulties or limitations caused by the high-resolution mask process. In addition, the pixel electrodes ET1 are formed to be stably and / or easily separated from each other by the insulating layer INS, so that the manufacturing process of the display device 100 can be simplified and facilitated and the defects of the display device 100 can be effectively prevented or significantly reduced.

[0114] In an embodiment, the insulating layer INS may be at least a double-layer insulating film or insulating pattern. In an embodiment, for example, the insulating layer INS may include a lower insulating layer INS1 having a thickness (or height) greater than that of each of the pixel electrodes ET1 and an upper insulating layer INS2 disposed on the lower insulating layer INS1.

[0115] In an embodiment, the lower insulating layer INS1 may have a thickness less than or equal to the sum of the thicknesses of the pixel electrode ET1, the light emitting layer EML, and the common electrode ET2 constituting each light emitting element EL, and the light emitting elements EL may share the common electrode ET2 formed as a single integral pattern with each other. In an embodiment, for example, the common electrode ET2 of the light emitting element EL may be formed as a common film covering (extending over) the conductive pattern CDP or the like disposed in the non-emission area NEA, and may be completely disposed in the display area DA including the emission area EA and the non-emission area NEA.

[0116] The lower insulating layer INS1 may be located between the pixel electrodes ET1 in the respective emission areas EA in the display area DA. In an embodiment, for example, the lower insulating layer INS1 may be located in the non-emission area NEA in the display area DA so as to be located between and / or around the pixel electrodes ET1, and may surround the respective pixel electrodes ET1. The lower insulating layer INS1 may be disposed on the fifth insulating layer 126 in the non-display area NA, and may include an opening (e.g., a first contact hole CH1) corresponding to the contact portion CNT.

[0117] The upper insulating layer INS2 may be disposed on the lower insulating layer INS1. In an embodiment, for example, the upper insulating layer INS2 may be located in the non-emission area NEA between the emission areas EA in the display area DA, and may be located at a height higher than that of the pixel electrode ET1. The upper insulating layer INS2 may be disposed on the lower insulating layer INS1 in the non-display area NA, and may include an opening (e.g., a first contact hole CH1) corresponding to the contact portion CNT.

[0118] In an embodiment, at an interface where the lower insulating layer INS1 and the upper insulating layer INS2 contact each other, the lower insulating layer INS1 and the upper insulating layer INS2 may have different areas, and the upper insulating layer INS2 may protrude outwardly than the lower insulating layer INS1 at the interface, that is, the upper insulating layer INS2 may protrude toward the adjacent pixel in the pixel PX than the lower insulating layer INS1. In an embodiment, for example, the upper insulating layer INS2 may have an area larger than the area of ​​the upper surface of the lower insulating layer INS1. In an embodiment, for example, the upper insulating layer INS2 may have an area at least larger than the area of ​​the upper surface of the lower insulating layer INS1, and may completely cover the upper surface of the lower insulating layer INS1. Accordingly, on the side surface of the insulating layer INS, the upper insulating layer INS2 may protrude outwardly than the lower insulating layer INS1. In an embodiment having the above structure, in the process of applying a conductive material for forming the pixel electrode ET1, the pixel electrodes ET1 may be more stably separated from each other and patterned. In an embodiment, the upper insulating layer INS2 may overlap the pixel electrode ET1 at the edge of the emission area EA.

[0119] The lower insulating layer INS1 and the upper insulating layer INS2 may include different insulating materials. In an embodiment, for example, the lower insulating layer INS1 may include an organic insulating film including at least one layer of an organic insulating material, and the upper insulating layer INS2 may include an inorganic insulating film including at least one layer of an inorganic insulating material. In an embodiment, for example, the lower insulating layer INS1 may be an organic insulating layer including polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB) or other organic insulating materials, and the upper insulating layer INS2 may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide or other inorganic insulating materials. In an embodiment, the lower insulating layer INS1 may be patterned by an etching process using the upper insulating layer INS2 as a mask.

[0120] The conductive pattern CDP may be disposed on the insulating layer INS. For example, the conductive pattern CDP may be separated from the pixel electrode ET1 of the pixel PX and disposed on the upper insulating layer INS2.

[0121] In an embodiment, the conductive pattern CDP may be formed simultaneously with the pixel electrode ET1 in a process of forming the pixel electrode ET1 (which includes a process of applying a conductive material for forming the pixel electrode ET1), and may be automatically or naturally separated from the pixel electrode ET1 by the insulating layer INS. In an embodiment, for example, the conductive pattern CDP is formed using a conductive material for forming the pixel electrode ET1, and may include the same conductive material as the pixel electrode ET1.

[0122] In the contact portion CNT, the conductive pattern CDP may be connected to the first electrode AXE1 under the insulating layer INS through the first contact hole CH1 defined through the insulating layer INS. The conductive pattern CDP may receive a first voltage supplied through the first electrode AXE1 and / or a power line PL connected to the first electrode AXE1.

[0123] In an embodiment, a dummy light emitting layer EMLd may be provided on the conductive pattern CDP. The dummy light emitting layer EMLd may be formed simultaneously with the light emitting layer EML in the process of forming the light emitting layer EML of each of the light emitting elements EL, and may be separated from the light emitting layer EML of each of the light emitting elements EL. In an embodiment, for example, the thickness of the lower insulating layer INS1 may be greater than the sum of the thicknesses of the pixel electrode ET1 and the light emitting layer EML of each of the light emitting elements EL, and in the process of forming the light emitting layer EML, the light emitting layer EML may be formed in each emission area EA while the material for forming the light emitting layer EML is fully applied to the display area DA, etc., so as to be separated from each other. In this process, the light emitting layers EML of the light emitting elements EL provided in the pixel PX may be separated from each other, with the lower insulating layer INS1 interposed therebetween. In addition, in the non-emission area NEA and the non-display area NA, a dummy light emitting layer EMLd separated from the light emitting layer EML of the light emitting element EL may be formed on the conductive pattern CDP. Even if the dummy light emitting layer EMLd or the like is disposed on the conductive pattern CDP, the occurrence of leakage current in the display area DA may be blocked, prevented, and / or reduced by applying the first voltage to the conductive pattern CDP.

[0124] Each light emitting element EL may include a pixel electrode ET1 (e.g., an anode electrode of the light emitting element EL) disposed in the corresponding emission area EA, a light emitting layer EML disposed on the pixel electrode ET1, and a common electrode ET2 (e.g., a cathode electrode of the light emitting element EL) disposed on the light emitting layer EML. In an embodiment, each light emitting element EL may be connected to a transistor Tpx of a pixel circuit PXC via at least one connection electrode CNE provided in a corresponding pixel PX. In an embodiment, for example, the pixel electrode ET1 of each pixel PX may be electrically connected to at least one transistor Tpx provided in a pixel circuit PXC of the corresponding pixel PX via a corresponding connection electrode CNE.

[0125] The pixel electrode ET1 may include a conductive material and may be disposed on the circuit layer 120. In an embodiment, for example, the pixel electrode ET1 may be disposed on the fifth insulating layer 126 so as to correspond to each emission area EA, and may be connected to the connection electrode CNE through the second contact hole CH2. In an embodiment, the pixel electrode ET1 may include a metal material having a high reflectivity. In an embodiment, for example, the pixel electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3) and multilayer structures of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) or nickel (Ni) (e.g., ITO / Mg, ITO / MgF 2 , ITO / Ag, ITO / Ag / ITO, etc.).

[0126] The light-emitting layer EML may include a polymer material or a low-molecular material. The light emitted from the light-emitting layer EML may contribute to image display. In an embodiment, the pixel PX may include a light-emitting layer EML comprising the same type, structure and / or material and emitting light of a specific color (e.g., white light or blue light), and a color filter and / or a wavelength conversion pattern corresponding to the color (or band) of the light to be emitted from each pixel PX may be provided in the emission area EA of at least some of the pixels PX. In an embodiment, for example, a light conversion layer including a color filter and / or a wavelength conversion pattern may be provided above the light-emitting element layer 130 (e.g., between the light-emitting element layer 130 and the encapsulation layer 140, above the encapsulation layer 140, or between the light-emitting element layer 130 and a separate upper substrate). In another embodiment, a light-emitting layer EML may be provided for each pixel PX or each of the pixels PX of a specific color, and the light-emitting layer EML of each pixel PX may emit light of a color corresponding to the corresponding pixel PX. The display device 100 in which the light emitting layer EML of each pixel PX emits light of a color corresponding to the corresponding pixel PX may or may not include a light conversion layer including a color filter and / or a wavelength conversion pattern.

[0127] The common electrode ET2 may include a conductive material and may be connected to the second power line VSL. In an embodiment, the common electrode ET2 may include a transparent conductive material (TCO) such as ITO or IZO through which light can be transmitted, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag), or may be made of the same. In an embodiment in which the common electrode ET2 includes a semi-transmissive conductive material or is made of a semi-transmissive conductive material, an improvement in luminous efficiency due to the microcavity effect may be expected.

[0128] In an embodiment, the common electrode ET2 may be a common film that is at least completely formed in the display area DA and shared by the light-emitting elements EL of the pixels PX. In an embodiment, for example, the common electrode ET2 may be completely formed on the light-emitting layer EML located in the emission area EA and the dummy light-emitting layer EMLd located in the non-emission area NEA. In an embodiment, the common electrode ET2 may be formed to extend to at least a portion of the non-display area NA, and the contact portion CNT may be formed in the region in which the common electrode ET2 is disposed.

[0129] In an embodiment, by adjusting the shape, structure, thickness, height, etc. of the insulating layer INS, it is possible to control whether the pixel electrode ET1, the light-emitting layer EML, and / or the common electrode ET2 provided in the emission area EA are separated from each other (for example, whether they are patterned). In an embodiment, for example, by adjusting the thickness TH (or height) of the lower insulating layer INS1 and the length L of the end of the upper insulating layer INS2 protruding from the lower insulating layer INS1, it is possible to control whether the pixel electrode ET1, the light-emitting layer EML, and / or the common electrode ET2 are separated from each other and / or patterned.

[0130] The encapsulation layer 140 may be disposed on the light emitting element layer 130 in the display area DA and the non-display area NA around the display area DA. The encapsulation layer 140 may block oxygen or moisture from penetrating into the light emitting element layer 130 and mitigate electrical or physical effects on the circuit layer 120 and the light emitting element layer 130.

[0131] In an embodiment, encapsulation layer 140 may include first encapsulation layer 141, second encapsulation layer 142, and third encapsulation layer 143 sequentially disposed on light emitting element layer 130. First encapsulation layer 141 and third encapsulation layer 143 may include an inorganic insulating material, and second encapsulation layer 142 may include an organic insulating material.

[0132] Figure 6 is a cross-sectional view illustrating a display device 100 according to an embodiment. For example, Figure 6 Schematically illustrates the Figure 4 1 , and illustrates an embodiment of a cross section of the display device 100 taken along line X1-X1', and illustrating a portion of the non-display area NA in which the first electrode AXE1 and the contact portion CNT are disposed. Figure 5 Embodiments of different embodiments.

[0133] remove Figures 1 to 5 In addition, reference Figure 6 In an embodiment, the first electrode AXE1 and the contact portion CNT may be located in a portion of the non-display area NA where the dummy light emitting layer EMLd and the common electrode ET2 are not provided and only the conductive pattern CDP is provided. In an embodiment, for example, the dummy light emitting layer EMLd and the common electrode ET2 may be provided only in the display area DA, or only in the display area DA and a portion of the non-display area NA around the display area DA. The first electrode AXE1 and the contact portion CNT may be located in another portion of the non-display area NA where the dummy light emitting layer EMLd and the common electrode ET2 are not provided (for example, an edge region of the non-display area NA). The position and number of the first electrode AXE1 and the contact portion CNT, etc. may be variously changed depending on the embodiment.

[0134] Figure 7 is a cross-sectional view illustrating a display device 100 according to an embodiment. For example, Figure 7 Schematically illustrates the Figure 4 The embodiment of the cross section of the display device 100 is taken along the line X1-X1', and illustrates the light emitting layer EML and Figure 5 Embodiments of different embodiments.

[0135] remove Figures 1 to 6 In addition, reference Figure 7 In an embodiment, the thickness of the lower insulating layer INS1 may be less than or equal to the sum of the thicknesses of each pixel electrode ET1 and the light emitting layer EML, and the height of the light emitting layer EML may be greater than or equal to the height of the lower insulating layer INS1. The light emitting layer EML may be a common film shared by the light emitting elements EL of the pixels PX. In an embodiment, for example, the light emitting layer EML of the pixel PX may be formed as a common film covering the conductive pattern CDP and may be completely disposed in the display area DA including the emission area EA and the non-emission area NEA, etc. Even if the light emitting layer EML is completely formed in the display area DA, since the first voltage is applied to the conductive pattern CDP in the non-emission area NEA, the leakage current may be blocked or prevented.

[0136] In an embodiment, the light-emitting layer EML may be a light-emitting layer having a series structure including at least two light-emitting layers sequentially stacked between the pixel electrode ET1 and the common electrode ET2 and at least one charge generation layer disposed between the light-emitting layers (e.g., a light-emitting stack including a plurality of light-emitting layers, an intermediate layer, and at least one charge generation layer). In another embodiment, the light-emitting layer EML may be a single-layer light-emitting layer or a light-emitting stack including a plurality of light-emitting layers but not including a charge generation layer. In addition, the type and structure of the light-emitting layer EML may be variously changed depending on the embodiment.

[0137] In an embodiment, the light emitting layer EML may generate light of the same color (e.g., white light or blue light) in the emission area EA of the pixel PX. In addition, respective color filters and / or wavelength conversion patterns corresponding to the colors of light to be emitted from the respective pixels PX may be disposed on the light emitting element EL of the pixel PX.

[0138] Figure 8 The diagram shows the display device 100. Figure 1 A schematic plan view of a portion corresponding to area A1. For example, Figure 8 The diagram shows the contact between CNT and Figure 4 Embodiments of different embodiments.

[0139] Fig. 9 is a cross-sectional view illustrating a display device 100 according to an embodiment. Fig.10is a cross-sectional view illustrating a display device 100 according to an embodiment. For example, Fig. 9 and Fig.10 The diagram shows the Figure 8 1 and 2 ′, and illustrate different embodiments of a cross section of the display device 100 taken along line X2-X2′. Figure 5 Examples and Figure 7 Embodiments of different modifications.

[0140] remove Figures 1 to 7 In addition, reference Figures 8 to 10 , an embodiment of the display device 100 may further include at least one contact portion CNT located in the display area DA. In an embodiment, for example, the display device 100 may include at least one first contact portion CNT1 located in the non-display area NA and at least one second contact portion CNT2 located in the non-emission area NEA of the display area DA. In addition, the display device 100 may further include at least one second electrode AXE2 (also referred to as a "second auxiliary electrode") located in the non-emission area NEA so as to correspond to each second contact portion CNT2.

[0141] In an embodiment, the second electrode AXE2 may be provided at the same conductive layer as the first electrode AXE1 and may be formed simultaneously with the first electrode AXE1. In an embodiment, for example, the second electrode AXE2 may be provided at the fourth conductive layer CDL4 including the connection electrode CNE and the first electrode AXE1.

[0142] In an embodiment, the first electrode AXE1 and the second electrode AXE2 may be supplied with the same first voltage. In an embodiment, for example, the first electrode AXE1 and the second electrode AXE2 may be connected to a power line PL (e.g., a second power line VSL) to which the first voltage is applied, or may be a part of the power line PL. Accordingly, the first voltage may be applied to the conductive pattern CDP through the first electrode AXE1 and the second electrode AXE2. The first voltage may be applied to the conductive pattern CDP more stably through the first electrode AXE1 and the second electrode AXE2, and accordingly, the leakage current may be more effectively blocked, prevented, or reduced.

[0143] In each second contact portion CNT2, the second electrode AXE2 may be connected to the conductive pattern CDP through a third contact hole CH3 defined by passing through an insulating layer INS disposed on the second electrode AXE2. In an embodiment, for example, in each second contact portion CNT2, the conductive pattern CDP is disposed on the second electrode AXE2 exposed by the third contact hole CH3, so that the second electrode AXE2 and the conductive pattern CDP may be electrically connected to each other.

[0144] In addition, the position, number or distribution density of the contact portion CNT and the auxiliary electrode (e.g., the first electrode AXE1 and / or the second electrode AXE2) connected to the contact portion CNT may be variously changed depending on the embodiment. For example, in another embodiment, the contact portion CNT and the auxiliary electrode may not be provided in the non-display area NA and may be provided only in the display area DA.

[0145] In an embodiment, the insulating layer INS may have a relatively expanded width in the region where the second contact portion CNT2 is located so as to appropriately surround the second contact portion CNT2. In addition, the emission area EA defined by the insulating layer INS may have a shape corresponding to the shape of the insulating layer INS. In an embodiment, for example, the emission area EA may have a relatively reduced width around the second contact portion CNT2. The pixel electrode ET1 may have a shape and / or area corresponding to the shape and / or area of ​​each emission area EA.

[0146] Figures 11 to 19 is a cross-sectional view illustrating a method for manufacturing the display device 100 according to the embodiment. For example, Figures 11 to 19 The sequence diagram shows the process for manufacturing the Figure 5 A method for displaying the device 100 of an embodiment.

[0147] remove Figures 1 to 10 In addition, reference Fig.11 and Fig.12 In an embodiment of a method for manufacturing the display device 100 , a substrate 110 including a display area DA and a non-display area NA may be prepared. In addition, a circuit layer 120 may be formed on the substrate 110 .

[0148] For example, Fig.11 As shown in FIG. 1 , a buffer layer 121, circuit elements of the pixel circuit PXC including the transistor Tpx, first to fourth insulating layers 122, 123, 124 and 125, a connection electrode CNE connected to the transistor Tpx, and a first electrode AXE1 connected to the power line PL, etc. may be formed on the substrate 110. Figures 8 to 10 In the case of the embodiment of the display device 100 further including the second electrode AXE2 shown in FIG, the second electrode AXE2 may be further formed in the circuit layer 120. In the embodiment, for example, in the process of forming the circuit element including the transistor Tpx and / or the connection electrode CNE on the substrate 110, an auxiliary electrode including the first electrode AXE1 and / or the second electrode AXE2 may be formed. In addition, in the process of forming the circuit element, the connection electrode CNE, the first electrode AXE1 and / or the second electrode AXE2, a line provided in the display panel together with the pixel PX may be formed.

[0149] In each pixel region (for example, including Figure 4 and Figure 5 In the embodiment having a structure in which one electrode of each of the transistors Tpx is directly connected to the light emitting element EL of the corresponding pixel PX, the connection electrode CNE may not be formed.

[0150] The auxiliary electrode (e.g., the first electrode AXE1 and / or the second electrode AXE2) may be provided at at least one of the conductive layers of the circuit layer 120 including the transistor Tpx, the line and / or the connection electrode CNE, and may be formed simultaneously with the electrode, line and / or bridge pattern provided at the at least one conductive layer. The first electrode AXE1 may be formed in the non-display area NA. The second electrode AXE2 may be formed in the non-emission area NEA of the display area DA.

[0151] Afterwards, if Fig.12 As shown in , the fifth insulating layer 126 may be formed on the substrate 110 on which the auxiliary electrode including the first electrode AXE1, the transistor Tpx, the connection electrode CNE, etc. are formed. In an embodiment, for example, the fifth insulating layer 126 having the first contact hole CH1 and the second contact hole CH2 may be formed by applying an inorganic insulating material to the substrate 110 on which the first electrode AXE1, the transistor Tpx, the connection electrode CNE, etc. are formed to form an inorganic insulating layer, and etching the inorganic insulating layer so that a portion of the first electrode AXE1 and a portion of each of the connection electrodes CNE are exposed.

[0152] remove Figures 1 to 12 In addition, reference Figures 13 to 16 , an insulating layer INS including a lower insulating layer INS1 and an upper insulating layer INS2 may be formed on the substrate 110 on which the auxiliary electrode including the first electrode AXE1 , the transistor Tpx, the connection electrode CNE, the fifth insulating layer 126 , and the like are formed.

[0153] For example, Fig.13 As shown in , the lower insulating layer INS1 may be formed by applying an organic insulating material to the substrate 110 on which the auxiliary electrode including the first electrode AXE1, the transistor Tpx, the connection electrode CNE, the fifth insulating layer 126, etc. are formed. In addition, the lower insulating layer INS1 may be etched so that a portion of the first electrode AXE1 is exposed in a region corresponding to the contact portion CNT. In the case of manufacturing an embodiment of the display device 100 including the second electrode AXE2, the lower insulating layer INS1 may be etched on the second electrode AXE2 so that a portion of the second electrode AXE2 is exposed.

[0154] Afterwards, if Fig.14 As shown in FIG. 1 , the upper insulating layer INS2 may be completely formed by applying an inorganic insulating material to the substrate 110 on which the lower insulating layer INS1 and the like are formed.

[0155] Afterwards, if Fig.15 As shown in , the upper insulating layer INS2 may be etched so that a portion of the first electrode AXE1 is exposed in a region corresponding to the contact portion CNT of the non-display area NA, and the lower insulating layer INS1 is exposed in the emission area EA. Accordingly, the upper insulating layer INS2 may be patterned to match a region in which the insulating layer INS is to be formed. In an embodiment, the upper insulating layer INS2 may prevent an opening of the lower insulating layer INS1 located on the first electrode AXE1 from being additionally etched in a subsequent process by covering a side surface of the lower insulating layer INS1 in a region corresponding to the contact portion CNT. In the case of manufacturing an embodiment of the display device 100 including the second electrode AXE2, the upper insulating layer INS2 may be etched on the second electrode AXE2 so that a portion of the second electrode AXE2 is exposed.

[0156] Afterwards, if Fig.16 As shown in , the lower insulating layer INS1 may be patterned by etching the lower insulating layer INS1 using the upper insulating layer INS2 as a mask. In an embodiment, for example, the lower insulating layer INS1 may be patterned to include an opening corresponding to the emission area EA. Accordingly, the insulating layer INS may be formed in the non-display area NA and the non-emission area NEA of the display area DA. The insulating layer INS may be opened (or removed) in the area corresponding to the contact portion CNT to expose a portion of the first electrode AXE1, and may be opened in the area corresponding to the emission area EA to expose the second contact hole CH2.

[0157] In an embodiment, the lower insulating layer INS1 may be etched by an isotropic dry etching process using the upper insulating layer INS2 as a mask. In the process of etching the lower insulating layer INS1, the lower insulating layer INS1 may be etched in a form in which its upper surface has an area smaller than that of the lower surface of the upper insulating layer INS2. Accordingly, in a subsequent process of forming the pixel electrode ET1 and the conductive pattern CDP, the pixel electrode ET1 and the conductive pattern CDP may be formed to be stably separated from each other while applying a conductive material.

[0158] remove Figures 1 to 16 In addition, reference Fig.17, the pixel electrode ET1 and the conductive pattern CDP may be formed on a substrate 110 on which at least a double insulating layer INS including a lower insulating layer INS1 and an upper insulating layer INS2 is formed. In an embodiment, for example, by completely applying a conductive material to the substrate 110 on which the insulating layer INS is formed, each pixel electrode ET1 may be formed in the emission area EA, and the conductive pattern CDP may be formed on a portion of the exposed first electrode AXE1 (or the exposed first electrode AXE1 and the second electrode AXE2) and the upper insulating layer INS2. Due to the insulating layer INS, the pixel electrode ET1 and the conductive pattern CDP may be formed to be separated (or disconnected) from each other in the process of applying the conductive material without performing a separate etching and / or patterning process. For example, by completely applying a conductive material to the substrate 110 on which the insulating layer INS is formed at a height smaller than that of the lower insulating layer INS1, the pixel electrode ET1 and the conductive pattern CDP may be formed to be separated from each other.

[0159] In the embodiment, due to the shape of the insulating layer INS, the edge of each of the pixel electrodes ET1 adjacent to the insulating layer INS may be formed as an inclined surface whose thickness and height gradually decrease. Accordingly, even if an additional insulating pattern (e.g., a pixel defining layer) is not formed in the non-emission area NEA, dielectric breakdown may be prevented from occurring between the pixel electrode ET1 and the common electrode ET2 to be formed in a subsequent process.

[0160] The pixel electrode ET1 may be electrically connected to the corresponding connection electrode CNE and / or the transistor Tpx through the corresponding second contact hole CH2. The conductive pattern CDP may be connected to the first electrode AXE1 through the first contact hole CH1. In an embodiment, for example, a portion of the conductive pattern CDP may contact the exposed first electrode AXE1 in the contact portion CNT. When manufacturing the display device 100 including the second electrode AXE2, a portion of the conductive pattern CDP may be connected to the exposed second electrode AXE2.

[0161] remove Figures 1 to 17 In addition, reference Fig.18 , a light emitting layer EML may be formed on the substrate 110 on which the pixel electrode ET1 and the conductive pattern CDP are formed. In an embodiment, when the light emitting layer EML is configured as a plurality of layers including at least one sub-light emitting layer and / or an intermediate layer, materials for forming the respective layers of the light emitting layer EML may be sequentially deposited.

[0162] In an embodiment, in a process of forming the light emitting layer EML, the respective light emitting layers EML may be formed in the emission area EA so as to be separated from each other through the insulating layer INS. In an embodiment, for example, by applying a material for forming the light emitting layer EML at a height smaller than that of the lower insulating layer INS1, the respective light emitting layers EML may be formed in the emission area EA so as to be separated from each other. In this case, a dummy light emitting layer EMLd separated from the light emitting layer EML of the pixel PX may be formed on the conductive pattern CDP. In another embodiment, by applying a material for forming the light emitting layer EML at a height greater than or equal to that of the lower insulating layer INS1, the light emitting layer EML may be completely and / or continuously formed at least in the display area DA.

[0163] remove Figures 1 to 18 In addition, reference Fig.19 , the common electrode ET2 may be formed on the substrate 110 on which the light emitting layer EML is formed. For example, by applying a conductive material for forming the common electrode ET2 at a height greater than or equal to that of the lower insulating layer INS1, the common electrode ET2 may be completely and / or continuously formed at least in the display area DA. Therefore, the light emitting element layer 130 may be formed.

[0164] Thereafter, a Figure 5 The encapsulation layer 140 shown in the figure may be used, or a separate upper substrate or the like may be used to encapsulate the light emitting element layer 130. In addition, if necessary, a process of forming or disposing a color filter and / or a wavelength conversion pattern on the light emitting element layer 130 or the encapsulation layer 140 may be additionally performed.

[0165] As described above, the display device 100 according to the embodiment includes an insulating layer INS located in the non-emission area NEA between the non-display area NA and the emission area EA of the pixel PX. The insulating layer INS may have at least a double-layer structure including a lower insulating layer INS1 located between the pixel electrodes ET1 disposed in each emission area EA and an upper insulating layer INS2 disposed on the lower insulating layer INS1.

[0166] In addition, the display device 100 according to the embodiment includes a conductive pattern CDP disposed on the insulating layer INS so as to be separated from the pixel electrode ET1. A first voltage having a voltage level capable of blocking, preventing or reducing leakage current flowing between pixels PX may be applied to the conductive pattern CDP.

[0167] In the display device 100 according to the embodiment and the method for manufacturing the display device 100, the pixel electrodes ET1 may be formed by the insulating layer INS so as to be automatically (or naturally) and / or immediately separated from each other. In such an embodiment, a conductive pattern CDP may be formed on the insulating layer INS while the pixel electrode ET1 is formed so as to be separated from each other by the insulating layer INS. Accordingly, the manufacturing process of the display device 100 may be simplified and facilitated, and the distance between the emission areas EA of the pixels PX may be reduced or minimized if necessary.

[0168] In addition, in the display device 100 and the method for manufacturing the display device 100 according to the embodiment, the emission area EA can be defined by the insulating layer INS without providing a separate pixel defining layer on the pixel electrode ET1. Accordingly, the structure and manufacturing process of the display device 100 can be simplified, and the degree of freedom in the design of the display device 100 can be improved.

[0169] In addition, in the display device 100 according to the embodiment and the method for manufacturing the display device 100, the leakage current can be blocked, prevented or reduced between the pixels PX by the non-emission area NEA. For example, the leakage current between the pixels PX can be blocked, prevented or reduced by the insulating layer INS. In addition, the leakage current between the pixels PX can be more effectively blocked, prevented or reduced by applying the first voltage to the conductive pattern CDP. For example, even in a high-resolution display device 100 in which the size of the pixel PX and the distance between the pixels PX are significantly smaller or significantly reduced compared to a display device with a relatively low resolution, the leakage current between the pixels PX can be effectively blocked, prevented or reduced. The conductive pattern CDP can be formed simultaneously with the pixel electrode ET1, and can effectively block, prevent or reduce the leakage current without adding a process for forming a separate electrode or line for blocking the leakage current. Accordingly, the structure and manufacturing process of the display device 100 can be simplified.

[0170] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0171] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, comprising: a substrate, a display area and a non-display area being defined on the substrate; Pixels are arranged on the substrate, wherein the pixels include pixel electrodes respectively arranged in emission areas located in the display area, light-emitting layers respectively arranged on the pixel electrodes, and a common electrode arranged on the light-emitting layers; an insulating layer disposed on the substrate and located in the non-display region and in a non-emission region between the emission regions of the pixels; and a conductive pattern disposed on the insulating layer to be separated from the pixel electrode of the pixel, wherein a first voltage is applied to the conductive pattern, Wherein, the insulating layer comprises: a lower insulating layer, located in the display area and between the pixel electrodes; and The upper insulating layer is disposed on the lower insulating layer and has an area larger than that of an upper surface of the lower insulating layer.

2. The display device according to claim 1, wherein: The conductive pattern and the pixel electrode include the same conductive material.

3. The display device according to claim 1, wherein: The first voltage is a cut-off voltage of a light emitting element including the pixel electrode, the light emitting layer, and the common electrode.

4. The display device according to claim 1, further comprising: A first electrode, located in the non-display area, is disposed between the substrate and the insulating layer and is connected to the conductive pattern through a contact hole defined through the insulating layer.

5. The display device according to claim 1, further comprising: A second electrode, located in the non-emitting region, is disposed between the substrate and the insulating layer and is connected to the conductive pattern through a contact hole defined through the insulating layer.

6. The display device according to claim 1, wherein: The upper insulating layer completely covers the upper surface of the lower insulating layer and protrudes toward an adjacent pixel among the pixels more than the lower insulating layer.

7. The display device according to claim 1, wherein: The lower insulating layer includes an organic insulating material, and The upper insulating layer includes an inorganic insulating material.

8. The display device according to claim 1, wherein: The thickness of the lower insulating layer is greater than the thickness of the pixel electrode.

9. The display device according to claim 8, wherein: The thickness of the lower insulating layer is less than or equal to the sum of the thicknesses of the pixel electrode, the light emitting layer, and the common electrode.

10. The display device according to claim 9, wherein: The common electrode of the pixel is a common film covering the conductive pattern, and is completely disposed in the display area including the emission area and the non-emission area.

11. The display device according to claim 8, wherein: The thickness of the lower insulating layer is greater than the sum of the thicknesses of the pixel electrode and the light emitting layer.

12. The display device according to claim 11, wherein: The light emitting layers of the pixels are separated from each other, the lower insulating layer is interposed between the light emitting layers of the pixels, and The display device further includes a dummy light emitting layer disposed in the non-emitting region, on the conductive pattern, and separated from the light emitting layer of the pixel.

13. The display device according to claim 8, wherein: The thickness of the lower insulating layer is less than or equal to the sum of the thicknesses of the pixel electrode and the light emitting layer.

14. The display device according to claim 13, wherein: The light emitting layer of the pixel is a common film covering the conductive pattern, and is entirely disposed in the display region including the emission region and the non-emission region.

15. The display device according to any one of claims 1 to 14, wherein: When viewed in a thickness direction of the substrate, the conductive pattern has a mesh shape provided with openings corresponding to the emission regions of the pixels.

16. A method for manufacturing a display device, the method comprising: forming a transistor and a connection electrode on a substrate in a display region, and forming an auxiliary electrode on the substrate in a non-display region, wherein the display region and the non-display region located around the display region are defined on the substrate, and the connection electrode is connected to the transistor; forming a lower insulating layer by applying an organic insulating material to the substrate on which the connection electrode and the auxiliary electrode are formed, and etching the lower insulating layer in such a manner that a portion of the auxiliary electrode is exposed; forming an upper insulating layer by applying an inorganic insulating material to the substrate on which the lower insulating layer is formed, and etching the upper insulating layer in such a manner that the portion of the auxiliary electrode in the non-display area is exposed and portions of the lower insulating layer in emission areas respectively located in the display area are exposed; etching the lower insulating layer using the upper insulating layer as a mask to pattern the lower insulating layer so as to be provided with openings corresponding to the portion of the auxiliary electrode and the emission region, respectively; forming pixel electrodes in the emission regions respectively by applying a conductive material to the substrate on which the patterned lower insulating layer and the upper insulating layer are formed, and forming a conductive pattern separated from the pixel electrode on the exposed portion of the auxiliary electrode and the upper insulating layer; forming a light emitting layer on the substrate on which the pixel electrode and the conductive pattern are formed; and A common electrode is formed on the substrate on which the light emitting layer is formed.

17. The method for manufacturing a display device according to claim 16, wherein: In etching the lower insulating layer using the upper insulating layer as the mask, the lower insulating layer is etched in such a manner that an upper surface of the lower insulating layer has an area smaller than an area of ​​a lower surface of the upper insulating layer.

18. The method for manufacturing a display device according to claim 16, wherein: In the forming of the pixel electrode and the forming of the conductive pattern, the pixel electrode and the conductive pattern are separated from each other by completely applying the conductive material at a height smaller than a height of the lower insulating layer.

19. The method for manufacturing a display device according to claim 16, wherein: In the forming of the common electrode, the common electrode is completely formed in the display area by applying a conductive material for forming the common electrode at a height greater than or equal to a height of the lower insulating layer.

20. The method for manufacturing a display device according to claim 19, further comprising: Prior to the formation of the lower insulating layer, an inorganic insulating layer is formed by applying an inorganic insulating material to the substrate on which the connecting electrode and the auxiliary electrode are formed, and etching the inorganic insulating layer in such a manner that a portion of the auxiliary electrode and a portion of each of the connecting electrodes are exposed.

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