Switching regulator

Abstract

A switching regulator includes: a comparator that compares a switching voltage corresponding to an inductive current flowing from the switching regulator to an inductor with a predetermined reference voltage and outputs a comparison result signal; a monitoring circuit that generates a current for generating a monitoring voltage that monitors the switching voltage; a reference voltage circuit generating a current for generating the reference voltage; and a control circuit that outputs a plurality of selection signals indicating a plurality of different timings to at least one of the monitoring circuit and the reference voltage circuit. At least one of the monitoring circuit and the reference voltage circuit changes the generated current according to the plurality of timings, and at least one of the monitoring circuit and the reference voltage circuit is common to the plurality of timings.

Description

Technical Field

[0001] The present invention relates to a switching regulator. Background Art

[0002] In a conventional switching regulator, it is known that in order to reduce the mounting area, the integrated circuit (IC) is required to be miniaturized.

[0003] For example, in Patent Document 1, a switching regulator according to a prior art example is invented in order to operate with low power consumption and reduce the occupied area in a semiconductor device, with respect to multiple abnormality detection functions of a switching regulator. The switching regulator includes a comparison circuit, multiple switch circuits, and a switch control circuit, and the switching regulator is characterized in that the multiple switch circuits are switched by multiple control signals of the switch control circuit, and multiple abnormality detection functions are realized by one comparison circuit.

[0004] That is, Patent Document 1 discloses a technique of using one comparator circuit for switching reference voltages and monitor voltages of a plurality of detection circuits having different operation timings in order to reduce chip area.

[0005] Prior art literature

[0006] Patent Document 1: Japanese Patent No. 6656956 Summary of the invention

[0007] Problems to be solved by the invention

[0008] However, in the switching regulator of the analog circuit so far, in order to maintain highly stable quality, it is necessary to correct the circuit of the manufacturing variation of the electrical characteristics and specific accuracy, and there is a problem that the circuit area is difficult to reduce. In particular, in the invention involved in Patent Document 1, it is impossible to eliminate the problem that the circuit needs to correct the manufacturing variation for each application.

[0009] An object of the present invention is to solve the above problems and provide a switching regulator capable of maintaining highly stable quality in the switching regulator while reducing the circuit area compared with the conventional technology.

[0010] Means for solving problems

[0011] A switching regulator according to one aspect of the present invention is a switching regulator including a pair of switching elements connected in series with each other, and includes:

[0012] a comparator for comparing a switching voltage corresponding to an inductor current flowing from the switching regulator to the inductor with a predetermined reference voltage and outputting a comparison result signal;

[0013] a monitoring circuit generating a current for generating a monitoring voltage for monitoring the switch voltage;

[0014] a reference voltage circuit that generates a current for generating the reference voltage; and

[0015] a control circuit that outputs a plurality of selection signals indicating a plurality of mutually different timings to at least one of the monitoring circuit and the reference voltage circuit,

[0016] At least one of the monitoring circuit and the reference voltage circuit changes the generated current according to the plurality of timings,

[0017] At least one of the monitoring circuit and the reference voltage circuit is commonly used for the plurality of timings.

[0018] Effects of the Invention

[0019] Therefore, according to the switching regulator according to one aspect of the present invention, it is possible to reduce the circuit area compared to the conventional technology while maintaining highly (highly) stable quality in the switching regulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 1 is a block diagram showing a configuration of a switching regulator 1 according to a basic circuit.

[0021] Figure 2 Yes means Figure 1 A block diagram of the structure of the zero cross detector 11 is shown.

[0022] Figure 3 Yes means Figure 1 A timing chart of each signal of an operation example of the switching regulator 1 is shown.

[0023] Figure 4 : is a block diagram showing the structure of the current monitoring circuit 11A according to the first modification.

[0024] Figure 5 Yes means including Figure 4 FIG. 1 is a timing chart of each signal of an operation example of a switching regulator of the current monitoring circuit 11A.

[0025] Figure 6 : is a block diagram showing the structure of the current monitoring circuit 11B according to the second modification.

[0026] Figure 7 Yes means including Figure 6 11B is a timing diagram of each signal of an operation example of a switching regulator of the current monitoring circuit 11B.

[0027] Figure 8 : is a block diagram showing the configuration of a current monitoring circuit 11C according to Modification 3.

[0028] Fig. 9 Yes means including Figure 8 FIG. 1 is a timing diagram of each signal of an operation example of a switching regulator of the current monitoring circuit 11C.

[0029] Fig.10 : is a block diagram showing the structure of a current monitoring circuit 11D according to Modification 4.

[0030] Fig.11 Yes means including Fig.10 11D is a timing diagram of each signal of an operation example of a switching regulator of the current monitoring circuit 11D.

[0031] Fig.12 : is a block diagram showing the structure of a current monitoring circuit 11E according to a comparative example.

[0032] Fig.13 Yes means Fig.12 11E is a block diagram of a portion of the structure of the current monitoring circuit 11E.

[0033] Fig.14 Yes means including Fig.13 11E is a timing diagram of each signal of an operation example of a switching regulator of the current monitoring circuit 11E.

[0034] Fig.15 Yes means Fig.12 11E is a block diagram of a portion of the structure of the current monitoring circuit 11E.

[0035] Fig.16 Yes means including Fig.15 11E is a timing diagram of each signal of an operation example of a switching regulator of the current monitoring circuit 11E.

[0036] Fig.17 11F is a block diagram showing a configuration example of a switching regulator including the current monitoring circuit 11F according to the first embodiment.

[0037] Fig.18 11 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11G according to the second embodiment.

[0038] Fig.19 1 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11H according to the third embodiment.

[0039] Fig. 20 11I is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11I according to the fourth embodiment.

[0040] Fig.21 11 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11J according to the fifth embodiment.

[0041] Fig. 22 1 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11K according to the sixth embodiment.

[0042] Fig.23 1 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11L according to the seventh embodiment.

[0043] Fig.24 11 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11M according to the eighth embodiment. DETAILED DESCRIPTION

[0044] Hereinafter, embodiments and modifications of the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or similar components.

[0045] (Opinion of the inventor)

[0046] First, in order to explain the subject of the present invention, a basic circuit will be described below.

[0047] (Basic Circuit)

[0048] Figure 1 1 is a block diagram showing the structure of a switching regulator 1 involved in a basic circuit. Figure 1 In the embodiment, the switching regulator 1 is configured to include a switching modulation circuit 10, an inverter INV1, an OR gate NOR1, a zero-crossing detector 11, MOS transistors Q1 and Q2 as a pair of switching elements, and terminals T1 to T4.

[0049] exist Figure 1In the embodiment, the switching modulation circuit 10 generates a PWM signal, for example, for switching the MOS transistors Q1 and Q2 constituting the inverter circuit, based on the output voltage Vout fed back to the terminal T4, and outputs the PWM signal to the gate of the MOS transistor Q1 via the inverter INV1 and to the gate of the MOS transistor Q2 via the NOR gate NOR1, thereby switching the MOS transistors Q1 and Q2 so that the output voltage Vout becomes a predetermined value. The power supply voltage Vdd is grounded via the terminal T1, the source and drain of the MOS transistor Q1, the drain and source of the MOS transistor Q2, and the terminal T2. The output voltage from each drain of the MOS transistors Q1 and Q2 is output as the output voltage Vout to the output capacitor Cout via the terminal T3, the current detector 12, and the inductor Ind. Here, the output voltage Vout is fed back to the terminal T4.

[0050] A current signal corresponding to the inductor current Iind detected by the current detector 12 is input to the zero-crossing detector 11. The zero-crossing detector 11 generates a high (H) level zero-crossing detection signal ZCDET and outputs it to the NOR gate NOR1 every time the zero-crossing occurs.

[0051] As above, Figure 1 The basic circuit of FIG. 1 is a diagram for explaining the basic operation of monitoring the inductor current Iind, and is characterized in that, in particular, the zero-crossing detector 11 detects when the inductor current becomes zero during rectification and controls the switching operation. Specifically, in Figure 1 In response to the high (H) level zero-crossing detection signal ZCDET, the switching action is stopped to prevent the reverse flow of current.

[0052] Next, modifications of the basic circuit will be described below.

[0053] (Variant 1)

[0054] Figure 2 Yes means Figure 1 A block diagram of the structure of the zero-crossing detector 11, Figure 3 Yes means Figure 1 The timing diagram of each signal of the operation example of the switching regulator 1 is shown in FIG. Figure 2 In FIG. 1 , the zero-crossing detector 11 is configured to include a “current monitoring circuit” including a comparator 13 .

[0055] exist Figure 2In the embodiment, the switching voltage Vsw at the connection point between the drain of MOS transistor Q1 and the drain of MOS transistor Q2 is applied to the non-inverting input terminal of comparator 13, and the ground voltage at the source of MOS transistor Q2 is applied to the inverting input terminal of comparator 13. Comparator 13 outputs the comparison result signal as zero crossing detection signal ZCDET.

[0056] The zero-crossing detector 11 constructed as described above can detect "0 A" by comparing the voltages across the MOS transistor Q2 when the inductor current Iind becomes "0 A", because the drain-source voltage Vds of the MOS transistor Q2 becomes 0 V. However, if Figure 3 As shown, there is a problem that a reverse current Iind is generated due to the delay time tdelay.

[0057] Therefore, a current monitoring circuit 11A (included in the zero-crossing detector 11 ) according to the following modification 1 is proposed.

[0058] (Variant 1)

[0059] Figure 4 1 is a block diagram showing the structure of a current monitoring circuit 11A according to Modification 1. Figure 5 Yes means including Figure 4 FIG. 1 is a timing chart of each signal of an operation example of a switching regulator of the current monitoring circuit 11A. Figure 4 The current monitoring circuit 11A and Figure 2 Compared with the current monitoring circuit 11, the following points are different.

[0060] (1) A constant current source IS1 is inserted between the power supply voltage Vdd and the non-inverting input terminal of the comparator 13 .

[0061] (2) The MOS transistor Q3 having the power supply voltage Vdd applied to the gate is inserted between the non-inverting input terminal of the comparator 13 and the drain of the MOS transistor Q2.

[0062] According to the switching regulator including the current monitoring circuit 11A configured as described above, Figure 5 As shown, by comparing the voltage Vmoni obtained by shifting the switching voltage Vsw by a predetermined voltage with the ground voltage, it is possible to detect the switching voltage Vsw earlier by the delay time.

[0063] The detection voltage of the comparator 13 is expressed by the following equation.

[0064] 0V<0V-Vdsdrv+Vdsmoni

[0065] Here, Vdsdrv is the voltage across the MOS transistor Q2, and Vdsmoni is the voltage across the MOS transistor Q3. The inductor current Iind, which is a DC detection current, is expressed by the following equation.

[0066] Iind = (on-resistance of Q3) × (bias current based on IS1) ÷ (on-resistance of Q2)

[0067] Furthermore, the AC detection current taking the delay time tdelay into consideration is expressed by the following equation.

[0068] AC detection current = DC detection current - Vout × tDelay ÷ Ind

[0069] Vdsdrv = (on-resistance of Q2) × (current Iind of Q2)

[0070] Vdsmoni = (on-resistance of Q3) × (bias current based on IS1)

[0071] Next, a current monitoring circuit other than detecting zero current will be described below.

[0072] (Variant 2)

[0073] Figure 6 is a block diagram showing the structure of a current monitoring circuit 11B according to Modification 2. Figure 7 Yes means including Figure 6 11B is a timing diagram of each signal of an operation example of a switching regulator of the current monitoring circuit 11B. Figure 6 The current monitoring circuit 11B and Figure 4 Compared with the current monitoring circuit 11A, the following points are different.

[0074] (1) A constant current source IS12 is provided instead of the constant current source IS1, thereby making the voltage Vdsmoni greater than Figure 4 During zero detection, the comparator 13 detects a current value greater than "0A".

[0075] (2) The comparator 13 outputs a voltage VCDET of a comparison result signal.

[0076] (Variant 3)

[0077] Figure 8 is a block diagram showing the structure of a current monitoring circuit 11C according to Modification 3. Fig. 9 Yes means including Figure 8 FIG. 1 is a timing diagram of each signal of an operation example of a switching regulator of the current monitoring circuit 11C. Figure 8 The current monitoring circuit 11C and Figure 6 Compared with the current monitoring circuit 11B, the following points are different.

[0078] (1) A constant current source IS2 is provided instead of the constant current source IS1A. Here, the power supply voltage Vdd is connected to the inverting input terminal of the comparator 13 via the constant current source IS2.

[0079] (2) The switching voltage Vsw is applied to the non-inverting input terminal of the comparator 13 .

[0080] (3) The MOS transistor Q4 having the power supply voltage Vdd applied to the gate is inserted between the inverting input terminal (reference voltage Vref) of the comparator 13 and the ground voltage.

[0081] In the current monitoring circuit 11C configured as described above, the comparator 13 is characterized in that it detects a current flowing in reverse by an amount equal to the voltage Vdsref.

[0082] (Variant 4)

[0083] Fig.10 is a block diagram showing the structure of a current monitoring circuit 11D according to Modification 4. Fig.11 Yes means including Fig.10 11D is a timing diagram of each signal of an operation example of a switching regulator of the current monitoring circuit 11D.

[0084] exist Fig.10 In the current monitoring circuit 11D, three constant current sources IS1, IS2, IS12, MOS transistors Q3 to Q5, switches SW1 to SW6, and a comparator 13 are configured. Here, switches SW1 and SW2 are turned on or off based on a selection signal RCSEL, switches SW3 and SW4 are turned on or off based on a selection signal VCSEL, and switches SW5 and SW6 are turned on or off based on a selection signal ZCSEL. Any switch is turned on. The comparator 13 outputs a voltage LSCDET of a comparison result signal.

[0085] The current monitoring circuit 11D configured as described above is an example of a circuit in which three types of inductor currents are detected by one comparator 13 .

[0086] (Comparative Example)

[0087] Fig.12 JP-A-2004-11776 is a block diagram showing a configuration of a current monitoring circuit 11E according to a comparative example disclosed in Patent Document 1.

[0088] exist Fig.12In the current monitoring circuit 11E, three variable constant current sources VIS1 to VIS3, MOS transistors Q3 to Q5, switches SW1 to SW6, and a comparator 13 are configured. Here, switches SW1 and SW2 are turned on or off based on a selection signal RCSEL, switches SW3 and SW4 are turned on or off based on a selection signal VCSEL, and switches SW5 and SW6 are turned on or off based on a selection signal ZCSEL. Any switch is turned on. The comparator 13 outputs a voltage LSCDET of a comparison result signal.

[0089] Hereinafter, problems 1 to 3 of the current monitoring circuit 11E configured as described above will be described.

[0090] (Topic 1)

[0091] When it is desired to monitor multiple detection values ​​such as zero, forward overcurrent, and reverse overcurrent of the inductor current Iind, even if the input conversion offset voltage Voffset of the common comparator 13 is the same, since the reference voltage Vrefr and the monitoring voltages Vmoniz and Vmoniv are deviated from each other, it is necessary to individually adjust the voltages generated in the MOS transistors Q3 to Q5, such as trimming, which increases the number of correction items during mass production and the chip area based on the correction circuit ( Fig.12 ).

[0092] Fig.13 Yes means Fig.12 A block diagram of a part of the structure of the current monitoring circuit 11E. Fig.14 Yes means including Fig.13 The following is a timing diagram of each signal of an operation example of a switching regulator of a current monitoring circuit.

[0093] (Topic 2)

[0094] Since both the reference voltage and the monitoring voltage have finite impedance, when the switching switches SW1 to SW6 are opened and closed, there is a concern that the noise via the parasitic capacitors C1 and C2 will overlap with the differential input and generated voltage of the comparator 13 and may result in erroneous detection ( Fig.13 as well as Fig.14 ).

[0095] Fig.15 Yes means Fig.12 A block diagram of the structure of the current monitoring circuit 11E. In addition, Fig.16 Yes means including Fig.15 The following is a timing diagram of each signal of an operation example of a switching regulator of a current monitoring circuit.

[0096] (Topic 3)

[0097] When the switching switches SW1 to SW6 are opened and closed, if the timing difference of the control signals of each SW1 to SW6 causes them to be turned on at the same time, there is a concern that the reference voltage and the monitoring voltage may be crossed and misdetected ( Fig.15 as well as Fig.16 ).

[0098] Hereinafter, embodiments for solving the above-mentioned problems 1 to 3 will be described.

[0099] (Implementation Method 1)

[0100] Fig.17 11F is a block diagram showing a configuration example of a switching regulator including the current monitoring circuit 11F according to the first embodiment.

[0101] exist Fig.17 In the embodiment, the current monitoring circuit 11F is configured to include four constant current sources IS21 to IS24, switches SW11 and SW12, MOS transistors Q3 and Q4, and a comparator 13. The switching regulator including the current monitoring circuit 11F includes a switching modulation circuit 10 as a control circuit.

[0102] The power supply voltage Vdd is connected to the inverting input terminal of the comparator 13 via the constant current source IS21, and is connected to the inverting input terminal of the comparator 13 via the switch SW11 and the constant current source IS22 which are controlled by the selection signal RCSEL. In addition, the power supply voltage Vdd is connected to the non-inverting input terminal of the comparator 13 via the constant current source IS23, and is connected to the non-inverting input terminal of the comparator 13 via the switch SW12 and the constant current source IS24 which are controlled by the selection signal VCSEL. Here, a MOS transistor Q3 to which the power supply voltage Vdd is applied to the gate is inserted between the non-inverting input terminal of the comparator 13 and the switch voltage Vsw. In addition, a MOS transistor Q4 to which the power supply voltage Vdd is applied to the gate is inserted between the inverting input terminal of the comparator 13 and the ground voltage.

[0103] The non-inverting input terminal of the comparator 13 is a generating point of the monitoring voltage Vmoni, and becomes the monitoring voltage Vmoni. The inverting input terminal is a generating point of the reference voltage Vref, and becomes the reference voltage Vref. The comparator 13 compares these voltages and outputs a voltage LSCDET of a comparison result signal. That is, the constant current sources IS21, IS22 and the switch SW11 constitute a reference voltage circuit for generating the reference voltage Vref, and the constant current sources IS23, IS24 and the switch SW12 constitute a monitoring circuit for generating the monitoring voltage Vmoni for monitoring the switch voltage Vsw.

[0104] exist Fig.17 In the embodiment, the switching modulation circuit 10 generates a PWM signal, for example, for switching the MOS transistors Q1 and Q2 constituting the inverter circuit based on the output voltage Vout fed back to the terminal T4, and switches the MOS transistors Q1 and Q2 so that the output voltage Vout becomes a predetermined value. In addition, the switching modulation circuit 10 controls the switching (ON) or disconnection (OFF) of the switches SW11 and SW12 by generating the selection signals RCSEL and VCSEL at different timings as described above and outputting them to the control terminals of the switches SW11 and SW12, respectively.

[0105] According to the above-mentioned Fig.17 The current monitoring circuit 11F does not generate the reference voltage Vref and the monitoring voltage Vmoni separately and switches them, but changes the voltages generated by the MOS transistor Q3 and the MOS transistor Q4 at the mutually different timings. Thus, by changing the reference voltage Vref or the monitoring voltage Vmoni, the problem can be solved. Fig.12 The three problems 1 to 3 of the comparative example are solved. Furthermore, by sharing the reference voltage circuit and the monitoring circuit, it is possible to reduce the chip area and reduce the circuit current consumption.

[0106] (Solution to Problem 1)

[0107] Regarding Topic 1 of the comparative example, by using the MOS transistor Q4 and its bias current (based on IS21 and IS22) that generate the reference voltage Vref and the MOS transistor Q3 and its bias current (based on IS23 and IS24) that generate the monitoring voltage, as long as one of the three detection currents is corrected, the other detection values ​​are also corrected.

[0108] exist Fig.12 In the current monitoring circuit 11E, when the on-resistance of the MOS transistor Q5 is made smaller than the design value and the on-resistance of the MOS transistor Q3 is made larger than the design value, the monitoring voltage Vmoniz and the monitoring voltage Vmoniv need to be corrected in the opposite direction. Fig.17 In the current monitoring circuit 11F, as described above, the circuit is shared and the deviation is made the same, so the correction can be completed by only performing a single fine adjustment of the input conversion offset, on-resistance, bias current, etc. of the comparator 13. Thus, the above-mentioned problem 1 can be solved.

[0109] (Solution to Issue 2)

[0110] The above-mentioned problem 2 can be solved by preventing direct parasitic capacitance of the switches SW11 and SW12 from being seen at the node of the reference voltage Vref and the node of the monitor voltage Vmoni.

[0111] (Solution to Issue 3)

[0112] Regardless of whether it is zero or forward overcurrent (switching the selection signal VCSEL to turn on the switch SW12 and disconnect the switch SW11), or zero or reverse overcurrent (switching the selection signal RCSEL to turn on the switch SW11 and disconnect the switch SW12), the switches SW11 and SW12 can be turned on by one switch in each case, so there is no need to adjust the control timing. Thus, the above-mentioned problem 3 can be solved.

[0113] As described above, according to Embodiment 1, not only the comparator 13 is shared, but also the monitoring circuit and the reference voltage circuit are shared, so that the manufacturing deviation of multiple detection circuits can be corrected at once. In addition, there is no need to adjust the control timing, and direct parasitic capacitance cannot be seen in the input terminal of the comparator 13, so erroneous detection can be avoided.

[0114] (Implementation Method 2)

[0115] Fig.18 11 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11G according to the second embodiment. Fig.18 The current monitoring circuit 11G and Fig.17 Compared with the current monitoring circuit 11F, the following points are different.

[0116] (1) The constant current source IS22 is inserted between the switch SW11 and the inverting input terminal of the comparator 13 .

[0117] (2) The constant current source IS24 is inserted between the switch SW11 and the inverting input terminal of the comparator 13 .

[0118] The differences are described below.

[0119] There are many implementation methods or technologies for generating the reference voltage Vref or the monitoring voltage Vmoni. Fig.18 Embodiment 2 is an example thereof, which is an example in which switches SW11 and SW12 are arranged downstream of the current of constant current sources IS22 and IS24 when the impedance of reference voltage Vref or monitoring voltage Vmoni is low or the parasitic capacitance of switches S11 and SW12 is small.

[0120] According to the second embodiment configured as above, in addition to the above-mentioned effects, the same effects as those of the first embodiment are achieved.

[0121] (Implementation method 3)

[0122] Fig.19 1 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11H according to the third embodiment. Fig.19 The current monitoring circuit 11H and Fig.17 Compared with the current monitoring circuit 11F, the following points are different.

[0123] (1) A resistor Rmoni is provided instead of the MOS transistor Q3.

[0124] (2) A resistor Rref is provided instead of the MOS transistor Q4.

[0125] The differences are described below.

[0126] Fig.19 The current monitoring circuit 11H is an example in which the reference voltage Vref or the monitoring voltage Vmoni is generated by the resistors Rmoni and Rref instead of the MOS transistors Q3 and Q4. Thus, the reference voltage Vref or the monitoring voltage Vmoni can be changed by the resistance value instead of the on-resistance of the MOS transistor.

[0127] According to the third embodiment configured as above, the same operational effects as those of the first embodiment are achieved.

[0128] (Implementation 4)

[0129] Fig. 20 11I is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11I according to the fourth embodiment. Fig. 20 The current monitoring circuit 11I and Fig.17 Compared with the current monitoring circuit 11F, the following points are different.

[0130] (1) A MOS transistor Q3A is provided instead of the switch SW12, the constant current source IS24, and the MOS transistor Q3.

[0131] (2) A MOS transistor Q4A is provided instead of the switch SW11, the constant current source IS22, and the MOS transistor Q4.

[0132] The differences are described below.

[0133] exist Fig. 20In the embodiment, the MOS transistors Q3A and Q4A are each formed of a circuit in which a plurality of MOS transistors are connected in series, for example, and some of the MOS transistors are short-circuited based on the selection signals VCSEL and RCSEL, thereby changing the actual transistor size, thereby changing the resistance value between the source and the drain of the MOS transistors Q3A and Q4A, changing the current flowing therethrough, thereby changing the monitor voltage Vmoni and the reference voltage Vref. In addition, instead of the MOS transistors Q3A and Q4A formed of a plurality of MOS transistors connected in series, for example, a circuit in which a plurality of resistors are connected in series may be used.

[0134] According to the fourth embodiment configured as described above, in addition to the above-described effects, the same effects as those of the first embodiment are achieved.

[0135] (Implementation method 5)

[0136] Fig.21 11 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11J according to the fifth embodiment. Fig.21 The current monitoring circuit 11J and Fig.17 Compared with the current monitoring circuit 11F, the following points are different.

[0137] (1) The switch SW11 and the constant current source IS22 are deleted.

[0138] The differences are described below.

[0139] In the above-constructed Fig.21 In the current monitoring circuit 11J, the current used to generate the monitoring voltage Vmoni can also be switched by two values ​​between the specified current value I11 and the specified current value I12, thereby switching the monitoring voltage Vmoni by two values ​​between the specified voltage value V11 and the specified voltage value V12.

[0140] According to the fifth embodiment configured as described above, in addition to the above-mentioned effects, the same effects as those of the first embodiment are achieved.

[0141] (Implementation method 6)

[0142] Fig. 22 1 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11K according to the sixth embodiment. Fig. 22 The current monitoring circuit 11K and Fig.17 Compared with the current monitoring circuit 11F, the following points are different.

[0143] (1) The switch SW12 and the constant current source IS24 are deleted.

[0144] The differences are described below.

[0145] In the above-constructed Fig. 22 In the current monitoring circuit 11K, the current used to generate the reference voltage Vref may be switched between two values ​​between the specified current value I11 and the specified current value I12, thereby switching the reference voltage Vref between two values ​​between the specified voltage value V11 and the specified voltage value V12.

[0146] According to the sixth embodiment configured as described above, in addition to the above-described effects, the same effects as those of the first embodiment are achieved.

[0147] (Implementation 7)

[0148] Fig.23 1 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11L according to the seventh embodiment. Fig.23 The current monitoring circuit 11L and Fig.17 Compared with the current monitoring circuit 11F, the following points are different.

[0149] (1) The switch SW11, constant current sources IS21, IS22 and MOS transistor Q4 are deleted.

[0150] (2) The inverting input terminal of the comparator 13 is grounded.

[0151] According to the seventh embodiment configured as described above, the same operational effects as those of the first embodiment are achieved.

[0152] (Implementation 8)

[0153] Fig.24 11 is a block diagram showing a configuration example of a switching regulator including a current monitoring circuit 11M according to the eighth embodiment. Fig.24 The current monitoring circuit 11M is configured to include a comparator 13, constant current sources IS31 and IS32, a switch SW21, and a MOS transistor Q3a.

[0154] exist Fig.24 In the embodiment, the power supply voltage Vdd is connected to the non-inverting input terminal of the comparator 13 via the MOS transistor Q3a whose gate is grounded. The non-inverting input terminal of the comparator 13 is grounded via the constant current source IS31, and is grounded via the switch SW21 and the constant current source IS32. In addition, the switch SW21 is turned on (ON) or off (OFF) based on the overcurrent selection signal.

[0155] In the above-constructed Fig.24In the current monitoring circuit 11M, by turning on (ON) or off (OFF) the switch SW21, the current of the MOS transistor Q3a in the non-inverting input terminal of the comparator 13 changes, and the reference voltage Vref changes. The comparator 13 compares the switch voltage Vsw with the reference voltage Vref and outputs a comparison result signal HSCDET.

[0156] exist Fig.24 The current monitoring circuit 11M is characterized in that it monitors the inductor current Iind when the inductor current passes through the MOS transistor Q1 which is a high-side driver element.

[0157] According to the eighth embodiment configured as described above, in addition to the above-described effects, the same effects as those of the first embodiment are achieved.

[0158] (Other Modifications)

[0159] In the above first to eighth embodiments, the MOS transistors Q1 and Q2 as a pair of switch elements are arranged outside the current monitoring circuits 11F to 11M, but the present invention is not limited thereto and the MOS transistors Q1 and Q2 may be built into the current monitoring circuits 11F to 11M.

[0160] Industrial Applicability

[0161] As described above in detail, according to the switching regulator according to the present invention, it is possible to reduce the circuit area compared with the conventional technology while maintaining highly stable quality in the switching regulator.

[0162] Description of Reference Numerals

[0163] 1 switching regulator; 10 switching modulation circuit; 11 zero-crossing detector; 11A~11M current monitoring circuit; 12 current detector; 13 comparator; C1~C2 parasitic capacitance; Cout output capacitor; Ind inductor; INV1 inverter; IS1~IS32, IS1A constant current source; NOR1 NOR gate; Q1~Q5, Q3A, Q5AMOS transistor; Rload load resistor; Rref reference resistor; SW1~SW21 switch; T1~T4 terminal; VIS1~VIS3 variable current source.

Claims

1. A switching regulator comprising a pair of switching elements connected in series with each other, the switching regulator comprising: a comparator for comparing a switching voltage corresponding to an inductor current flowing from the switching regulator to the inductor with a predetermined reference voltage and outputting a comparison result signal; a monitoring circuit generating a current for generating a monitoring voltage for monitoring the switch voltage, A reference voltage circuit generates a current for generating the reference voltage; as well as a control circuit that outputs a plurality of selection signals indicating a plurality of mutually different timings to at least one of the monitoring circuit and the reference voltage circuit, At least one of the monitoring circuit and the reference voltage circuit changes the generated current according to the plurality of timings, At least one of the monitoring circuit and the reference voltage circuit is commonly used for the plurality of timings.

2. The switching regulator according to claim 1, wherein: At least one of the monitoring circuit and the reference voltage circuit includes a circuit in which a first constant current source, a second constant current source connected in series with each other, and a series circuit of switches are connected in parallel.

3. The switching regulator according to claim 2, wherein: A point at which the reference voltage of the reference voltage circuit is generated is grounded via a MOS transistor having a gate to which a predetermined voltage is applied.

4. The switching regulator according to claim 2, wherein: A point at which the reference voltage of the reference voltage circuit generates the reference voltage is grounded via a resistor.

5. The switching regulator according to claim 2, wherein: A generation point of the reference voltage of the reference voltage circuit is grounded.

6. The switching regulator according to claim 1, wherein: The monitoring circuit and the reference voltage circuit each include a first constant current source connected to a generating point of the monitoring voltage or the reference voltage and a MOS transistor having a predetermined voltage applied to a gate. By applying the selection signal to the back gate of the MOS transistor, the resistance value of the MOS transistor is changed, thereby changing the monitor voltage or the reference voltage.

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