Base station fronthaul interface parsing processor and message parsing method

Abstract

The present invention provides a base station front-haul interface parsing processor and a message parsing method, belonging to the field of communication technology, wherein the processor comprises a register group module composed of a plurality of registers, an operation module, a block moving module, a data recovery module and a cache, wherein the operation module processes the message data under the drive of a parsing instruction sequence when the message type of the message data is a U-plane message and generates a block moving control word and a data recovery control word, the block moving module moves the message data from the register group module based on the block moving control word and writes the message data into the cache, the data recovery module loads the message data from the cache based on the data recovery control word for recovery, and sends the recovered message data until the sending of a message data is completed. The present invention configures the control words for realizing block moving and data recovery in the processor through the operation module, constructs a new architecture for collaborative parsing of message data by ASIP and accelerator, and realizes a high-speed and high-throughput processor under the parsing of message data of the front-haul interface.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a base station fronthaul interface parsing processor and a message parsing method. Background Art

[0002] The fronthaul interface is the data transmission bridge between the air interface and the base station processing unit. The performance of the fronthaul interface processor in parsing message data will affect the execution effect of the upper-layer application software.

[0003] Currently, network processors that support the eCPRI protocol, O-RAN protocol, and similar protocols generally have the disadvantages of high cost, slow processing speed, and can only support relatively small data throughput when parsing message data.

[0004] Therefore, it is necessary to provide a low-cost, high-speed, and high-throughput base station fronthaul interface parsing processor. Summary of the invention

[0005] The present invention provides a base station fronthaul interface parsing processor and a message parsing method, which are used to solve the defects of the network processor in the prior art, such as high cost, slow processing speed and only supporting relatively small data throughput, and realize a low-cost, high-speed and large-throughput base station fronthaul interface parsing processor.

[0006] The present invention provides a base station fronthaul interface analysis processor, comprising: a register group module composed of multiple registers, a calculation module, a block moving module, a data recovery module and a cache;

[0007] The register group module is used to temporarily store message data and the calculation results of the calculation module;

[0008] The operation module is used to extract the header of the message data from the register group module under the drive of the parsing instruction sequence after responding to the start signal of the data packet, process the header, and determine the message type of the message data based on the header processing result; the parsing instruction sequence is composed of a plurality of special processing instructions in the special processing instruction set;

[0009] The operation module is further used for processing the message data under the drive of the parsing instruction sequence when the message type is a U-plane message, and generating a block move control word and a data recovery control word based on the message processing result;

[0010] The block moving module is used to move the message data from the register group module based on the block moving control word, and write the message data into the cache;

[0011] The data recovery module is used to load the message data from the cache based on the data recovery control word after responding to the timing transmission signal, restore the data bit width and size of the message data, and send the recovered message data until the transmission of one message data is completed.

[0012] According to a base station fronthaul interface parsing processor provided by the present invention, the operation module is further used to process the message data under the drive of the parsing instruction sequence when the message type is a C-plane message, and obtain parameters for U-plane message parsing based on the message processing result;

[0013] And / or, the operation module is further used to discard the message data when the message type is not a forward transmission message.

[0014] According to a base station fronthaul interface parsing processor provided by the present invention, the register group module is mapped with a data input interface and a data output interface, the data input interface and the data output interface are externally connected to an Ethernet switch, and the register group module and the Ethernet switch complete data writing based on a hardware handshake method.

[0015] According to a base station fronthaul interface parsing processor provided by the present invention, the block move control word includes a first initial cache address control word, a first data length control word, a register initial number control word and a register quantity control word;

[0016] The generating of the block move control word and the data recovery control word based on the message processing result includes: generating the first initial cache address control word, the first data length control word, the register initial number control word and the register quantity control word based on the message processing result;

[0017] The moving the message data from the register group module based on the block move control word and writing the message data into the cache comprises:

[0018] Based on the register initial number control word and the register quantity control word, determining a target register for carrying the message data from the register group module; the first register in the target register is the initial register corresponding to the register initial number control word;

[0019] Starting from the initial register in sequence, the message data is moved from the target register in a loop, and the message data is written into the storage space in the cache with the cache address corresponding to the first initial cache address control word as the initial cache address, until the length of the message data being moved is equal to the data length corresponding to the first data length control word.

[0020] According to a base station fronthaul interface parsing processor provided by the present invention, the block shift control word further includes a low byte number control word and a high byte number control word;

[0021] The method starts from the initial register in sequence, cyclically moves the message data from the target register, and writes the message data into a storage space in the cache with the cache address corresponding to the first initial cache address control word as the initial cache address, including:

[0022] Based on the low byte number control word, determining a first byte number;

[0023] Determining a second byte number based on the high byte number control word;

[0024] Starting from the initial register in sequence, the message data is transferred from the target register in a loop, the low byte data of the first byte number in the message data transferred from the previous register is used as the high-order data, and the high byte data of the second byte number in the message data transferred from the next register is used as the low-order data;

[0025] Sequentially splicing the high-order data and the low-order data to obtain spliced ​​message data;

[0026] The spliced ​​message data is written into a storage space in the cache with the cache address corresponding to the first initial cache address control word as the initial cache address, until the length of the message data being transported is equal to the data length corresponding to the first data length control word.

[0027] According to a base station fronthaul interface parsing processor provided by the present invention, the data recovery control word includes a second initial cache address control word, a second data length control word, a register number control word, a compression bit width control word and a compression method control word;

[0028] The step of loading the message data from the cache based on the data recovery control word, recovering the data bit width and size of the message data, and sending the recovered message data includes:

[0029] The message data is sequentially loaded from the storage space in the cache with the cache address corresponding to the second initial cache address control word as the initial cache address, and the data bit width and size of the message data are restored according to the compression bit width corresponding to the compression bit width control word and the compression method corresponding to the compression method control word, and the restored message data is sent to the register corresponding to the register number control word in the register group module until the length of the loaded message data is equal to the data length corresponding to the second data length control word.

[0030] According to a base station fronthaul interface parsing processor provided by the present invention, each dedicated processing instruction in the dedicated processing instruction set is configured with a calculation method of the dedicated processing instruction, a bit starting position of two operands, a bit length and a number of bits;

[0031] The operation module comprises: a first masker, a second masker, a first shifter, a second shifter and an operator;

[0032] The first masker is used to perform a mask operation on one of the operands using a first mask to obtain a first mask result; the first mask is determined based on a bit starting position and a bit length of the one operand;

[0033] The second masker is used to perform a mask operation on another operand using a second mask to obtain a second mask result; the second mask is determined based on a bit starting position and a bit length of the other operand;

[0034] The first shifter is used to shift the first mask result based on the number of bits of the first operand to obtain a first shift result;

[0035] The second shifter is used to shift the second mask result based on the number of bits of the other operand to obtain a second shift result;

[0036] The operator is used to operate the first shift result and the second shift result based on the calculation method to obtain the operation result and complete the execution of the dedicated processing instruction.

[0037] A base station fronthaul interface parsing processor according to the present invention further includes: a fast table lookup module, used to determine the header processing result based on the simultaneous matching result of the header and each key value record group; the fast table lookup module stores a plurality of key value record groups; each of the key value record groups includes a plurality of key value records;

[0038] The extracting the header of the message data from the register group module and processing the header includes: extracting the header of the message data from the register group module, forwarding the header to the fast table lookup module, and receiving the header processing result returned by the fast table lookup module.

[0039] A base station fronthaul interface analysis processor provided by the present invention further includes: a program control module, an instruction storage module, a decoder module and a check module; the check module includes a checksum module and a cyclic redundancy check module;

[0040] The program control module is used to manage program counts and arbitrate program count change requests sent by various modules of the base station fronthaul interface analysis processor;

[0041] The instruction storage module is used to store the parsed instruction sequence;

[0042] The decoder module is used to decode the parsing instructions in the parsing instruction sequence and distribute the decoding results to the various modules of the base station front transmission interface parsing processor to drive the various modules to work;

[0043] The checksum module is used to complete the checksum calculation of the message data;

[0044] The cyclic redundancy check module is used to complete the verification calculation of the cyclic redundancy check sequence of the message data.

[0045] The present invention also provides a message parsing method based on any of the above-mentioned base station fronthaul interface parsing processors, comprising:

[0046] After responding to the start signal of the data packet, the control operation module extracts the header of the message data from the register group module under the drive of the parsing instruction sequence, processes the header, and determines the message type of the message data based on the header processing result; the parsing instruction sequence is composed of a plurality of special processing instructions in a special processing instruction set; the register group module is composed of a plurality of registers, which are used to temporarily store the message data and the operation result of the operation module;

[0047] Controlling the operation module to process the message data under the drive of the parsing instruction sequence when the message type is a U-plane message, and generating a block move control word and a data recovery control word based on the message processing result;

[0048] The control block moving module moves the message data from the register group module based on the block moving control word, and writes the message data into the cache;

[0049] After responding to the timing transmission signal, the control data recovery module loads the message data from the cache based on the data recovery control word, recovers the data bit width and size of the message data, and sends the recovered message data until the transmission of one message data is completed.

[0050] The base station fronthaul interface parsing processor and message parsing method provided by the present invention process message data under the drive of a parsing instruction sequence obtained by flexible programming based on a dedicated processing instruction set by a computing module, and generate control words for realizing block movement function and data recovery function, that is, by configuring the control words for realizing block movement function and data recovery function in the processor through ASIP, a new architecture for collaborative parsing of message data by ASIP and ASIC accelerator is constructed in the processor, which has low cost and can improve the rate of special functions such as block movement function and data recovery function in the process of message data parsing, thereby improving the processing speed of message data parsing and meeting the real-time requirements of message processing at the same time, realizing a high-speed and high-throughput processor in the scenario of message data parsing of the base station fronthaul interface; The register group module loads the message data, and the data input to the processor can directly participate in the operation of the operation module without the need to store the message data in the cache first and then extract it from the cache by the operation module. This can save the time of reading the input message data, optimize the timing of message data parsing and simplify the programming difficulty of the parsing instruction sequence; by using a dedicated processing instruction set when pre-programming the parsing instruction sequence, the number of parsing instructions required to be programmed by the operator when parsing the message data can be reduced, the instruction overhead can be reduced and the message data parsing speed can be improved; when processing the U-plane message, the processed message data is temporarily stored in the cache and sent only after receiving the timing transmission signal, that is, the timing requirements of the 5G fronthaul interface and the wireless system are realized through the cache and the external control signal, and the network jitter is eliminated at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1 This is one of the structural schematic diagrams of the base station fronthaul interface parsing processor provided by the present invention.

[0053] Figure 2 This is one of the flow charts of parsing message data provided by the present invention.

[0054] Figure 3 This is the second flow chart of parsing message data provided by the present invention.

[0055] Figure 4 This is an example diagram of the alignment message data provided by the present invention.

[0056] Figure 5 It is a structural schematic diagram of the operation module provided by the present invention.

[0057] Figure 6 This is the second structural diagram of the base station fronthaul interface parsing processor provided by the present invention.

[0058] Figure 7 It is a structural schematic diagram of the fast table lookup module provided by the present invention.

[0059] Figure 8 It is a flow chart of a message parsing method based on a base station fronthaul interface parsing processor provided by the present invention. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] It should be noted that, in the description of the present invention, the term "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0062] The terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" means at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0063] Combine the following Figure 1-Figure 8 The present invention describes a base station fronthaul interface parsing processor and a message parsing method.

[0064] Application Specific Instruction Set Processor (ASIP), also known as a dedicated processor, is a programmable platform that is customized for a specific operation or a certain type of algorithm. It has both software programming capabilities and is oriented to accelerated processing in a specific field. It can use the same chip on multiple related applications, different versions of applications, and even future applications. It has the advantages of sharing the chip design cost on a large number of chips, having enough functions and flexibility to deal with chip modifications during product development, and extending the product life cycle. ASIP is often programmed for specific fields and has strong specialization. It has a significant performance improvement over general-purpose processors.

[0065] Corresponding to ASIP, Application Specific Integrated Circuit (ASIC) is specially used to implement a certain type of customized circuit algorithm. In comparison, ASIC has higher performance but poorer flexibility, while ASIP has slightly lower performance than ASIC but has greater flexibility.

[0066] In the design and implementation of LTE (Long Time Evolution) and 5G NR (New Radio), the baseband processing unit (Building Baseband Unit, BBU) and the remote radio unit (Remote Radio Unit, RRU) are usually split and connected using optical fiber. The interface between the RRU and BBU is called the fronthaul interface.

[0067] Common fronthaul interfaces include Common Public Radio Interface (CPRI) and enhanced CPRI (eCPRI). The CPRI protocol is block-based data transmission, and its application scenarios are relatively simple. In addition, there are a large number of custom fields, which makes the CPRI protocol poorly adaptable. Compared with the CPRI protocol, the eCPRI protocol is used in the implementation of 5G. The eCPRI protocol is carried on the Ethernet, MAC layer or TCP / IP layer to integrate the eCPRI protocol into the TCP / IP protocol family. Compared with the proprietary CPRI protocol, the universality of the eCPRI protocol allows the RRU to no longer be attached to the BBU, thus acting as an independent network element. The network management center can directly manage the RRU, and no longer needs to rely on the BBU to manage the RRU. The protocol between the BBU and the RRU can be standardized, which provides an architectural guarantee for the interconnection and interoperability of BBU and RRU from different manufacturers, and greatly improves the universality.

[0068] The Open Radio Access Network (O-RAN) protocol is a specific implementation of the eCPRI protocol. The eCPRI protocol is only a transport layer protocol and does not define application layer protocol specifications such as IQ data format and real-time control plane data format above the service access point. The O-RAN protocol defines in detail the specific usage details when used as the fronthaul interface of NR, making the fronthaul interface implemented using the O-RAN protocol have good adaptability.

[0069] The eCPRI protocol and O-RAN protocol have the following characteristics when applied: First, both the eCPRI protocol and the O-RAN protocol are relatively new, and there are not many hardware devices that can support the eCPRI protocol and the O-RAN protocol (such as those based on FAGA implementation), but both have the defects of high cost, slow processing speed and can only support relatively small data throughput; second, the eCPRI protocol and the O-RAN protocol are in the process of continuous evolution. If ASIC is used, the form risk is high and it is difficult to cope with subsequent protocol upgrades; third, the eCPRI protocol and the O-RAN protocol work on the fronthaul interface, which is the transmission bridge between the air interface and the base station processing unit data, requiring high real-time and high accuracy that traditional network processors cannot achieve; finally, due to the characteristics of the fronthaul interface service, in order to reduce the complexity of hardware design, improve the data transmission efficiency of the fronthaul interface and reduce the system bandwidth, the message data of the fronthaul interface will be compressed before transmission, resulting in changes in the data bit width and size of the message data, and the boundary of the message data is no longer aligned with the transmission bit width, which requires that when parsing the message data, the network processor needs to have the ability to decompress non-aligned data.

[0070] In view of the characteristics of the eCPRI protocol and the O-RAN protocol in their applications, the processor that supports the eCPRI protocol and the O-RAN protocol must at least meet the following requirements: (1) high speed and large throughput. Taking the fronthaul interface of a 5G NR 4-transmit 4-receive small base station as an example, the processor must achieve at least an average throughput of 10 Gbps and support a burst throughput processing capability of 60 Gbps; (2) support the recovery of compressed source message data; (3) support the reordering of message data; and (4) support the sending and parsing of message data.

[0071] In view of this, the base station fronthaul interface parsing processor provided by the present invention is a network processor (NP) based on ASIP, which can support the message parsing work of the eCPRI protocol, O-RAN protocol and similar protocols when working on the base station fronthaul interface, and can process data packets and data frames in the network in real time at line speed, and can be widely used in scenarios where message data needs to be parsed in the fields of mobile communications, broadband communications, industrial control, etc.

[0072] Figure 1 FIG. 1 is one of the structural diagrams of the base station fronthaul interface parsing processor provided by the present invention, such as Figure 1 As shown, the base station fronthaul interface analysis processor includes but is not limited to a register group module 101 composed of multiple registers, a calculation module 102, a block movement module 103, a data recovery module 104 and a cache 105. The solid arrows represent the data flow direction of the message data, and the dotted arrows represent the data flow direction of the control word.

[0073] The register group module 101 is used to temporarily store message data and the calculation results of the calculation module 102.

[0074] The operation module 102 is used to extract the header of the message data from the register group module 101 under the drive of the parsing instruction sequence after responding to the start of packet (SOP) signal, process the header, and determine the message type of the message data based on the header processing result.

[0075] The operation module 102 is further used to process the message data under the drive of the parsing instruction sequence when the message type is a U-plane message, and generate a block move control word and a data recovery control word based on the message processing result.

[0076] The block transfer module 103 is used to transfer the message data from the register group module 101 based on the block transfer control word, and write the message data into the cache 105 .

[0077] The data recovery module 104 is used to load the message data from the cache 105 based on the data recovery control word after responding to the timing transmission signal, recover the data bit width and size of the message data, and send the recovered message data until the transmission of one message data is completed.

[0078] The parsing instruction sequence is composed of a number of special processing instructions in a special processing instruction set.

[0079] When processing the message data parsing task, it is necessary to pre-program the various protocols used by the message data, and then obtain a parsing instruction sequence consisting of several parsing instructions to drive each module of the base station fronthaul interface parsing processor to process the message data. When processing message data based on the base station fronthaul interface parsing processor, the parsing instruction sequence will be composed of several special processing instructions in a pre-set special processing instruction set.

[0080] The number of special processing instructions involved in the parsing instruction sequence and the number of times they are reused are determined according to the specific message data parsing task, and the present invention does not impose any limitation on this.

[0081] The calculation results of the calculation module 102 include but are not limited to header processing results, message processing results, etc.

[0082] The block transfer control word is a control word for controlling the block transfer module 103 to transfer message data.

[0083] The data recovery control word is a control word for controlling the data recovery module 104 to transport message data.

[0084] Specifically, Figure 2 It is one of the flow charts of parsing message data provided by the present invention, such as Figure 2 As shown, after the base station fronthaul interface parsing processor starts working, driven by instructions, the operation module 102 polls the SOP signal of the data packet written into the register group module 101. After responding to the SOP signal, the operation module 102 starts loading the message data through the register group module 101.

[0085] In the process of loading message data, the operation module 102, driven by the parsing instruction sequence, extracts the header of the message data from the register group module 101, processes the header, and determines which message type the message data belongs to based on the header processing result, such as the forward transmission message, U-plane message, C-plane message, etc.

[0086] When it is determined that the currently parsed message data belongs to the U-plane message, the operation module 102, driven by the parsing instruction sequence, processes the message data for the U-plane message, continuously reads and parses the U-plane header in the message data from the register group module 101, calculates the payload address, payload length and other information in the message data, obtains the message processing result based on the calculated information, and further generates the block move control word and the data recovery control word based on the information in the message processing result.

[0087] Furthermore, the block moving module 103 is configured according to the generated block moving control word, so that the block moving module 103 continuously moves the payload in the message data from the register group module 101 according to the block moving control word, and writes the payload in the message data into the cache 105 .

[0088] Wait for the scheduled sending signal. After receiving the scheduled sending signal and responding, configure the data recovery module 104 according to the previously generated data recovery control word. The data recovery module 104 loads the payload in the message data from the cache 105 according to the data recovery control word, restores the payload in the message data to the original data bit width and size, and sends the recovered message data until the sending of a message data is finally completed, thereby completing the parsing of the currently processed message data.

[0089] Further, after completing the parsing of the currently processed message data, continue to poll the SOP signal of the received data packet, receive the next SOP signal and respond, start from the step of the operation module 102 loading the next message data through the register group module 101, and parse the next message data.

[0090] The base station fronthaul interface parsing processor provided by the present invention processes message data under the drive of a parsing instruction sequence obtained by flexible programming based on a dedicated processing instruction set by a computing module, and generates a control word for realizing a block moving function and a data recovery function, that is, the control word for realizing the block moving function and the data recovery function in the processor is configured by ASIP, and a new architecture for collaborative parsing of message data by ASIP and ASIC accelerator is constructed in the processor, which has low cost and can improve the rate of special functions such as block moving function and data recovery function in the process of message data parsing, thereby improving the processing speed of message data parsing and meeting the real-time requirements of message processing at the same time, and realizing a high-speed and high-throughput processor in the scenario of message data parsing of the base station fronthaul interface; by means of a register group The module loads message data, and the data input to the processor can directly participate in the operation of the operation module without the need to store the message data in the cache first and then extract it from the cache by the operation module. This can save the time of reading the input message data, optimize the timing of message data parsing and simplify the programming difficulty of the parsing instruction sequence; by using a dedicated processing instruction set when pre-programming the parsing instruction sequence, the number of parsing instructions required to be programmed by the operator when parsing the message data can be reduced, the instruction overhead can be reduced and the message data parsing speed can be improved; when processing the U-plane message, the processed message data is temporarily stored in the cache and sent only after the timing transmission signal is received, that is, the timing requirements of the 5G fronthaul interface and the wireless system are realized through the cache and the external control signal, and the network jitter is eliminated at the same time.

[0091] Based on the above embodiment, as an optional embodiment, the operation module is further used to process the message data under the drive of the parsing instruction sequence when the message type is a C-plane message, and obtain parameters for U-plane message parsing based on the message processing result;

[0092] And / or, the operation module is further used to discard the message data when the message type is not a forward transmission message.

[0093] Specifically, the result obtained by the operation module extracting the header of the message data and processing it under the drive of the parsing instruction sequence is not only to determine that the message data belongs to the U-plane message, but also to determine that the message type is a C-plane message or is not a forward message. Among them, the situation where the message type is not a forward message means that the message type is neither a U-plane message nor a C-plane message.

[0094] When the message type is a C-plane message, the operation module processes the message data under the drive of the parsing instruction sequence, and the obtained message processing result can be used as the parameter for U-plane message parsing; when the message type is not a forward transmission message, the message data is discarded, and the operation module does not perform subsequent steps on the message data.

[0095] Figure 3 This is the second flow chart of parsing message data provided by the present invention, such as Figure 3 As shown, when the operation module extracts the header of the message data from the register group module and processes it under the drive of parsing the instruction sequence, it first determines whether the message data is a forward transmission message based on the header processing result. If it is not a forward transmission message, the message data is discarded, and the step of responding to the start signal of the data packet is returned to wait for the arrival of the next message data; if it is a forward transmission message, it is further determined whether the type of the message data belongs to a C-plane message or a U-plane message.

[0096] If the header processing result indicates that the message type is a C-plane message, the operation module obtains parameters that can be used for U-plane message parsing according to the message processing result; if the message type is a U-plane message, a block move control word and a data recovery control word are generated based on the message processing result.

[0097] The base station fronthaul interface parsing processor provided by the present invention accurately judges whether the message data belongs to the fronthaul message, U-plane message and C-plane message through the operation module, thereby obtaining different subsequent parameters according to different message types using the message processing results to perform different processing, thereby improving the processing speed of message data parsing.

[0098] Based on the above embodiment, as an optional embodiment, the register group module is mapped with a data input interface and a data output interface, the data input interface and the data output interface are externally connected to an Ethernet switch, and the register group module and the Ethernet switch complete data writing based on a hardware handshake.

[0099] Optionally, the register group module and the Ethernet switch complete data writing based on a handshake method of hardware Semaphone.

[0100] Specifically, after responding to the SOP signal, the operation module can directly load the message data from the external Ethernet switch through the data input interface and the data output interface mapped in the register group module, and then extract the message data from the register group for processing.

[0101] The base station fronthaul interface parsing processor provided by the present invention maps the data interface and the control interface to a general register group and uses hardware handshaking to complete data writing, thereby omitting the step of temporarily storing the message data in a cache in the traditional way, so that the data input to the processor can directly participate in the calculation, saving the time of reading the message data, optimizing the timing of message data parsing and simplifying the programming difficulty of parsing the instruction sequence.

[0102] Based on the above embodiment, as an optional embodiment, the block move control word includes a first initial cache address control word, a first data length control word, a register initial number control word and a register quantity control word;

[0103] The generating of the block move control word and the data recovery control word based on the message processing result includes: generating the first initial cache address control word, the first data length control word, the register initial number control word and the register quantity control word based on the message processing result;

[0104] The moving the message data from the register group module based on the block move control word and writing the message data into the cache comprises:

[0105] Based on the register initial number control word and the register quantity control word, determining a target register for carrying the message data from the register group module; the first register in the target register is the initial register corresponding to the register initial number control word;

[0106] Starting from the initial register in sequence, the message data is moved from the target register in a loop, and the message data is written into the storage space in the cache with the cache address corresponding to the first initial cache address control word as the initial cache address, until the length of the message data being moved is equal to the data length corresponding to the first data length control word.

[0107] Specifically, the block movement control words generated by the operation module for processing the U-plane message under the drive of the parsing instruction sequence include a first initial cache address control word rd, a first data length control word rs2, a register initial number control word rs1 and a register quantity control word range.

[0108] When the block transfer module transfers the message data based on the block transfer control word, it first determines the target register for transferring the message data from the register group module composed of multiple registers according to the register initial number control word rs1 and the register quantity control word range. Among them, the first register in the target register is the initial register, that is, the register corresponding to the register initial number control word rs1.

[0109] The number of target registers may be one or more, which is determined by the block movement control word specifically calculated by the operation module in a specific message data parsing task.

[0110] After configuring the block move module based on the block move control word, the block move module starts from the initial register, and moves the message data from the target register in a loop according to the number of the target register, and then stores the moved message data into the cache in sequence, using the cache address corresponding to the first initial cache address control word rd as the storage space with the initial cache address, until the length of the moved message data is equal to the data length corresponding to the first data length control word rs2.

[0111] The above process can be expressed in code form as the block movement instruction "Blks rd,rs1,rs2,range", where "Blks" represents block movement during message data parsing, and "rd", "rs1", "rs2" and "range" are all block movement control words generated after the operation module processes the message data.

[0112] Taking "Blks y10,x1,x4,3" as an example, the block moving module will cyclically read the message data from the three registers x1, x2 and x3 starting from register x1, and continuously write them to the storage address y10 in the cache, moving a total of z4 data. Assume that z4=7, that is, the block moving module reads the "x1, x2, x3, x1, x2, x3, x1" registers in turn when moving these 7 data, and the storage addresses of the 7 data cached in the cache are "x10, x10+1, x10+2, x10+3, x10+4, x10+5, x10+6" in turn.

[0113] Taking the O-RAN protocol as an example, the O-RAN protocol first defines the data format of the application layer data on the U (user) plane, followed by the compressed and tightly arranged IQ data (also known as IQ payload), which occupies the main body of the message and needs to be extracted when parsing the message. Due to the flexibility of the message, the starting address of the IQ payload in the message data has various possibilities, and because the payload in the message is large, using software loops to move it will result in excessive time overhead.

[0114] The base station fronthaul interface parsing processor provided by the present invention adopts a read-write dual loop method, cyclically reads message data from a target register, cyclically stores the read message data into a cache, and fixes the message data load block transport method based on a block transport module. Each time the message data load is transported, the block transport module can be started as a new task by configuring the block transport control word determined by the operation module. The fast transport of message data is realized with the help of hardware, and the execution logic of other parts of the base station fronthaul interface parsing processor is not affected, thereby improving the performance of the base station fronthaul interface parsing processor in parsing message data.

[0115] Based on the above embodiment, as an optional embodiment, the block move control word further includes a low byte number control word and a high byte number control word;

[0116] The method starts from the initial register in sequence, cyclically moves the message data from the target register, and writes the message data into a storage space in the cache with the cache address corresponding to the first initial cache address control word as the initial cache address, including:

[0117] Based on the low byte number control word, determining a first byte number;

[0118] Determining a second byte number based on the high byte number control word;

[0119] Starting from the initial register in sequence, the message data is transferred from the target register in a loop, the low byte data of the first byte number in the message data transferred from the previous register is used as the high-order data, and the high byte data of the second byte number in the message data transferred from the next register is used as the low-order data;

[0120] Sequentially splicing the high-order data and the low-order data to obtain spliced ​​message data;

[0121] The spliced ​​message data is written into a storage space in the cache with the cache address corresponding to the first initial cache address control word as the initial cache address, until the length of the message data being transported is equal to the data length corresponding to the first data length control word.

[0122] Specifically, in order to solve the problem that the received message data cannot be aligned due to compression, the operation module processes the U-plane message under the drive of the parsing instruction sequence to generate a block movement control word that also includes a low byte control word lowbyte and a high byte control word highbyte.

[0123] When the block transfer module transfers the message data based on the block transfer control word, it first determines the first byte number according to the low byte number control word lowbyte, and determines the second byte number according to the high byte number control word highbyte. Then, starting from the initial register, it starts to read the message data from the target register in a loop according to the number of the target register.

[0124] Starting from the first message data read, for two message data read adjacently from the target register, the low byte data of the first byte number in the message data moved in the previous register is used as the high-order data, and the high byte data of the second byte number in the message data moved in the next register is used as the low-order data, and a high-order data and a low-order data are spliced ​​in sequence to obtain the spliced ​​message data.

[0125] The spliced ​​message data are sequentially stored in the cache with the cache address corresponding to the first initial cache address control word rd as the storage space of the initial cache address until the length of the message data being transported is equal to the data length corresponding to the first data length control word rs2. In this process, the splicing of rs2 spliced ​​message data is completed.

[0126] The above process can be expressed in code form as the non-aligned block move instruction "Blksna rd,rs1(lowbyte,highbyte),rs2", where "Blksna" represents the non-aligned block move in the message data parsing process, and "rd", "rs1", "rs2", "lowbyte", and "highbyte" are all block move control words generated after the operation module processes the message data.

[0127] Figure 4 is an example diagram of alignment message data provided by the present invention, such as Figure 4 As shown, the block transfer module continuously reads message data from the interface register rs1, takes the low byte data "d0_low" of the first byte number in the first message data transferred in the previous register as the high-order data, and takes the high byte data "d0_hi" of the second byte number in the second message data transferred in the next register as the low-order data, and obtains the spliced ​​message data "d0_low+d0_hi", and the spliced ​​message data "d0_low+d0_hi" will be stored in the storage address rd position in the cache. Similarly, the spliced ​​spliced ​​message data "d1_low+d1_hi" will be stored in the storage address rd+1 position in the cache.

[0128] Since the received message data is compressed and has misaligned boundaries, that is, the boundaries of the payload in the message data are not 64-bit aligned, when network message data are all stored in big-endian and general registers are all in little-endian machines, using the traditional general-purpose processor's DMA to perform data movement operations cannot support the alignment of message data with misaligned big-endian storage boundaries.

[0129] The base station fronthaul interface parsing processor provided by the present invention adopts an aligned transport method of non-aligned message data with fixed boundaries based on a block transfer module. Each time the payload of the message data is transported, a low-byte control word and a high-byte control word are generated by a calculation module. The block transfer module is configured by all control words, and data can be spliced ​​front and back with the help of hardware, and written into the cache in an address-aligned manner, thereby supporting automatic alignment of message data boundaries when the big-endian storage boundaries are not aligned.

[0130] Based on the above embodiment, as an optional embodiment, the data recovery control word includes a second initial cache address control word, a second data length control word, a register number control word, a compression bit width control word and a compression method control word;

[0131] The step of loading the message data from the cache based on the data recovery control word, recovering the data bit width and size of the message data, and sending the recovered message data includes:

[0132] The message data is sequentially loaded from the storage space in the cache with the cache address corresponding to the second initial cache address control word as the initial cache address, and the data bit width and size of the message data are restored according to the compression bit width corresponding to the compression bit width control word and the compression method corresponding to the compression method control word, and the restored message data is sent to the register corresponding to the register number control word in the register group module until the length of the loaded message data is equal to the data length corresponding to the second data length control word.

[0133] The compression methods include but are not limited to μ-law, a-law, BFP (block floating point), block scaling and the like; the compression bit width is 7-15 bits.

[0134] Specifically, the data recovery control words generated by the operation module when processing the U-plane message under the drive of the parsing instruction sequence specifically include the second initial cache address control word rs1, the second data length control word rs2, the register number control word rd, the compression bit width control word compwidth and the compression method control word compmethod.

[0135] After configuring the data recovery module based on the data recovery control word, the data recovery module loads the message data in sequence from the cache using the cache address corresponding to the second initial cache address control word rs1 as the storage space of the initial cache address, recovers the data bit width and size of the message data according to the compression bit width corresponding to the compression bit width control word compwidth and the compression method corresponding to the compression method control word compmethod, and then sends the recovered message data to the register corresponding to the register number control word rd in the register group module for sending, until the length of the loaded message data is equal to the data length corresponding to the second data length control word rs2.

[0136] Optionally, the process of restoring the message data to the original data bit width according to the compression bit width corresponding to the compression bit width control word compwidth is also called decoding, which can be implemented by an ASIC-based decoding accelerator; the process of restoring the message data to the original data size according to the compression method corresponding to the compression method control word compmethod is also called decompression, which can be implemented by an ASIC-based decompression accelerator. That is, the data recovery module includes two serial, ASIC-based decoding accelerators and decompression accelerators.

[0137] The above process can be expressed in code form as the data recovery module configuration instruction "Rcv rd,rs1,rs2,compwidth,compmethod", where "Rcv" represents data recovery during message data parsing, and "rd", "rs1", "rs2", "compwidth" and "compmethod" are all data recovery control words generated after the operation module processes the message data.

[0138] The base station fronthaul interface parsing processor provided by the present invention adopts a configurable ASIC to fix the decoding method and decompression method of the data bit width and size of the recovered message data. When parsing the message, the data recovery control word determined by the operation module is used to configure the data recovery module. The data recovery module can be started to accelerate the processing of the application layer message data. After the data recovery module is started, it will work in parallel with the processor without affecting the normal execution of the processor, thereby improving the rate of message data parsing.

[0139] Based on the above embodiment, as an optional embodiment, each special processing instruction in the special processing instruction set is configured with a calculation method of the special processing instruction, a bit starting position of two operands, a bit length and a bit number.

[0140] The calculation method includes but is not limited to any one of the methods such as the change method, the operation method and the arbitration method. The change method includes but is not limited to data replacement, insertion, etc.; the operation method includes but is not limited to bit domain data addition, subtraction, multiplication, and, or, XOR, etc.; the arbitration method includes but is not limited to bit domain precise branching with comparison conditions of equal, not equal, greater than, less than or equal to, etc.

[0141] Correspondingly, the types of special processing instructions include data change instructions, bit operation instructions or bit arbitration instructions.

[0142] Taking the special processing instruction as a bit operation instruction as an example, each bit operation instruction includes an operation method (i.e., a calculation method), a first operand rs1, a second operand rs2 and a target address rd; the first operand rs1 includes a first bit starting position d, a first bit length e and a first bit number f; the second operand rs2 includes a second bit starting position g, a second bit length h and a second bit number i.

[0143] Accordingly, when executing the bit operation instruction, the operation module will fixedly obtain the first bit data of the first bit length e from the first bit starting position d in the register corresponding to the first operand rs1, and shift the first bit data left by the first bit position f, and the first bit data after the left shift is number 1; at the same time, fixedly obtain the second bit data of the second bit length h from the second bit starting position g in the register corresponding to the second operand rs2, and shift the second bit data left by the second bit position i, and the second bit data after the left shift is number 2. The operation module further operates on number 1 and number 2 according to the operation method, and stores them in the target address rd, thereby completing the operation of the message data.

[0144] Taking addition as an example, the above process is presented in code form, which can be expressed as a bit-domain precise addition instruction "Bpadd rd,rs1[d,e,f],rs2[g,h,i]", where "Bpadd" means precise addition of the bit-domains of two data.

[0145] For example, when the bit-domain precise addition instruction is "Bpadd n2,n0[8,12,0],n1[4,4,12]", the operation module intercepts bits [19:8] from the n0 register, shifts left by 0 bits, and obtains the number 1; intercepts bits [7:4] from the n1 register, shifts left by 12 bits, and obtains the number 2; and adds the numbers 1 and 2 to complete the bit-domain precise addition of the message data.

[0146] Figure 5 is a schematic diagram of the structure of the operation module provided by the present invention, such as Figure 5As shown, the operation module includes a first masker 511 , a second masker 512 , a first shifter 521 , a second shifter 522 and an operator 530 .

[0147] The first masker 511 is used to perform a mask operation on one of the operands using a first mask to obtain a first mask result; the first mask is determined based on the bit starting position and bit length of the one operand.

[0148] The second masker 512 is used to perform a mask operation on another operand using a second mask to obtain a second mask result; the second mask is determined based on the bit starting position and bit length of the other operand.

[0149] The first shifter 521 is used to shift the first mask result based on the bit number of the first operand to obtain a first shift result.

[0150] The second shifter 522 is used to shift the second mask result based on the bit number of the other operand to obtain a second shift result.

[0151] The operator 530 is used to perform an operation on the first shift result and the second shift result based on the calculation method to obtain an operation result and complete the execution of the dedicated processing instruction.

[0152] Specifically, taking the special processing instruction as a bit operation instruction as an example, the first masker 511 in the operation module first determines the first mask based on the first bit starting position and the first bit length, and then uses the first mask to perform a mask operation on the first bit data to obtain a first mask result; the second masker 512 first determines the second mask based on the second bit starting position and the second bit length, and then uses the second mask to perform a mask operation on the second bit data to obtain a second mask result.

[0153] The first shifter 521 then performs a left shift operation on the first mask result according to the first bit number to obtain a first shift result; the second shifter 522 then performs a left shift operation on the second mask result according to the second bit number to obtain a second shift result.

[0154] The operator 530 operates on the first shift result and the second shift result according to the operation method in the current execution instruction (such as addition, subtraction, multiplication, AND, OR, XOR, etc.), and writes the obtained operation result to the second target address, thereby completing the execution of the current execution instruction.

[0155] The base station fronthaul interface parsing processor provided by the present invention considers the commonality of operations performed by the operation module when adding, subtracting, multiplying, ANDing, ORing, and XORing message data in the process of implementing message data parsing, fixes the way in which the operation module operates on two bit fields, thereby accelerating the operation speed and allowing the operation module to simultaneously complete accurate data interception and operation; and the processing of these execution instructions by the operation module has been fixed by setting two maskers, two shifters and an operator in the operation module in a hardware manner. When facing high-throughput message data processing, it can greatly reduce programming costs and time, while reducing the instruction overhead and clock overhead of the processor, thereby greatly improving the processing speed of the message data.

[0156] Figure 6 This is a second structural diagram of the base station fronthaul interface parsing processor provided by the present invention, such as Figure 6 As shown, the base station fronthaul interface parsing processor also includes: a fast table lookup module 601, which is used to determine the header processing result based on the simultaneous matching result of the header and each key value record group; the fast table lookup module 601 stores a plurality of key value record groups; each of the key value record groups includes a plurality of key value records;

[0157] The extracting the header of the message data from the register group module 101 and processing the header includes: extracting the header of the message data from the register group module 101, forwarding the header to the fast table lookup module 601, and receiving the header processing result returned by the fast table lookup module 601.

[0158] Specifically, the quick table lookup module 601 stores a number of key-value record groups, each of which includes a specific number of key-value records, and each key-value record includes a one-to-one corresponding comparison value (equivalent to "key") and a result value (equivalent to "value").

[0159] For example, the specific number may be set to 8, 16, etc., that is, each key-value record group includes 8 key-value records, or each key-value record group includes 16 key-value records.

[0160] There is a lot of information that needs to be arbitrated in the header of the message data, such as Ethernet type, message type field in eCPRI, C-plane message type, IQ address start offset, etc. Correspondingly, the one-to-one comparison value and result value included in each key value record are also determined according to the information that needs to be arbitrated in the header of these message data.

[0161] Specifically, after the operation module 102 extracts the header of the message data from the register group module 101, the header is forwarded to the fast table lookup module 601, and the fast table lookup module 601, driven by the parsing instruction, determines the current specific data segment from the header according to the relevant control word, and determines the current key value record group for comparison with the current specific data segment. Among them, the current specific data segment is any field corresponding to the protocol information such as the Ethernet type in the header, the message type field in eCPRI, the C-plane message type, and the IQ address start offset.

[0162] The quick table lookup module 601 further performs a matching comparison between the current specific data segment and the comparison values ​​of all the multiple key value records in the current key value record group to obtain a simultaneous matching result. If there is a matching result in which the current specific data segment has the same comparison value as any key value record, the result value corresponding to the comparison value is used as a candidate result value. Among them, the matching method between the current specific data segment and the comparison value of any key value record includes but is not limited to equal to, not equal to, greater than, greater than or equal to, less than, less than or equal to, etc., and the present invention does not limit this.

[0163] In the process of simultaneously matching the current specific data segment with the comparison values ​​of a specific number of key-value records in the current key-value record group, on the one hand, the current specific data segment may not match any key-value records in the current key-value record group, and the simultaneous matching result obtained at this time will not determine the candidate result value. On the other hand, the current specific data segment may match the comparison values ​​of more than one key-value record in the current key-value record group, and at this time, more than one candidate result value is obtained.

[0164] After all relevant table lookup parsing instructions are executed, the fast table lookup module 601 arbitrates all candidate result values ​​obtained in the simultaneous matching process, determines the target result value for identifying the protocol information of the message data from a number of candidate result values, and returns it as a header processing result to the operation module 102. The operation module 102 receives the header processing result and determines the message type of the message data based on the header processing result.

[0165] Optionally, the parsing instruction driving the fast table lookup module 601 includes table lookup control words such as a register number control word rs1, a bit address control word d, a bit quantity control word e, and a key value record group control word cond.

[0166] The quick table lookup module 601 determines the target register from the register group module 101 according to the register number control word rs1, determines the target bit address range according to the bit address control word d and the bit quantity control word e, extracts the message data in the target bit address range from the target register as the current specific data segment; and determines the current key value record group based on the key value record group control word cond.

[0167] The quick table lookup module 601 further compares the current specific data segment with the comparison values ​​of all the multiple key value records in the current key value record group to obtain a simultaneous matching result. If there is a matching result in which the current specific data segment has the same comparison value as any key value record, the result value corresponding to the comparison value is used as a candidate result value.

[0168] This process can be expressed in code form as a fast table lookup instruction "Case rs1[d,e],cond", where "Case" means fast table lookup, and "rs1", "d", "e", and "cond" are all table lookup control words.

[0169] Optionally, Figure 7 is a schematic diagram of the structure of the fast table lookup module provided by the present invention, such as Figure 7 As shown, the fast table lookup module includes but is not limited to a key value table module 701, a result table module 702, a matcher 703 and an arbitrator 704. The key value table module 701 is used to store a plurality of key value record groups. The matcher 703 is used to determine the current key value record group and the current specific data segment extracted from the register group module according to the table lookup control word of the parsing instruction. The matcher 703 is also used to simultaneously match the current data segment with the comparison values ​​of a specific number of key value records in the current key value record group, and use the result value corresponding to the successfully matched comparison value as a candidate result value. The arbitrator 704 is used to arbitrate the candidate result values ​​matched by the matcher 703 under a plurality of parsing instructions and determine the target result value. The result table module 702 is used to store the candidate result values ​​matched by the matcher 703 under a plurality of parsing instructions.

[0170] The base station fronthaul interface parsing processor provided by the present invention sets a fast table lookup module that implements a one-to-many table lookup method. The fast table lookup module compares specific data segments in the header with multiple key value records in the key value record group at the same time. When the header processing result is obtained, it is only necessary to use the relevant table lookup parsing instructions to drive the fast table lookup module, so that the fast table lookup module can be started as a new task, and the message information can be quickly determined with the help of special instruction hardware without affecting the execution logic of other processing units; and the fast table lookup module can increase the number of key values ​​for comparison driven by each table lookup instruction, thereby realizing simultaneous and rapid matching between message data and multiple comparison values ​​in multiple key value records, thereby improving the rate of obtaining header processing results in a manner that is low in cost and shortens the matching time, and improving the message data parsing performance from the link of determining the header type in a fast and simultaneous table lookup manner.

[0171] Based on the above embodiment, as an optional embodiment, combined with Figure 6As shown, the base station fronthaul interface analysis processor also includes a program control module 602, an instruction storage module 603, a decoder module 604 and a check module 605; the check module 605 includes a checksum module and a cyclic redundancy check module.

[0172] The program control module 602 is used to manage program counts and arbitrate program count change requests sent by various modules of the base station fronthaul interface analysis processor.

[0173] The instruction storage module 603 is used to store the parsed instruction sequence.

[0174] The decoder module 604 is used to decode the parsing instructions in the parsing instruction sequence and distribute the decoding results to the various modules of the base station fronthaul interface parsing processor to drive the various modules to work.

[0175] The checksum module is used to complete the checksum calculation of the message data.

[0176] The cyclic redundancy check module is used to complete the check calculation of the cyclic redundancy check sequence (Cyclic Redundancy Check, CRC) of the message data.

[0177] Specifically, the decoder module 604 decodes the parsed instructions stored in the instruction storage module 603 and distributes the decoding results to each module to drive each module to work.

[0178] After each module completes the work of parsing the instruction drive, it sends a program count change request to the program control module 602 for managing the program count, so that the program control module 602 can arbitrate the program count change request.

[0179] When parsing the message data, the check module is responsible for the check calculation of CRC and checksum, so it includes a checksum module and a cyclic redundancy check module. The check module 605 is configured and started under the drive of the instruction, and does not affect the work of the base station front transmission interface parsing processor.

[0180] The parsing instruction for starting the checksum includes a register number rs1, which is used to obtain the checksum from the register corresponding to the register number rs1.

[0181] The parsing instruction for ending the checksum verification includes the register number rs1 and the cache address rd, and is used to drive the checksum module to stop obtaining the checksum from the register corresponding to the register number rs1, and write the result of the checksum calculation to the cache address rd.

[0182] The parsing instruction for starting the CRC check includes the register number rs1 and the bit width width, which is used to configure the bit width of CRC to be width, and the CRC data is obtained from the register corresponding to the register number rs1.

[0183] The parsing instruction for ending the CRC check includes the register number rs1 and the cache address rd, and is used to drive the cyclic redundancy check module to stop obtaining CRC data from the register corresponding to the register number rs1, and write the result of the check calculation to the cache address rd.

[0184] The base station fronthaul interface parsing processor provided by the present invention sets a verification module based on ASIC to accelerate the IP layer and the link layer. The verification module is configured, started and works according to instructions without affecting the normal operation of other modules of the processor.

[0185] As an optional embodiment, the base station fronthaul interface parsing processor also includes a block channel processing module and a slow channel processing module.

[0186] The fast channel processing module is used to accelerate the parsing process of the message data to obtain the payload data in the message data when determining that the message data is a data packet or a control packet based on the protocol information.

[0187] The slow channel processing module is used to not perform accelerated parsing processing on the message data when it is determined that the message data is a management packet based on the protocol information.

[0188] Data packets, control packets, and management packets are distinguished through programming. Data packets and control packets will be unpacked and parsed at an accelerated pace to extract payload data. Management packets are handled by the upper-layer software protocol stack, which can give full play to the performance of the base station fronthaul interface parsing processor, reduce the processing pressure of the main processor, and reduce the programming difficulty when the protocol stack processing is very large.

[0189] On the whole, the base station fronthaul interface parsing processor provided by the present invention provides a hot-potato come-and-go stream processing architecture, including a program control module, an instruction storage module, a decoder module, a block movement module, a fast table lookup module, an operation module, a cache, a data recovery module, a register group module and a verification module, taking into account both efficiency and flexibility, and the data channel for unpacking and parsing implemented includes program-driven bit synchronization, data segment search, data segment extraction, multi-data segment linking, error checking parallel operation, long field error checking background decoding operation, case accelerated execution circuit, with an ASIP-based accelerated instruction set and architecture with flexible programmable capabilities, which accelerates message data processing with fast processing speed and high efficiency.

[0190] Figure 8is a flow chart of a message parsing method based on a base station fronthaul interface parsing processor provided by the present invention, such as Figure 8 As shown, the message parsing method includes but is not limited to steps 801 to 804.

[0191] Step 801: After responding to the data packet start signal, the control operation module extracts the header of the message data from the register group module under the drive of the parsing instruction sequence, processes the header, and determines the message type of the message data based on the header processing result.

[0192] The parsed instruction sequence is composed of a number of special processing instructions in a special processing instruction set.

[0193] The register group module is composed of a plurality of registers and is used to temporarily store the message data and the operation results of the operation module.

[0194] Step 802: When the message type is a U-plane message, the operation module is controlled to process the message data under the drive of the parsing instruction sequence, and generate a block move control word and a data recovery control word based on the message processing result.

[0195] Step 803: The control block moving module moves the message data from the register group module based on the block moving control word, and writes the message data into the cache.

[0196] Step 804: After responding to the timing transmission signal, the control data recovery module loads the message data from the cache based on the data recovery control word, recovers the data bit width and size of the message data, and sends the recovered message data until the transmission of one message data is completed.

[0197] It should be noted that the message parsing method provided by the present invention, when specifically executed, can be based on the base station fronthaul interface parsing processor described in any of the above embodiments, which will not be elaborated in this embodiment.

[0198] The message parsing method based on the base station fronthaul interface parsing processor provided by the present invention processes the message data under the drive of the parsing instruction sequence obtained by flexible programming based on the dedicated processing instruction set by the operation module, and generates the control word realizing the block moving function and the data recovery function, that is, the control word realizing the block moving function and the data recovery function in the processor is configured by ASIP, and a new architecture for ASIP and accelerator to cooperate in parsing message data is constructed in the processor, which has low cost and can improve the rate of special functions such as the block moving function and the data recovery function in the message data parsing process, thereby improving the processing speed of message data parsing and meeting the real-time requirements of message processing at the same time, and realizing a high-speed and large-throughput processor in the message data parsing scenario of the base station fronthaul interface; The memory group module loads the message data, and the data input to the processor can directly participate in the operation of the operation module without the need to store the message data in the cache first and then extract it from the cache by the operation module. This can save the time of reading the input message data, optimize the timing of message data parsing and simplify the programming difficulty of the parsing instruction sequence; by using a dedicated processing instruction set when pre-programming the parsing instruction sequence, the number of parsing instructions required to be programmed by the operator when parsing the message data can be reduced, the instruction overhead can be reduced and the message data parsing speed can be improved; when processing the U-plane message, the processed message data is temporarily stored in the cache and sent only after receiving the timing transmission signal, that is, the timing requirements of the 5G fronthaul interface and the wireless system are realized through the cache and the external control signal, and the network jitter is eliminated at the same time.

[0199] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0200] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0201] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A base station fronthaul interface analysis processor, characterized in that: include: A register group module composed of multiple registers, a calculation module, a block movement module, a data recovery module and a cache; The register group module is used to temporarily store message data and the calculation results of the calculation module; The operation module is used to extract the header of the message data from the register group module under the drive of the parsing instruction sequence after responding to the start signal of the data packet, process the header, and determine the message type of the message data based on the header processing result; the parsing instruction sequence is composed of a plurality of special processing instructions in the special processing instruction set; The operation module is further used for processing the message data under the drive of the parsing instruction sequence when the message type is a U-plane message, and generating a block move control word and a data recovery control word based on the message processing result; The block moving module is used to move the message data from the register group module based on the block moving control word, and write the message data into the cache; The data recovery module is used to load the message data from the cache based on the data recovery control word after responding to the timing transmission signal, restore the data bit width and size of the message data, and send the recovered message data until the transmission of one message data is completed.

2. The base station fronthaul interface analysis processor according to claim 1, characterized in that: The operation module is further used for processing the message data under the drive of the parsing instruction sequence when the message type is a C-plane message, and obtaining parameters for U-plane message parsing based on the message processing result; And / or, the operation module is further used to discard the message data when the message type is not a forward transmission message.

3. The base station fronthaul interface analysis processor according to claim 1, characterized in that: The register group module is mapped with a data input interface and a data output interface, the data input interface and the data output interface are externally connected to an Ethernet switch, and the register group module and the Ethernet switch complete data writing based on a hardware handshake method.

4. The base station fronthaul interface analysis processor according to claim 3, characterized in that: The block move control word includes a first initial cache address control word, a first data length control word, a register initial number control word and a register quantity control word; The generating of the block move control word and the data recovery control word based on the message processing result includes: generating the first initial cache address control word, the first data length control word, the register initial number control word and the register quantity control word based on the message processing result; The moving the message data from the register group module based on the block move control word and writing the message data into the cache comprises: Based on the register initial number control word and the register quantity control word, determining a target register for carrying the message data from the register group module; the first register in the target register is the initial register corresponding to the register initial number control word; Starting from the initial register in sequence, the message data is moved from the target register in a loop, and the message data is written into the storage space in the cache with the cache address corresponding to the first initial cache address control word as the initial cache address, until the length of the message data being moved is equal to the data length corresponding to the first data length control word.

5. The base station fronthaul interface analysis processor according to claim 4, characterized in that: The block move control word also includes a low byte number control word and a high byte number control word; The method starts from the initial register in sequence, cyclically moves the message data from the target register, and writes the message data into a storage space in the cache with the cache address corresponding to the first initial cache address control word as the initial cache address, including: Based on the low byte number control word, determining a first byte number; Determining a second byte number based on the high byte number control word; Starting from the initial register in sequence, the message data is transferred from the target register in a loop, the low byte data of the first byte number in the message data transferred from the previous register is used as the high-order data, and the high byte data of the second byte number in the message data transferred from the next register is used as the low-order data; Sequentially splicing the high-order data and the low-order data to obtain spliced ​​message data; The spliced ​​message data is written into a storage space in the cache with the cache address corresponding to the first initial cache address control word as the initial cache address, until the length of the message data being transported is equal to the data length corresponding to the first data length control word.

6. The base station fronthaul interface analysis processor according to claim 3, characterized in that: The data recovery control word includes a second initial cache address control word, a second data length control word, a register number control word, a compression bit width control word and a compression method control word; The step of loading the message data from the cache based on the data recovery control word, recovering the data bit width and size of the message data, and sending the recovered message data includes: The message data is sequentially loaded from the storage space in the cache with the cache address corresponding to the second initial cache address control word as the initial cache address, and the data bit width and size of the message data are restored according to the compression bit width corresponding to the compression bit width control word and the compression method corresponding to the compression method control word, and the restored message data is sent to the register corresponding to the register number control word in the register group module until the length of the loaded message data is equal to the data length corresponding to the second data length control word.

7. The base station fronthaul interface analysis processor according to claim 1, characterized in that: Each special processing instruction in the special processing instruction set is configured with a calculation method of the special processing instruction, a bit starting position of two operands, a bit length and a bit number; The operation module comprises: a first masker, a second masker, a first shifter, a second shifter and an operator; The first masker is used to perform a mask operation on one of the operands using a first mask to obtain a first mask result; the first mask is determined based on a bit starting position and a bit length of the one operand; The second masker is used to perform a mask operation on another operand using a second mask to obtain a second mask result; the second mask is determined based on a bit starting position and a bit length of the other operand; The first shifter is used to shift the first mask result based on the number of bits of the first operand to obtain a first shift result; The second shifter is used to shift the second mask result based on the number of bits of the other operand to obtain a second shift result; The operator is used to operate the first shift result and the second shift result based on the calculation method to obtain the operation result and complete the execution of the dedicated processing instruction.

8. The base station fronthaul interface analysis processor according to claim 1, characterized in that: Also includes: A fast table lookup module, used to determine the header processing result based on the simultaneous matching result of the header and each key value record group; The quick table lookup module stores a number of key value record groups; Each of the key-value record groups includes a plurality of key-value records; The extracting the header of the message data from the register group module and processing the header includes: extracting the header of the message data from the register group module, forwarding the header to the fast table lookup module, and receiving the header processing result returned by the fast table lookup module.

9. The base station fronthaul interface analysis processor according to claim 1, characterized in that: Also includes: A program control module, an instruction storage module, a decoder module and a check module; the check module includes a checksum module and a cyclic redundancy check module; The program control module is used to manage program counts and arbitrate program count change requests sent by various modules of the base station fronthaul interface analysis processor; The instruction storage module is used to store the parsed instruction sequence; The decoder module is used to decode the parsing instructions in the parsing instruction sequence and distribute the decoding results to the various modules of the base station front transmission interface parsing processor to drive the various modules to work; The checksum module is used to complete the checksum calculation of the message data; The cyclic redundancy check module is used to complete the verification calculation of the cyclic redundancy check sequence of the message data.

10. A message parsing method based on the base station fronthaul interface parsing processor according to any one of claims 1 to 9, characterized in that: include: After responding to the start signal of the data packet, the control operation module extracts the header of the message data from the register group module under the drive of the parsing instruction sequence, processes the header, and determines the message type of the message data based on the header processing result; the parsing instruction sequence is composed of a plurality of special processing instructions in a special processing instruction set; the register group module is composed of a plurality of registers, which are used to temporarily store the message data and the operation result of the operation module; Controlling the operation module to process the message data under the drive of the parsing instruction sequence when the message type is a U-plane message, and generating a block move control word and a data recovery control word based on the message processing result; The control block moving module moves the message data from the register group module based on the block moving control word, and writes the message data into the cache; After responding to the timing transmission signal, the control data recovery module loads the message data from the cache based on the data recovery control word, recovers the data bit width and size of the message data, and sends the recovered message data until the transmission of one message data is completed.

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