FlexRay node driving circuit based on TJA1080

Abstract

The invention discloses a FlexRay node driving circuit based on TJA1080 in the technical field of bus communication. The FlexRay node driving circuit comprises an MCU (Microprogrammed Control Unit) chip, an FPGA (Field Programmable Gate Array) chip, a TJA1080 chip, a power supply module and a voltage drop module, the MCU chip, the FPGA chip and the TJA1080 chip are sequentially in communication connection, the power supply module is connected to the MCU chip through the voltage drop module, and the FPGA chip and the TJA1080 chip are used for supplying power to the chip; the FPGA chip comprises a multimedia module MAC, a data processing module DP, a sending module TX, a receiving module RX and a clock synchronization module TCU; according to the invention, the FPGA is used, and the FlexRay communication of a plurality of nodes can be realized by one FPGA as long as logic resources are sufficient; and compared with the traditional MFR4310, the use cost of the chip is reduced, and the system stability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of bus communication, and in particular to a FlexRay node driving circuit based on TJA1080. Background Art

[0002] Today, there are more and more automotive electronic devices. The early CAN communication rate was 125Kbps~1Mbps, and the CAN bus can no longer solve the communication between many electronic devices. The FlexRay bus is a new generation of serial synchronous and asynchronous communication system. The bus is fault-tolerant and can provide a definite data transmission rate of 500kbps~10Mbps and a 24-bit CRC (cyclic redundancy) check code. Its communication rate meets the needs of today's automotive electronic devices. The FlexRay bus provides flexible configuration and can support various topologies such as bus, star and hybrid. It uses two independent lines for communication, and the transmission rate of each line is up to 10Mbps. It provides message redundant transmission and non-redundant transmission. The system can be optimized to double the throughput.

[0003] TJA1080 is a high-performance FlexRay transceiver that supports FlexRay node and active star structure functions, with a data transmission speed of up to 10Mbit / s. In addition, the chip also has features such as ECU low power management, local and remote wake-up functions, and data frame wake-up, which can meet the various needs of the internal communication system of the car.

[0004] MFR4310 is a controller chip circuit compatible with the FlexRay bus protocol, and the communication protocol is compatible with FlexRayCommunications System Protocol Specification V2.1A. MFR4310 has two channels A and B, which can perform single-channel or dual-channel transmission. When performing single-channel transmission, the FR_A_TXEN signal is enabled, and the flexray protocol module sends the FR_A_TXD signal to the TXD port of the TJA1080, and then sends a signal to the MFR4310 through RXD to indicate that the data has been received and the conversion has begun. The MFR4310 controls up to two TJA1080s. Multiple MFR4310s are required for FlexRay dual-node or multi-node communication, which will increase costs and reduce circuit stability. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a FlexRay node driving circuit based on TJA1080 to solve the technical problem that the existing MFR4310 chip cannot meet the FlexRay dual-node or multi-node communication requirements.

[0006] To achieve the above object, the present invention is implemented by adopting the following technical solutions: The present invention provides a TJA1080-based FlexRay node driving circuit, comprising an MCU chip, an FPGA chip, a TJA1080 chip, a power module and a voltage drop module; the MCU chip, the FPGA chip and the TJA1080 chip are communicatively connected in sequence, and the power module is connected to the MCU chip, the FPGA chip and the TJA1080 chip via the voltage drop module for chip power supply.

[0007] Optionally, the FPGA chip includes a multimedia module MAC, a data processing module DP, a sending module TX, a receiving module RX and a clock synchronization module TCU; The multimedia module MAC includes a counting module, a MAC state machine and a data transmission control module, wherein the counting module is used to count the communication cycle, the data transmission control module is used to generate a control signal and encapsulate the data frame, and the MAC state machine is used to generate an enable signal of the transmission module TX and the receiving module RX and a control signal of the data processing module DP and the clock synchronization module TCU to achieve overall control; The sending module TX includes a Tx state machine, a shift register, a CRC check module and a serial output module; the Tx state machine encodes the output data of the multimedia module MAC, the shift register sends the output data of the multimedia module MAC to the FlexRay bus through the serial output module, and the CRC check module is used to check whether the output data of the multimedia module MAC is valid; The receiving module RX includes a filtering module, a frame decoding module, a second CRC checking module and a second shift register, and is used for filtering, decoding, checking validity and sending data received from the FlexRay bus; The data processing module DP includes a DP state machine and a receiving frame checking module. The DP state machine is used to receive an external clock signal and perform synchronization processing. The receiving frame checking module is used to check whether the data content is valid. If valid, it is written into the RAM and a clock signal is generated and sent to the clock synchronization module TCU. The clock synchronization module TCU includes a clock synchronization module TC and a beat counting module CNT. The beat counting module CNT is used to count the communication cycle and beat and send them to the MAC state machine and the data processing module DP; the clock synchronization module TC measures the clock error and adjusts the measured error by increasing or decreasing the beat to ensure that the clock cycles of the two nodes are synchronized when the next communication cycle arrives.

[0008] Optionally, a filter capacitor is pulled down at the connection end between the voltage drop module and the TJA1080 chip.

[0009] Optionally, the enable input pin EN, the bus protection enable pin BGE and the standby input pin STBN of the TJA1080 chip are all pulled high.

[0010] Optionally, the MCU chip and the FPGA chip perform 12-bit address addressing and 16-bit data reading and writing through the address bus and the data bus, and perform communication control through chip enable CE, write enable WE and output enable OE.

[0011] Optionally, the MCU chip has a built-in USART transceiver for communicating with a host computer.

[0012] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a FlexRay node driving circuit based on TJA1080, which uses a programmable logic device FPGA to replace MFR4310 as a FlexRay communication controller. As long as the logic resources of FPGA are sufficient, one FPGA can realize FlexRay communication of multiple nodes, thereby reducing the number of chips used, reducing costs and improving system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a circuit diagram of a FlexRay node driving circuit based on TJA1080 provided in an embodiment of the present invention; Figure 2 It is a schematic diagram of the connection between the FPGA chip and the TJA1080 chip provided in an embodiment of the present invention; Figure 3 is a structural diagram of a multimedia module MAC provided by an embodiment of the present invention; Figure 4 is a structural diagram of a data processing module DP provided in an embodiment of the present invention; Figure 5 is a structural diagram of a sending module TX provided in an embodiment of the present invention; Figure 6 is a structural diagram of a receiving module RX provided in an embodiment of the present invention; Figure 7 is a structural diagram of a clock synchronization module TCU provided in an embodiment of the present invention; Figure 8 It is a structural diagram of the TJA1080 chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0015] Embodiment 1:

[0016] like Figure 1 As shown, the present invention provides a FlexRay node driving circuit based on TJA1080, including an MCU chip, an FPGA chip, a TJA1080 chip, a power module and a voltage drop module; the MCU chip, the FPGA chip and the TJA1080 chip are communicatively connected in sequence, and the power module is connected to the MCU chip, the FPGA chip and the TJA1080 chip via the voltage drop module for chip power supply.

[0017] The MCU chip is STM32F427, whose working voltage is 12V; the FPGA chip is XC7Z010, whose working voltage is 3.3V; the working voltage of the TJA1080 chip is 5V; the system can be powered by a 12V power module, and the voltage conversion is performed through a 12-5V voltage drop module and a 5-3.3V voltage drop module. Furthermore, filters and protection circuits can be added to the power module to reduce the impact of power supply noise and overcurrent and overvoltage on the system. The frequency of FlexRay signal transmission is relatively high, which is easy to generate electromagnetic interference and cause errors in the transmission signal. Therefore, when powering the TJA1080 chip, a 100nF capacitor is connected in parallel to the ground to play a filtering role.

[0018] The enable input pin EN, bus protection enable pin BGE and standby input pin STBN of the TJA1080 chip are all pulled high to meet working requirements.

[0019] The address bus A[1:12] and data bus D[0:15] of STM32F427 and XC7Z010 are connected respectively for communication. The 12-bit address addressing and 16-bit read and write data of 427 are used. WE is used to control the direction of data interaction. When reading data, OE enables data output to the microcontroller. CE and A[12:1] are used to decode internal registers. The MCU chip has a built-in USART transceiver. The USART transceiver uses the CH340 chip. The CH340 chip converts the TTL level to the USB level to communicate with the host computer.

[0020] Using a programmable logic device FPGA chip instead of MFR4310 as a communication controller, as long as the logic resources are sufficient, one FPGA can realize FlexRay communication of multiple nodes. This example uses XC7Z010, which can control eight TJA1080s to realize FlexRay communication of four nodes.

[0021] In order to control the cost, this design uses FPGA to implement the functions of MFR4310. The FPGA chip includes a multimedia module MAC, a data processing module DP, a transmitting module TX, a receiving module RX, and a clock synchronization module TCU; Figure 2 As shown. The present invention makes full use of the rich logic resources of FPGA to design eight FlexRay transmission channels. Each submodule is instantiated in the top-level module, and the control signal and data transmitted by the single-chip microcomputer are converted and distributed to each channel, and then sent to the transceiver corresponding to each channel. After conversion, the FlexRay signal is sent to the bus, and finally the FlexRay communication of four nodes is realized. Compared with the existing control system, it has the characteristics of miniaturization, high flexibility and good openness.

[0022] like Figure 3 As shown, the multimedia module MAC includes a counting module, a MAC state machine and a data transmission control module. The counting module is used to count the communication cycle, the data transmission control module is used to generate a control signal and encapsulate the data frame, and the MAC state machine is used to generate an enable signal of the transmission module TX and the receiving module RX as well as a control signal of the data processing module DP and the clock synchronization module TCU to achieve overall control; In FlexRay node communication, the CPU sends data to the communication controller, the MAC state machine encapsulates the data frame, and then sends the data frame to the receiving module RX. The transmitting module TX encodes the data frame and sends it to the FlexRay bus. This node is called the sending node, and the node that receives the data is called the receiving node. The receiving node decodes the received data frame and sends it to the CPU or memory if it is a valid frame.

[0023] like Figure 4 As shown, the sending module TX includes a Tx state machine, a shift register, a CRC check module and a serial output module; the Tx state machine encodes the output data of the multimedia module MAC, the shift register sends the output data of the multimedia module MAC to the FlexRay bus through the serial output module, and the CRC check module is used to check whether the output data of the multimedia module MAC is valid.

[0024] like Figure 5 As shown, the receiving module RX includes a filtering module, a frame decoding module, a second CRC checking module and a second shift register, and is used to perform filtering processing, frame decoding processing, validity checking processing and sending processing on the data received from the FlexRay bus.

[0025] like Figure 6As shown, the data processing module DP includes a DP state machine and a receiving frame check module. The DP state machine is used to receive an external clock signal and perform synchronization processing. The receiving frame check module is used to check whether the data content is valid. If valid, it is written into the RAM and a clock signal is generated and sent to the clock synchronization module TCU.

[0026] like Figure 7 As shown, the clock synchronization module TCU includes a clock synchronization module TC and a beat counting module CNT. The beat counting module CNT is used to count the communication cycle and beat and send them to the MAC state machine and the data processing module DP; the clock synchronization module TC measures the clock error and adjusts the measured error by increasing or decreasing the beat to ensure that the clock cycles of the two nodes are synchronized when the next communication cycle arrives.

[0027] The structure diagram of TJA1080 chip is as follows Figure 8 As shown, the power supply voltage is 5 V and 12 V. After the input management module receives the signal, it converts it into an RXD signal through the state machine and sends it to the FlexRay controller, indicating that the signal has been received. At the same time, the received signal is converted and passed to the transmitter through the signal router to send BP and BM differential signals.

[0028] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A FlexRay node driving circuit based on TJA1080, characterized in that: It includes an MCU chip, an FPGA chip, a TJA1080 chip, a power module and a voltage drop module; the MCU chip, the FPGA chip and the TJA1080 chip are communicatively connected in sequence, and the power module is connected to the MCU chip, the FPGA chip and the TJA1080 chip via the voltage drop module for chip power supply.

2. The FlexRay node driving circuit based on TJA1080 according to claim 1, characterized in that: The FPGA chip includes a multimedia module MAC, a data processing module DP, a sending module TX, a receiving module RX and a clock synchronization module TCU; The multimedia module MAC includes a counting module, a MAC state machine and a data transmission control module, wherein the counting module is used to count the communication cycle, the data transmission control module is used to generate a control signal and encapsulate the data frame, and the MAC state machine is used to generate an enable signal of the transmission module TX and the receiving module RX and a control signal of the data processing module DP and the clock synchronization module TCU to achieve overall control; The sending module TX includes a Tx state machine, a shift register, a CRC check module and a serial output module; the Tx state machine encodes the output data of the multimedia module MAC, the shift register sends the output data of the multimedia module MAC to the FlexRay bus through the serial output module, and the CRC check module is used to check whether the output data of the multimedia module MAC is valid; The receiving module RX includes a filtering module, a frame decoding module, a second CRC checking module and a second shift register, and is used for filtering, decoding, checking validity and sending data received from the FlexRay bus; The data processing module DP includes a DP state machine and a receiving frame checking module. The DP state machine is used to receive an external clock signal and perform synchronization processing. The receiving frame checking module is used to check whether the data content is valid. If valid, it is written into the RAM and a clock signal is generated and sent to the clock synchronization module TCU. The clock synchronization module TCU includes a clock synchronization module TC and a beat counting module CNT. The beat counting module CNT is used to count the communication cycle and beat and send them to the MAC state machine and the data processing module DP; the clock synchronization module TC measures the clock error and adjusts the measured error by increasing or decreasing the beat to ensure that the clock cycles of the two nodes are synchronized when the next communication cycle arrives.

3. The FlexRay node driving circuit based on TJA1080 according to claim 1, characterized in that: A filter capacitor is pulled down at the connection end between the voltage drop module and the TJA1080 chip.

4. The FlexRay node driving circuit based on TJA1080 according to claim 1, characterized in that: The enable input pin EN, the bus protection enable pin BGE and the standby input pin STBN of the TJA1080 chip are all pulled high.

5. The FlexRay node driving circuit based on TJA1080 according to claim 1, characterized in that: The MCU chip and the FPGA chip perform 12-bit addressing and 16-bit data reading and writing through the address bus and the data bus, and perform communication control through the chip enable CE, write enable WE and output enable OE.

6. The FlexRay node driving circuit based on TJA1080 according to claim 1, characterized in that: The MCU chip has a built-in USART transceiver for communicating with the host computer.

Images