Multi-channel NAND Flash data processing method and device

Abstract

The invention provides a multi-channel NAND Flash data processing method and device, and the method comprises the steps: receiving a writing instruction, and alternately writing corresponding first data into a first data block corresponding to each channel; if a CopyBackk instruction is received, for each channel, in the process of migrating all data written in the first data block corresponding to the channel to the second data block corresponding to the channel according to the CopyBackk instruction, alternately continuing to write respective corresponding second data into the first data blocks respectively corresponding to other channels, so as to migrate all data written in the first data block corresponding to the channel to the second data block corresponding to the channel; and the data to be written is completely written into the NAND Flash. In the mode, when one channel migrates all data written in the first data block to the corresponding second data block, other channels alternately perform data writing operation, so that the data migration time is fully utilized, and the data writing speed is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a multi-channel NAND Flash data processing method and device. Background Art

[0002] In the related art, in order to improve the data storage speed of NAND Flash multi-CE (channel), a common method is to write two CEs alternately. When data needs to be written into NAND Flash, the controller will select a CE for the write operation. After sending the write operation command to NAND Flash, the write operation to NAND Flash begins. At this time, the RB time (response time of the Ready / Busy pin) will be waited for the next write operation; during this waiting time, the controller can select another CE for the write operation, thereby hiding this RB time and improving the data writing speed. However, in order to control costs, the prior art has a relatively small RAM on the T card master, and cannot directly perform TLC (Trinary-Level Cell, each cell can store 3 bits of data) or QLC (Quad-Level Cell, each cell can store 4 bits of data) writing, but needs to be written through SLC (Single-Level Cell, each cell can store 1 bit of data), and then the data is moved to the TLC / QLC block through the CopyBack method. However, the CopyBack process takes a long time, resulting in a decrease in the data writing speed. Summary of the invention

[0003] The object of the present invention is to provide a multi-channel NAND Flash data processing method and device to improve the data writing speed.

[0004] The present invention provides a data processing method for a multi-channel NAND Flash, wherein each channel has a storage block unit corresponding to the channel; each storage block unit includes a plurality of first data blocks and a plurality of second data blocks; the method comprises: receiving a write instruction for data to be written, and alternately writing the first data corresponding to each channel into the first data block corresponding to each channel; if a CopyBack instruction is received, for each channel, while all the data written in the first data block corresponding to the channel is migrated to the second data block corresponding to the channel according to the CopyBack instruction, alternately continuing to write the second data corresponding to each other channel into the first data block corresponding to each other channel until all the data to be written are written into the NAND Flash; wherein the CopyBack instruction is used to instruct the migration of the data in the first data block corresponding to each channel to the corresponding second data block; the first data and the second data are both at least a part of the data to be written.

[0005] Furthermore, after the step of alternately writing the first data corresponding to each channel into the first data blocks respectively corresponding to each channel, the method further includes: when the number of first data blocks corresponding to each channel into which the first data is written reaches a first preset number, triggering generation of a CopyBack instruction.

[0006] Further, for each other channel, the second data written into the first data block corresponding to the channel occupies a second preset number of data pages.

[0007] Furthermore, the second preset number is determined in the following manner: obtaining the channel number of multiple channels, the number of CopyBack times corresponding to the NAND Flash, and the number of data pages in the second data block corresponding to the channel; dividing the number of data pages by the number of CopyBack times and the number of channels in sequence to obtain the second preset number.

[0008] Furthermore, the method also includes: for each channel, obtaining the number of migrations corresponding to the channel; wherein the number of migrations is: migrating all the data written in the first data block corresponding to the channel to the number of migrations corresponding to the second data block corresponding to the channel; when the number of migrations corresponding to each channel reaches the CopyBack number, determining that the CopyBack is completed; and repeating the steps of alternately writing the respective first data to the first data blocks corresponding to each channel until all the data to be written are written into the NAND Flash.

[0009] Furthermore, each storage unit of the first data block stores one bit of data; and each storage unit of the second data block stores multiple bits of data.

[0010] Furthermore, different NAND Flashes correspond to different CopyBack times.

[0011] The present invention provides a data processing device for a multi-channel NAND Flash, wherein each channel has a storage block unit corresponding to the channel; each storage block unit includes a plurality of first data blocks and a plurality of second data blocks; the device includes: a writing module, which is used to receive a writing instruction for data to be written, and alternately write the first data corresponding to each channel into the first data block corresponding to each channel; a migration module, which is used to, if a CopyBack instruction is received, for each channel, when all the data written in the first data block corresponding to the channel is migrated to the second data block corresponding to the channel according to the CopyBack instruction, alternately continue to write the second data corresponding to each other channel into the first data block corresponding to each channel until all the data to be written are written into the NAND Flash; wherein the CopyBack instruction is used to instruct the data in the first data block corresponding to each channel to be migrated to the corresponding second data block; wherein the first data and the second data are both at least a part of the data to be written.

[0012] An electronic device provided by the present invention includes a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement any of the above multi-channel NAND Flash data processing methods.

[0013] The present invention provides a machine-readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement any of the above-mentioned multi-channel NAND Flash data processing methods.

[0014] The data processing method and device of the multi-channel NAND Flash provided by the present invention receive a write instruction for data to be written, and alternately write the first data corresponding to each channel to the first data block corresponding to each channel; if a CopyBack instruction is received, for each channel, when all the data written in the first data block corresponding to the channel is migrated to the second data block corresponding to the channel according to the CopyBack instruction, the second data corresponding to each other channel is alternately continued to be written to the first data block corresponding to each other channel until all the data to be written is written to the NAND Flash; wherein the CopyBack instruction is used to indicate that the data in the first data block corresponding to each channel is migrated to the corresponding second data block; the first data and the second data are both at least a part of the data to be written. In this method, when a channel is in the process of migrating all the data written in the first data block to the corresponding second data block, other channels will alternately perform data write operations, which fully utilizes the time of data migration and improves the speed of data writing. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic diagram of a data processing method provided by an embodiment of the present invention;

[0017] Figure 2 A schematic diagram of a storage block unit provided by an embodiment of the present invention;

[0018] Figure 3 A flowchart of a multi-channel NAND Flash data processing method provided by an embodiment of the present invention;

[0019] Figure 4 A flowchart of another multi-channel NAND Flash data processing method provided by an embodiment of the present invention;

[0020] Figure 5 A schematic diagram of a data processing method provided by an embodiment of the present invention.

[0021] Figure 6 A schematic diagram of the structure of a multi-channel NAND Flash data processing device provided by an embodiment of the present invention;

[0022] Figure 7 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In the existing technology, in order to improve the data storage speed of NAND Flash multi-CE (Chip Enable, chip enable pin), a common method is to write two CEs alternately. This method can write more data at the same time through the parallel processing capability between CEs, making the data writing speed faster. Figure 1 The schematic diagram of a data processing method shown in FIG. 1 is a diagram of a data processing method. In the prior art, multiple CEs are mainly used to write alternately, and the RB time of SLC writing between CEs is hidden to increase the writing speed.

[0025] However, the existing technology has some problems in this field. First, in order to control costs, the RAM on the T card master is relatively small, and needs to be written through SLC, and then the data is moved to the TLC / QLC block through CopyBack. However, the CopyBack process takes a long time, which reduces the speed of data writing. Secondly, the existing technology only uses the SLC of two CEs to write alternately to hide the RB time, and does not fully utilize the performance potential of NAND Flash. Based on this, the embodiment of the present invention provides a multi-channel NAND Flash data processing method and device, which can be applied to applications that need to write data to NAND flash.

[0026] To facilitate understanding of this embodiment, first, a data processing method for a multi-channel NAND Flash disclosed in an embodiment of the present invention is introduced. In this method, NAND Flash may have multiple CEs, each CE corresponds to a channel, and each channel has a corresponding storage block unit; each storage block unit includes multiple first data blocks and multiple second data blocks; each storage unit of the first data block stores one bit of data; each storage unit of the second data block stores multiple bits of data; in actual implementation, the first data block may be an SLC, and each storage unit of the SLC can only write 1 bit of data; the second data block may be a TLC or QLC, and each storage unit of the TLC can write 3 bits of data, and each storage unit of the QLC can write 4 bits of data. For example, Figure 2 Schematic diagram of a storage block unit shown in FIG. 1 , the storage block unit includes a Tab block (occupying 5 SLC blocks), a Data block (occupying 16 SLC blocks) and a QLC block, wherein the Tab block is used to store mapping related tables (not used in this embodiment); the Data block is a data writing area; the QLC block is the final data storage area, which is moved from the Data block CopyBack; Figure 3 As shown, the method comprises the following steps:

[0027] Step S302, receiving a write instruction for the data to be written, and alternately writing the first data corresponding to each channel into the first data block corresponding to each channel;

[0028] The above-mentioned data to be written may be data that needs to be written into the NAND Flash. In actual implementation, after receiving a write instruction for the data to be written, each channel may be controlled to alternately write data of the first data block. For convenience of explanation, taking two channels as an example, when the data to be written needs to be written into the NAND Flash, the first channel may be selected first. After receiving the write instruction, a write operation is performed through the first channel to write the first data block corresponding to the first channel to the first data block corresponding to the first channel. The first data is a part of the data to be written. At this time, the RB time will be waited for the next write operation. During this waiting time, the second channel may be selected to perform a write operation. The first data corresponding to the channel is written into the first data block corresponding to the second channel. The first data is another part of the data to be written. Since it is written alternately, the first data written through each channel is usually different.

[0029] Step S304, if a CopyBack instruction is received, for each channel, while all the data written in the first data block corresponding to the channel is migrated to the second data block corresponding to the channel according to the CopyBack instruction, the second data corresponding to each of the other channels is alternately written into the first data block respectively corresponding to each other channel until all the data to be written is written into the NAND Flash; wherein the CopyBack instruction is used to instruct the migration of the data in the first data block corresponding to each channel to the corresponding second data block; the first data and the second data are both at least part of the data to be written.

[0030] In actual implementation, when the first data written into the first data block corresponding to each channel meets certain conditions, the CopyBack instruction can be triggered. After receiving the CopyBack instruction, all the data written into the first data block corresponding to each channel can be migrated to the second data block corresponding to the channel. Specifically, when one of the channels migrates all the data written into the first data block corresponding to the channel to the second data block corresponding to the channel, the data write operation can be continued for each other channel at the same time, that is, the second data is continued to be written alternately into the first data block corresponding to each other channel. For each channel, the amount of the second data written is usually smaller than the amount of the first data. The above process of alternately writing the corresponding first data into the first data block corresponding to each channel can be repeated until all the data to be written is written into the NAND Flash, that is, all is written into the second data block.

[0031] The data processing method of the multi-channel NAND Flash receives a write instruction for the data to be written, and alternately writes the first data corresponding to each channel into the first data block corresponding to each channel; if a CopyBack instruction is received, for each channel, when all the data written in the first data block corresponding to the channel is migrated to the second data block corresponding to the channel according to the CopyBack instruction, the second data corresponding to each other channel is alternately continued to be written into the first data block corresponding to each other channel until all the data to be written is written into the NAND Flash; wherein the CopyBack instruction is used to indicate that the data in the first data block corresponding to each channel is migrated to the corresponding second data block; the first data and the second data are both at least a part of the data to be written. In this method, when a channel is in the process of migrating all the data written in the first data block to the corresponding second data block, other channels will alternately perform data write operations, making full use of the time of data migration and improving the speed of data writing.

[0032] The embodiment of the present invention further provides another multi-channel NAND Flash data processing method, which is implemented on the basis of the method in the above embodiment. For the convenience of description, this embodiment takes two channels, CE0 and CE1, the first data block is SLC, and the second data block is QLC as an example for description. The method includes the following steps:

[0033] Step 1, receiving a write instruction for data to be written, and alternately writing the first data corresponding to each channel into the first data block corresponding to each channel;

[0034] Step 2: When the number of first data blocks written with the first data corresponding to each channel reaches a first preset number, triggering generation of a CopyBack instruction;

[0035] The above-mentioned first preset number can be set according to actual needs, for example, it can be 8, etc.; in actual implementation, the two channels first perform SLC writes alternately, and the number of SLC blocks written is counted each time the SLC blocks are changed. When the number of SLC blocks written reaches the first preset number, such as 8 blocks, a CopyBack instruction can be triggered to trigger the CopyBack migration from SLC to QLC.

[0036] Step three, if a CopyBack instruction is received, for each channel, while all the data written in the first data block corresponding to the channel is migrated to the second data block corresponding to the channel according to the CopyBack instruction, the second data corresponding to each other channel is alternately written into the first data block respectively corresponding to each other channel until all the data to be written are written into the NAND Flash; wherein the CopyBack instruction is used to instruct the migration of the data in the first data block corresponding to each channel to the corresponding second data block; the first data and the second data are both at least part of the data to be written.

[0037] For each of the other channels, the second data written into the first data block corresponding to the channel occupies a second preset number of data pages. The second preset number is determined by following steps 30 to 31:

[0038] Step 30, obtaining the channel numbers of the multiple channels, the number of CopyBacks corresponding to the NAND Flash, and the number of data pages in the second data block corresponding to the channel;

[0039] In actual implementation, the number of CopyBacks corresponding to different NAND Flashes is usually different, which is mainly determined by the CopyBack characteristics of NAND Flash. For example, the Order number of some common NAND Flashes (corresponding to the above-mentioned CopyBack number) can be 2400 times, 448 times, 512 times, 1408 times, etc. The number of data pages can be specifically determined according to the number of pages contained in each second data block and the number of second data blocks. When it is necessary to determine the above-mentioned second preset number, it is usually necessary to first obtain the channel number of the above-mentioned multiple channels, the number of CopyBacks corresponding to the NAND Flash, and the number of data pages in the second data block corresponding to a single channel; usually, the number of data pages in the second data block corresponding to different channels is the same.

[0040] Step 31, divide the number of data pages by the number of CopyBacks and the number of channels in sequence to obtain a second preset number.

[0041] Specifically, the second preset number can be calculated according to the following formula:

[0042] The second preset number=the number of data pages of the QLC block / (the number of CopyBack times×the number of channels).

[0043] Considering that the number of SLC blocks is limited in actual applications, calculating the second preset number according to the formula can ensure the balance of the SLC and avoid the situation where the SLC is full and cannot be written any more.

[0044] For example, the second preset number calculated according to the above formula is 7; when CE0 is performing the CopyBack operation, it starts to perform the data writing operation on CE1 at the same time, and writes 7 pages continuously, that is, writes 7 pages to the SLC of CE1; the CopyBack time of different NAND Flash models is different (here refers to the time it takes for the data written in the SLC to be migrated to the QLC once), and the number of pages written continuously is also different. For example, CopyBack takes 5ms, but writing a page only takes about 500ns, and it only takes 3.5ms to write 7 pages, so the duration of the two is usually different; then the CopyBack operation of CE1 is performed, and the data writing operation on CE0 is started at the same time, and 7 pages are written continuously, that is, 7 pages are written to the SLC of CE0; and the operation is repeated in this way.

[0045] Step 4: for each channel, obtain the migration times corresponding to the channel; wherein the migration times is: the migration times corresponding to migrating all data written in the first data block corresponding to the channel to the second data block corresponding to the channel;

[0046] Step 5: When the number of migrations corresponding to each channel reaches the number of CopyBacks, it is determined that the CopyBack is completed;

[0047] In actual implementation, it is usually necessary to count the number of migrations for each channel separately. When the number of migrations corresponding to each channel reaches the CopyBack number, such as 2400 times, the CopyBack can be considered completed.

[0048] Step six, repeatedly executing the step of alternately writing the first data corresponding to each channel into the first data block corresponding to each channel, until all the data to be written are written into the NAND Flash.

[0049] After it is determined that CopyBack is completed, the process of alternating writing of the SLCs of CE0 and CE1 can be continued, and the above steps are repeated until all the data to be written is written into the NAND Flash.

[0050] For easier understanding, see Figure 4The flowchart of another multi-channel NAND Flash data processing method shown in the figure, when receiving a write instruction, the data write operation starts to be executed, and CE0 and CE1 perform SLC write alternately; it is determined whether CopyBack is in progress, and if CopyBack is not in progress, the data write operation continues to be executed; if CopyBack is in progress, it is determined whether CopyBack is completed, and if CopyBack is completed, the data write operation continues to be executed, and if CopyBack is not completed, the CopyBack of CE0 is started first, and only the write operation is performed on CE1, such as writing 7 pages to the SLC corresponding to CE1, and then the CopyBack of CE1 is started, and only the write operation is performed on CE0, such as writing 7 pages to the SLC corresponding to CE0.

[0051] like Figure 5 The diagram shows a data processing method, which processes the CopyBack between CEs on the basis of hiding the RB time of SLC writing between CEs. When one CE is performing CopyBack, data is written to another CE at the same time, which can improve the data writing speed.

[0052] The above-mentioned multi-channel NAND Flash data processing method utilizes the parallel processing capability of multiple channels. When one of the channels is performing a CopyBack operation, data can be written to other channels at the same time, thereby reducing the RB time waiting for CopyBack. In this way, the parallel processing capability of the channels can be effectively utilized, the data writing speed is increased, and the data processing efficiency is further improved.

[0053] This method makes full use of the intermittent time of multi-channel CopyBack and improves the efficiency of data writing. For T cards, the main way to move data to TLC / QLC is CopyBack, so for those NAND Falsh that require a long time for CopyBack, the write speed will be significantly improved. The intermittent time of multi-channel CopyBack can be used to increase the NANDFlash data storage speed, thereby improving the efficiency of data writing.

[0054] Corresponding to the above method embodiment, the embodiment of the present invention provides a multi-channel NAND Flash data processing device, each channel has a corresponding storage block unit; each storage block unit includes a plurality of first data blocks and a plurality of second data blocks; Figure 6As shown, the device includes: a write module 60, which is used to receive write instructions for data to be written, and alternately write the first data corresponding to each channel into the first data block corresponding to each channel; a migration module 61, which is used to, if a CopyBack instruction is received, for each channel, when all the data written in the first data block corresponding to the channel is migrated to the second data block corresponding to the channel according to the CopyBack instruction, alternately continue to write the second data corresponding to each other channel into the first data block corresponding to each other channel until all the data to be written are written into the NAND Flash; wherein the CopyBack instruction is used to instruct the migration of the data in the first data block corresponding to each channel to the corresponding second data block; the first data and the second data are both at least part of the data to be written.

[0055] In the above multi-channel NAND Flash data processing method, when one channel is migrating all the data written in the first data block to the corresponding second data block, other channels will alternately perform data writing operations, thereby making full use of the data migration time and improving the data writing speed.

[0056] Furthermore, the device is also used to: trigger the generation of a CopyBack instruction when the number of first data blocks written with the first data corresponding to each channel reaches a first preset number.

[0057] Further, for each other channel, the second data written into the first data block corresponding to the channel occupies a second preset number of data pages.

[0058] Furthermore, the second preset number is determined in the following manner: obtaining the channel number of multiple channels, the number of CopyBack times corresponding to the NAND Flash, and the number of data pages in the second data block corresponding to the channel; dividing the number of data pages by the number of CopyBack times and the number of channels in sequence to obtain the second preset number.

[0059] Furthermore, the device is also used to: for each channel, obtain the number of migrations corresponding to the channel; wherein the number of migrations is: the number of migrations corresponding to migrating all data written in the first data block corresponding to the channel to the second data block corresponding to the channel; when the number of migrations corresponding to each channel reaches the CopyBack number, determine that the CopyBack is completed; repeat the steps of alternately writing the respective first data into the first data blocks corresponding to each channel until all the data to be written is written into the NAND Flash.

[0060] Furthermore, each storage unit of the first data block stores one bit of data; and each storage unit of the second data block stores multiple bits of data.

[0061] Furthermore, different NAND Flashes correspond to different CopyBack times.

[0062] The implementation principle and technical effects of the multi-channel NAND Flash data processing device provided in the embodiment of the present invention are the same as those of the aforementioned multi-channel NAND Flash data processing method embodiment. For the sake of brief description, for matters not mentioned in the embodiment of the multi-channel NAND Flash data processing device, reference may be made to the corresponding contents in the aforementioned multi-channel NAND Flash data processing method embodiment.

[0063] The embodiment of the present invention further provides an electronic device, see Figure 7 As shown, the electronic device includes a processor 130 and a memory 131, wherein the memory 131 stores machine executable instructions that can be executed by the processor 130, and the processor 130 executes the machine executable instructions to implement the above-mentioned multi-channel NAND Flash data processing method.

[0064] Further, Figure 7 The electronic device shown further includes a bus 132 and a communication interface 133 , and the processor 130 , the communication interface 133 and the memory 131 are connected via the bus 132 .

[0065] The memory 131 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk storage. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 133 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used. The bus 132 may be an ISA bus, a PCI bus, or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0066] The processor 130 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 130. The above processor 130 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present invention can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution. The software module may be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 131, and the processor 130 reads the information in the memory 131 and completes the steps of the method of the above embodiment in combination with its hardware.

[0067] An embodiment of the present invention further provides a machine-readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the above-mentioned multi-channel NAND Flash data processing method. The specific implementation can be found in the method embodiment, which will not be repeated here.

[0068] The computer program product of the multi-channel NAND Flash data processing method and device provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method described in the previous method embodiment. The specific implementation can be referred to the method embodiment, which will not be repeated here.

[0069] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-channel NAND Flash data processing method, characterized in that: Each channel has a corresponding storage block unit; each of the storage block units includes a plurality of first data blocks and a plurality of second data blocks; the method includes: receiving a write instruction for data to be written, and alternately writing the first data corresponding to each channel into the first data block corresponding to each channel; If a CopyBack instruction is received, for each channel, while all the data written in the first data block corresponding to the channel is migrated to the second data block corresponding to the channel according to the CopyBack instruction, the second data corresponding to each of the other channels is alternately written into the first data blocks respectively corresponding to each other channel until all the data to be written are written into the NAND Flash; wherein the CopyBack instruction is used to instruct the migration of the data in the first data block corresponding to each channel to the corresponding second data block; the first data and the second data are both at least part of the data to be written.

2. The method according to claim 1, characterized in that After the step of alternately writing the first data corresponding to each channel into the first data block corresponding to each channel, the method further includes: When the number of first data blocks written into the first data corresponding to each channel reaches a first preset number, the generation of a CopyBack instruction is triggered.

3. The method according to claim 1, characterized in that: For each other channel, the second data written into the first data block corresponding to the channel occupies a second preset number of data pages.

4. The method according to claim 3, characterized in that: The second preset number is determined in the following manner: Obtain the number of channels of the multiple channels, the number of CopyBacks corresponding to the NAND Flash, and the number of data pages in the second data block corresponding to the channel; The second preset number is obtained by dividing the number of data pages by the number of CopyBack times and the number of channels in sequence.

5. The method according to claim 1, characterized in that The method further comprises: For each channel, the number of migrations corresponding to the channel is obtained; wherein the number of migrations is: the number of migrations corresponding to migrating all data written in the first data block corresponding to the channel to the second data block corresponding to the channel; When the number of migrations corresponding to each channel reaches the number of CopyBacks, it is determined that the CopyBack is completed; Repeat the step of alternately writing the first data corresponding to each channel into the first data block corresponding to each channel until all the data to be written are written into the NAND Flash.

6. The method according to claim 1, characterized in that Each storage unit of the first data block stores one bit of data; each storage unit of the second data block stores multiple bits of data.

7. The method according to claim 1, characterized in that Different NAND Flashes have different corresponding CopyBack times.

8. A multi-channel NAND Flash data processing device, characterized in that: Each channel has a corresponding storage block unit; each of the storage block units includes a plurality of first data blocks and a plurality of second data blocks; the device includes: A writing module, used for receiving a writing instruction for data to be written, and alternately writing the first data corresponding to each channel into the first data block corresponding to each channel; A migration module, for if receiving a CopyBack instruction, for each channel, while migrating all the data written in the first data block corresponding to the channel to the second data block corresponding to the channel according to the CopyBack instruction, the migration module continues to write the respective corresponding second data to the first data blocks corresponding to each other channel alternately until all the data to be written are written into the NAND Flash; wherein the CopyBack instruction is used to instruct the migration of the data in the first data block corresponding to each channel to the corresponding second data block; the first data and the second data are both at least part of the data to be written.

9. An electronic device, characterized in that: The invention comprises a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement the multi-channel NAND Flash data processing method according to any one of claims 1 to 7.

10. A machine-readable storage medium, characterized in that: The machine-readable storage medium stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the multi-channel NAND Flash data processing method according to any one of claims 1 to 7.

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