Method for preparing graphene device and application thereof

Abstract

The invention discloses a method and a system for researching and preparing a graphene device on a 200mm CMOS (Complementary Metal-Oxide-Semiconductor Transistor) test line. The method comprises the following steps: growing wafer-level high-quality graphene on a material compatible with a CMOS (Complementary Metal Oxide Semiconductor), and epitaxially growing a Ge (001) layer on a Si (001) substrate by adopting a chemical vapor deposition (CVD) technology so as to utilize the catalytic activity and low-carbon solubility of Ge. In addition, graphene is transferred from a growth wafer (donor) to an isolation wafer (target wafer) through an electrochemical layering process, and low-defect and large-scale graphene transfer is realized.

Description

Technical Field

[0001] The present application relates to a method for preparing a graphene device, and in particular, to a method for preparing a graphene device on a 200 mm CMOS test line. Background Art

[0002] With the development of microelectronics technology, traditional silicon-based CMOS technology is facing a bottleneck in performance improvement. Graphene, as a new type of two-dimensional material, is considered to be an ideal choice to surpass silicon-based technology due to its excellent electronic, thermal and mechanical properties. However, integrating graphene into existing CMOS technology requires solving key technologies such as graphene growth, transfer, passivation and electrical contact. Technical Solution

[0003] In view of the technical problems existing in the prior art, the present invention proposes a method and system for studying and preparing graphene devices on a 200 mm CMOS test line. The method includes growing wafer-level high-quality graphene on CMOS-compatible materials, epitaxially growing a Ge(001) layer on a Si(001) substrate using chemical vapor deposition (CVD) technology to utilize the catalytic activity and low carbon solubility of Ge. In addition, the graphene is transferred from the growth wafer (donor) to an isolation wafer (target wafer) through an electrochemical layering process, achieving low-defect, large-scale graphene transfer.

[0004] The deposition of the passivation layer is accomplished by plasma enhanced chemical vapor deposition (PECVD) technology, using SiN as the passivation material to protect the graphene from the destructive effects of the environment and subsequent processing. In addition, the present invention also relates to a method for forming electrical contacts on graphene, including patterning and metal deposition steps, to achieve electrical performance testing of graphene-based devices.

[0005] The following is a detailed description of the technical solution of this application.

[0006] A method for preparing a graphene device on a 200 mm CMOS test line comprises the following steps: a. Growing wafer-scale high-quality graphene on CMOS-compatible materials; b. Depositing a reliable passivation layer on top of graphene; c. Complete graphene wafer processing on a standard SiCMOS pilot production line.

[0007] Furthermore, the CMOS-compatible material is germanium (Ge).

[0008] Furthermore, the growth of graphene adopts chemical vapor deposition (CVD) technology to epitaxially grow a Ge (001) layer on a Si (001) substrate.

[0009] Furthermore, the method includes the step of transferring the graphene from the growth wafer to the isolation wafer, wherein the transfer method adopts an electrochemical layering process.

[0010] Furthermore, the passivation layer is formed by a SiN layer through plasma enhanced chemical vapor deposition (PECVD).

[0011] Furthermore, the method comprises the step of forming electrical contacts on the graphene, wherein the contacts are achieved by patterning and metal deposition.

[0012] The present invention also provides a system for studying and preparing graphene devices on a 200 mm CMOS test line. The system includes a CVD device, a PECVD device, and standard SiCMOS test line equipment. The CVD device is used to epitaxially grow a Ge(001) layer on a Si(001) substrate to achieve the growth of high-quality graphene at the wafer level. The PECVD device is used to deposit a SiN passivation layer on top of the graphene to protect the graphene from destructive effects that may occur during subsequent processing. The standard SiCMOS test line equipment is used to complete the processing of the graphene wafer, including patterning and metal deposition to form electrical contacts.

[0013] The following is a detailed description of another technical solution of the present application.

[0014] A system for preparing graphene devices on a 200 mm CMOS pilot line, comprising: a) Chemical vapor deposition (CVD) equipment for growing wafer-scale high-quality graphene on CMOS-compatible materials; b) a plasma enhanced chemical vapor deposition (PECVD) apparatus for depositing a reliable passivation layer on top of the graphene; c) Standard SiCMOS pilot production line equipment used to complete graphene wafer processing.

[0015] Furthermore, the CVD apparatus is provided with equipment for epitaxially growing a Ge(001) layer on a Si(001) substrate.

[0016] Further, an electrochemical layering apparatus for transferring graphene from a growth wafer to an isolation wafer is included.

[0017] Further, the PECVD apparatus is configured with a setup for growing a SiN layer directly on graphene, and patterning and metal deposition equipment for forming electrical contacts on the graphene. Beneficial Effects

[0018] a) Graphene is grown on the Ge(001) layer using CVD technology, achieving wafer-level high-quality graphene growth compatible with CMOS processes, laying a foundation for the large-scale application of graphene.

[0019] b) Efficient transfer of graphene is achieved through the electrochemical layering process, which avoids the problem of metal cross-contamination and ensures the high quality and large-scale transfer of graphene.

[0020] c) Using PECVD technology to directly grow a SiN layer on graphene effectively protects the electronic properties of graphene and provides a guarantee for the subsequent processing and application of graphene.

[0021] d) Through patterning and metal deposition steps, efficient electrical contact between graphene and metal is achieved, which reduces the contact resistance and improves the electrical performance of graphene-based devices.

[0022] The method and system for studying and preparing graphene devices on a 200mm CMOS test line opens up new possibilities for the application of graphene in the field of microelectronics. By optimizing the growth, transfer, passivation and electrical contact process of graphene, the present invention not only improves the quality of graphene materials and the performance of devices, but also achieves compatibility with existing CMOS technology, providing key technical support for the commercial application and industrial production of graphene.

Claims

1. A method for preparing a graphene device on a 200 mm CMOS test line, comprising the following steps: a. Growing wafer-scale high-quality graphene on CMOS-compatible materials; b. Depositing a reliable passivation layer on top of graphene; c. Complete graphene wafer processing on a standard Si CMOS pilot production line.

2. The method according to claim 1, wherein the CMOS compatible material is germanium (Ge).

3. The method according to claim 1, wherein the graphene is grown by epitaxially growing a Ge(001) layer on a Si(001) substrate using chemical vapor deposition (CVD) technology.

4. The method according to claim 1 further comprises the step of transferring the graphene from the growth wafer to the isolation wafer, wherein the transfer method adopts an electrochemical layering process. The method according to claim 1 , wherein the passivation layer is formed of a SiN layer by plasma enhanced chemical vapor deposition (PECVD).

6. The method of claim 1, further comprising the step of forming electrical contacts on the graphene, the contacts being achieved by patterning and metal deposition.

7. A system for preparing graphene devices on a 200 mm CMOS test line, comprising: a) Chemical vapor deposition (CVD) equipment for growing wafer-scale high-quality graphene on CMOS-compatible materials; b) a plasma enhanced chemical vapor deposition (PECVD) apparatus for depositing a reliable passivation layer on top of the graphene; c) Standard SiCMOS pilot production line equipment used to complete graphene wafer processing.

8. The system of claim 7, wherein the CVD apparatus is configured with equipment for epitaxially growing a Ge(001) layer on a Si(001) substrate.

9. The system of claim 7, further comprising an electrochemical layering device for transferring graphene from the growth wafer to the isolation wafer.

10. The system of claim 7, wherein the PECVD apparatus is configured with a setup for growing a SiN layer directly on graphene, and patterning and metal deposition equipment for forming electrical contacts on the graphene.