Material suitable for chip bonding and coating method thereof

Abstract

The invention belongs to the technical field of chip materials, and particularly relates to a material suitable for chip bonding and a coating method thereof. The bonding material comprises one or more of In, Sn, Bi, Au and Sn, the material can greatly reduce stress caused by difference of thermal expansion coefficients of sapphire and silicon genes in a lower-temperature bonding environment, the bonding accuracy and success rate are improved, the material is harder in texture, and the service life of the material is prolonged. Therefore, the success rate of bonding is improved, and the existing problems are effectively solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip materials, and in particular relates to a material suitable for chip bonding and a coating method thereof. Background Art

[0002] Die bonding is a critical process step in semiconductor manufacturing that involves securing and connecting a die to a substrate to ensure a stable electrical and mechanical connection. This process typically involves placing the die in position and forming an effective connection between the die and substrate by applying pressure and heat or chemical methods.

[0003] The basic principle of chip bonding involves two main steps: first, placing the chip in the appropriate position, and then achieving an effective connection between the chips by applying pressure and heat or chemical methods. This process creates a fully functional integrated circuit. Common physical bonding techniques include solder ball bonding and gold wire bonding. The former uses tin solder balls and alloy materials and is suitable for high-density mounting, while gold wire bonding utilizes the ductility of metal materials and uses ultrasonic welding to solder gold wires to the chip surface. It is characterized by simple process and low cost.

[0004] Selecting the right bonding material is crucial to ensuring high-performance chips. Different materials have different physical and chemical properties. For example, metals such as aluminum, gold, and copper are commonly used to connect microelectronic devices and have good conductivity and mechanical strength. Polymers such as epoxy resins and polyimides are used to encapsulate and protect chips and have excellent insulation and corrosion resistance. Ceramic materials exhibit excellent thermal stability in high-temperature environments.

[0005] Existing bonding processes typically use gold-indium and gold-tin bonding. Indium has a low melting point, and gold and indium can form a eutectic at low temperatures. Tin, on the other hand, is a commonly used material in welding and has a relatively mature technical solution. However, due to the different thermal expansion coefficients of sapphire and silicon, and both exhibit a certain amount of warpage, the softer indium cannot withstand the stress caused by the thermal expansion coefficient and warpage, resulting in localized bond loss. Tin, on the other hand, has a higher melting point (232°C), and high temperatures exacerbate the thermal expansion difference between sapphire and silicon, thus affecting alignment accuracy. Summary of the Invention

[0006] In order to solve the above technical problems, the present invention proposes the use of a material suitable for chip bonding, which greatly reduces the stress caused by the difference in thermal expansion coefficients between sapphire and silicon genes in a lower temperature bonding environment, improves bonding accuracy and success rate, or improves resistance to stress, thereby improving the success rate of bonding, and a coating method for the material.

[0007] Specifically, a first aspect of the present invention provides a material suitable for chip bonding, wherein the material is composed of one or more of In, Sn, Bi, Au, and Sn.

[0008] In one embodiment, the material is In x Sn y Bi z , where 0≤x≤0.41, 0≤y≤0.8, 0≤z≤0.5.

[0009] In one embodiment, the material is In x Sn y Bi z , where 0≤x≤0.3, 0≤y≤0.6, 0≤z≤0.4.

[0010] In one embodiment, the material has a melting point of ≤ 100°C.

[0011] In one embodiment, the material is Au a Sn b , where 0≤a≤0.9, 0≤b≤0.6.

[0012] In one embodiment, the material is Au a Sn b , where 0≤a≤0.4, 0≤b≤0.6.

[0013] In one embodiment, the material has a melting point of 200-500°C.

[0014] A second aspect of the present invention is to provide a method for coating a material suitable for chip bonding, the method comprising the following steps:

[0015] (1) Clean and dry the surface of the CMOS driver substrate with the circuit engraved inside;

[0016] (2) coating photoresist on the CMOS driver substrate;

[0017] (3) exposing the coated portion of the CMOS driver substrate and removing the exposed photoresist;

[0018] (4) depositing a buffer layer material on the surface of the CMOS driver substrate in the form of a coating to form a buffer layer, and stripping off the remaining photoresist;

[0019] (5) Then, the photoresist is spin-coated, and the buffer layer is exposed through a photolithography process. The material suitable for chip bonding is deposited on the surface of the CMOS driver substrate in the form of a coating to form a metal electrode. The photoresist is removed, and the coating of the material suitable for chip bonding is completed.

[0020] In one embodiment, the buffer layer material in step (4) is any one or more of Cr, Ni, Ti, Pt, and Au. The coating process is to pre-melt the buffer layer material first, and then control the PID parameters to deposit the material atoms onto the surface of the CMOS driver substrate. The buffer layer thickness is 0 to 1.5 μm.

[0021] In one embodiment, the coating process in step (5) is to pre-melt the buffer layer material first, and then control the PID parameters to deposit the material atoms onto the surface of the CMOS driver substrate. The thickness of the metal electrode is 3 to 6 μm.

[0022] Beneficial effects:

[0023] The bonding material of the present invention can greatly reduce the stress caused by the difference in thermal expansion coefficients between sapphire and silicon in a lower temperature bonding environment, thereby improving bonding accuracy and success rate. In addition, the material has a harder texture, which improves its resistance to stress, thereby improving the success rate of bonding and effectively solving existing problems. DETAILED DESCRIPTION

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In the event of a conflict, the definitions in this specification shall prevail.

[0025] Unless otherwise indicated, all percentages, parts, ratios, etc. are by weight.

[0026] As used herein, the terms "comprises," "includes," "has," "having," "containing," or any other variations thereof, are intended to cover a non-exclusive inclusion. For example, a composition, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may also include other elements not expressly listed or inherent to such composition, process, method, article, or apparatus.

[0027] When quantity, weight part or other numerical value or parameter is given as range, preferred range or a series of upper preferred value and lower preferred value, it should be understood that it specifically discloses all ranges formed by any pair of numerical values ​​of any larger range limit or preferred value and any smaller range limit or preferred value, and no matter whether scope is disclosed respectively.For example, when describing the scope of "1 to 5", described scope should be understood as including the scope of "1 to 4", "1 to 3", "1 to 2", "1 to 2 and 4 to 5", "1 to 3 and 5" etc.Unless otherwise stated, when describing numerical range herein, described range is intended to include range end value and all integers, fractions, decimals etc. within the range.

[0028] In addition, the indefinite articles "a" and "an" before the elements or components of the present disclosure are intended to indicate that the number of occurrences (i.e., occurrences) of the elements or components is not limited. Therefore, "a" or "an" should be understood to include one or at least one, and unless it is clearly indicated that the number is singular, the elements or components in the singular also include plural cases.

[0029] Unless otherwise specified, the materials, methods, and examples described herein are illustrative only and not limiting. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure, suitable methods and materials are described herein.

[0030] The present disclosure is described in detail below.

[0031] PID parameters are standard parameters for PID controllers and typically include proportional (P), integral (I), and differential (D). The proportional parameter determines the system's response speed to deviations, the integral parameter is used to eliminate steady-state errors, and the differential parameter is used to predict the deviation's changing trend.

[0032] At the same time, the PID parameters affect the stability of the power during coating, the film coefficient affects the actual film thickness, and because metals have different effects on the crystal oscillator frequency, a proportional coefficient needs to be added to balance the crystal oscillator reading and the actual film thickness.

[0033] Specifically, the first aspect provides a material suitable for chip bonding, wherein the composition of the material is one or more of In, Sn, Bi, Au, and Sn.

[0034] Regarding the material being In x Sn y Bi z , where 0≤x≤0.41, 0≤y≤0.8, 0≤z≤0.5.

[0035] Regarding the material being In x Sn y Bi z , where 0≤x≤0.3, 0≤y≤0.6, 0≤z≤0.4.

[0036] The melting point of the material is ≤100°C.

[0037] In the above materials x Sn y Bi z , it can greatly reduce the stress caused by the difference in thermal expansion coefficients between sapphire and silicon genes in a lower temperature bonding environment, thereby improving bonding accuracy and success rate.

[0038] Regarding the material being Au a Sn b, where 0≤a≤0.9, 0≤b≤0.6.

[0039] Regarding the material being Au a Sn b , where 0≤a≤0.4, 0≤b≤0.6.

[0040] The melting point of the material is 200-500°C.

[0041] In the above materials Au a Sn b The material is harder, which improves the resistance to stress and thus increases the success rate of bonding.

[0042] The second aspect is to provide a method for coating a material suitable for chip bonding, the method comprising the following steps:

[0043] (1) Clean and dry the surface of the CMOS driver substrate with the circuit engraved inside;

[0044] (2) coating photoresist on the CMOS driver substrate;

[0045] (3) exposing the coated portion of the CMOS driver substrate and removing the exposed photoresist;

[0046] (4) depositing a buffer layer material on the surface of the CMOS driver substrate in the form of a coating to form a buffer layer, and stripping off the remaining photoresist;

[0047] (5) Then, the photoresist is spin-coated, and the buffer layer is exposed through a photolithography process. The material suitable for chip bonding is deposited on the surface of the CMOS driver substrate in the form of a coating to form a metal electrode. The photoresist is removed, and the coating of the material suitable for chip bonding is completed.

[0048] In the above process, the buffer layer material is any one of Cr, Ni, Ti, Pt, and Au. The coating process is to pre-melt the buffer layer material first, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The buffer layer thickness is 0 to 1.5 μm.

[0049] In the above process, the coating process in step (5) is to pre-melt the buffer layer material first, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The thickness of the metal electrode is 3 to 6 μm.

[0050] Example 1

[0051] The material suitable for chip bonding is In 0.33 Sn 0.17 Bi 0.5 , melting point 82℃.

[0052] A method for coating a material suitable for chip bonding, the method comprising the following steps:

[0053] (1) Clean and dry the surface of the CMOS driver substrate with the circuit engraved inside;

[0054] (2) coating photoresist on the CMOS driver substrate;

[0055] (3) exposing the coated portion of the CMOS driver substrate and removing the exposed photoresist;

[0056] (4) depositing a buffer layer material on the surface of the CMOS driver substrate in the form of a coating to form a buffer layer. The buffer layer material is Au. The coating process is to pre-melt the buffer layer material to melt it, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The buffer layer thickness is 0.8 μm, and the remaining photoresist is stripped cleanly.

[0057] (5) Then, the photoresist is spin-coated, and the buffer layer is exposed through the photolithography process. The material suitable for chip bonding is deposited on the surface of the CMOS driver substrate in the form of a coating to form a metal electrode. The coating process is to pre-melt the buffer layer material first, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The thickness of the metal electrode is 4μm. After removing the photoresist, the coating of the material suitable for chip bonding is completed.

[0058] Example 2

[0059] The material suitable for chip bonding is In 0.29 Sn 0.27 Bi 0.44 , melting point 83.5℃.

[0060] A method for coating a material suitable for chip bonding, the method comprising the following steps:

[0061] (1) Clean and dry the surface of the CMOS driver substrate with the circuit engraved inside;

[0062] (2) coating photoresist on the CMOS driver substrate;

[0063] (3) exposing the coated portion of the CMOS driver substrate and removing the exposed photoresist;

[0064] (4) depositing a buffer layer material on the surface of the CMOS driver substrate in the form of a coating to form a buffer layer. The buffer layer material is Au. The coating process is to pre-melt the buffer layer material to melt it, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The buffer layer thickness is 0.8 μm, and the remaining photoresist is stripped cleanly.

[0065] (5) Then, the photoresist is spin-coated, and the buffer layer is exposed through the photolithography process. The material suitable for chip bonding is deposited on the surface of the CMOS driver substrate in the form of a coating to form a metal electrode. The coating process is to pre-melt the buffer layer material first, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The thickness of the metal electrode is 4μm. After removing the photoresist, the coating of the material suitable for chip bonding is completed.

[0066] Example 3

[0067] The material suitable for chip bonding is In 0.4 Sn 0.17 Bi 0.426 , melting point 75.1℃.

[0068] A method for coating a material suitable for chip bonding, the method comprising the following steps:

[0069] (1) Clean and dry the surface of the CMOS driver substrate with the circuit engraved inside;

[0070] (2) coating photoresist on the CMOS driver substrate;

[0071] (3) exposing the coated portion of the CMOS driver substrate and removing the exposed photoresist;

[0072] (4) depositing a buffer layer material on the surface of the CMOS driver substrate in the form of a coating to form a buffer layer. The buffer layer material is Au. The coating process is to pre-melt the buffer layer material to melt it, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The buffer layer thickness is 0.8 μm, and the remaining photoresist is stripped cleanly.

[0073] (5) Then, the photoresist is spin-coated, and the buffer layer is exposed through the photolithography process. The material suitable for chip bonding is deposited on the surface of the CMOS driver substrate in the form of a coating to form a metal electrode. The coating process is to pre-melt the buffer layer material first, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The thickness of the metal electrode is 4μm. After removing the photoresist, the coating of the material suitable for chip bonding is completed.

[0074] Example 4

[0075] The material suitable for chip bonding is Au 0.1 Sn 0.2 , the melting point of the material is 309°C.

[0076] The melting point of the material is 200-500°C.

[0077] A method for coating a material suitable for chip bonding, the method comprising the following steps:

[0078] (1) Clean and dry the surface of the CMOS driver substrate with the circuit engraved inside;

[0079] (2) coating photoresist on the CMOS driver substrate;

[0080] (3) exposing the coated portion of the CMOS driver substrate and removing the exposed photoresist;

[0081] (4) depositing a buffer layer material on the surface of the CMOS driver substrate in the form of a coating to form a buffer layer. The buffer layer material is Au. The coating process is to pre-melt the buffer layer material to melt it, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The buffer layer thickness is 0.8 μm, and the remaining photoresist is stripped cleanly.

[0082] (5) Then, the photoresist is spin-coated, and the buffer layer is exposed through the photolithography process. The material suitable for chip bonding is deposited on the surface of the CMOS driver substrate in the form of a coating to form a metal electrode. The coating process is to pre-melt the material suitable for chip bonding first, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The thickness of the metal electrode is 4μm. After removing the photoresist, the coating of the material suitable for chip bonding is completed.

[0083] Example 5

[0084] The material suitable for chip bonding is Au 0.1 Sn 0.4 The melting point of the material is 257°C.

[0085] A method for coating a material suitable for chip bonding, the method comprising the following steps:

[0086] (1) Clean and dry the surface of the CMOS driver substrate with the circuit engraved inside;

[0087] (2) coating photoresist on the CMOS driver substrate;

[0088] (3) exposing the coated portion of the CMOS driver substrate and removing the exposed photoresist;

[0089] (4) depositing a buffer layer material on the surface of the CMOS driver substrate in the form of a coating to form a buffer layer. The buffer layer material is Au. The coating process is to pre-melt the buffer layer material to melt it, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The buffer layer thickness is 0.8 μm, and the remaining photoresist is stripped cleanly.

[0090] (5) Then, the photoresist is spin-coated, and the buffer layer is exposed through the photolithography process. The material suitable for chip bonding is deposited on the surface of the CMOS driver substrate in the form of a coating to form a metal electrode. The coating process is to pre-melt the material suitable for chip bonding first, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The thickness of the metal electrode is 4μm. After removing the photoresist, the coating of the material suitable for chip bonding is completed.

[0091] Example 6

[0092] The material suitable for chip bonding is Au 0.8 Sn 0.2 , the melting point of the material is 280°C.

[0093] A method for coating a material suitable for chip bonding, the method comprising the following steps:

[0094] (1) Clean and dry the surface of the CMOS driver substrate with the circuit engraved inside;

[0095] (2) coating photoresist on the CMOS driver substrate;

[0096] (3) exposing the coated portion of the CMOS driver substrate and removing the exposed photoresist;

[0097] (4) depositing a buffer layer material on the surface of the CMOS driver substrate in the form of a coating to form a buffer layer. The buffer layer material is Au. The coating process is to pre-melt the buffer layer material to melt it, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The buffer layer thickness is 0.8 μm, and the remaining photoresist is stripped cleanly.

[0098] (5) Then, the photoresist is spin-coated, and the buffer layer is exposed through the photolithography process. The material suitable for chip bonding is deposited on the surface of the CMOS driver substrate in the form of a coating to form a metal electrode. The coating process is to pre-melt the material suitable for chip bonding first, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The thickness of the metal electrode is 4μm. After removing the photoresist, the coating of the material suitable for chip bonding is completed.

[0099] 100 products prepared in Examples 1 to 6 above were randomly selected and tested as follows:

[0100] Detection method: There are VDD and GND pins in the pad area of ​​the CMOS chip. Connect the GND terminal to the positive electrode and the VDD terminal to the negative electrode. Input voltage is -1V to 1V, step 0.01V, test the IV characteristic curve, and take the average value of 100 test results of the test embodiment product. The test results are shown in Table 1.

[0101] Table 1

[0102]

[0103] Take 500 products prepared in Examples 1 to 6 and perform the following operations:

[0104] (1) Spin-coating a protective photoresist on the surface of a CMOS driver substrate (i.e., the product prepared in Examples 1 to 6) with a material suitable for chip bonding, and scribing along the dicing lines to separate each die;

[0105] (2) Bonding the Micro LED chip to the CMOS driver substrate through a bonding process, wherein the bonding temperature of Examples 1 to 3 is 100° C., the bonding pressure is 200 N, and the bonding time is 5 minutes; and the bonding temperature of Examples 4 to 6 is 320° C., the bonding pressure is 200 N, and the bonding time is 5 minutes;

[0106] (3) Peeling off the Micro LED growth substrate by laser or chemical peeling;

[0107] (4) Package the bonded chip onto the PCB board.

[0108] Thus, the products of Preparation Examples 1 to 6 were obtained and tested. The test results are shown in Table 2 below.

[0109] Table 2

[0110]

[0111]

[0112] Comparative Example 1

[0113] The material suitable for chip bonding is Au-In.

[0114] A method for coating a material suitable for chip bonding, the method comprising the following steps:

[0115] (1) Clean and dry the surface of the CMOS driver substrate with the circuit engraved inside;

[0116] (2) coating photoresist on the CMOS driver substrate;

[0117] (3) exposing the coated portion of the CMOS driver substrate and removing the exposed photoresist;

[0118] (4) depositing a buffer layer material on the surface of the CMOS driver substrate in the form of a coating to form a buffer layer. The buffer layer material is Au. The coating process is to pre-melt the buffer layer material to melt it, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The buffer layer thickness is 0.8 μm, and the remaining photoresist is stripped cleanly.

[0119] (5) Then, the photoresist is spin-coated, and the buffer layer is exposed through the photolithography process. The material suitable for chip bonding is deposited on the surface of the CMOS driver substrate in the form of a coating to form a metal electrode. The coating process is to pre-melt the material suitable for chip bonding first, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The thickness of the metal electrode is 4μm. After removing the photoresist, the coating of the material suitable for chip bonding is completed.

[0120] Comparative Example 2

[0121] The material suitable for chip bonding is Au-Sn.

[0122] A method for coating a material suitable for chip bonding, the method comprising the following steps:

[0123] (1) Clean and dry the surface of the CMOS driver substrate with the circuit engraved inside;

[0124] (2) coating photoresist on the CMOS driver substrate;

[0125] (3) exposing the coated portion of the CMOS driver substrate and removing the exposed photoresist;

[0126] (4) depositing a buffer layer material on the surface of the CMOS driver substrate in the form of a coating to form a buffer layer. The buffer layer material is Au. The coating process is to pre-melt the buffer layer material to melt it, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The buffer layer thickness is 0.8 μm, and the remaining photoresist is stripped cleanly.

[0127] (5) Then, the photoresist is spin-coated, and the buffer layer is exposed through the photolithography process. The material suitable for chip bonding is deposited on the surface of the CMOS driver substrate in the form of a coating to form a metal electrode. The coating process is to pre-melt the material suitable for chip bonding first, and then control the PID parameters to deposit the material atoms on the surface of the CMOS driver substrate. The thickness of the metal electrode is 4μm. After removing the photoresist, the coating of the material suitable for chip bonding is completed.

[0128] Comparative Examples 1 and 2 were tested in the following manner: there were VDD and GND pins in the pad area of ​​the CMOS chip. The GND terminal was connected to the positive electrode and the VDD terminal was connected to the negative electrode. The input voltage was -1V to 1V with a step of 0.01V. The IV characteristic curve was tested. The average of 100 test results of the test embodiment products was taken. The test results are shown in Table 3.

[0129] Table 3

[0130]

[0131] Take 500 products prepared in Comparative Examples 1 and 2 respectively and perform the following operations:

[0132] (1) Spin-coating a protective photoresist on the surface of a CMOS driver substrate (i.e., the product prepared in Comparative Examples 1 and 2) with a material suitable for chip bonding, and scribing along the dicing lines to separate each die;

[0133] (2) Bonding the Micro LED chip to the CMOS driver substrate through a bonding process, selecting the bonding temperature, bonding pressure, and bonding time suitable for Au-In and Au-Sn materials;

[0134] (3) Peeling off the Micro LED growth substrate by laser or chemical peeling;

[0135] (4) Package the bonded chip onto the PCB board.

[0136] The products of Comparative Examples 1 and 2 were obtained and tested. The test results are shown in Table 4 below.

[0137] Table 4

[0138]

[0139] In summary, the product of the present invention improves bonding accuracy and success rate and has excellent performance.

[0140] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A material suitable for chip bonding, characterized in that: The material comprises one or more of In, Sn, Bi, Au and Sn.

2. The material suitable for chip bonding according to claim 1, characterized in that: The material is In x Sn y Bi z , where 0≤x≤0.41, 0≤y≤0.8, 0≤z≤0.

5.

3. The material suitable for chip bonding according to claim 2, characterized in that: The material is In x Sn y Bi z , where 0≤x≤0.3, 0≤y≤0.6, 0≤z≤0.

4.

4. The material suitable for chip bonding according to claim 2 or 3, characterized in that: The melting point of the material is ≤100°C.

5. The material suitable for chip bonding according to claim 1, characterized in that: The material is Au a Sn b , where 0≤a≤0.9, 0≤b≤0.

6.

6. The material suitable for chip bonding according to claim 5, characterized in that: The material is Au a Sn b , where 0≤a≤0.4, 0≤b≤0.

6.

7. The material suitable for chip bonding according to claim 5 or 6, characterized in that: The melting point of the material is 200-500°C.

8. A method for coating a material suitable for chip bonding as claimed in any one of claims 1 to 7, characterized in that: The method comprises the following steps: (1) Clean and dry the surface of the CMOS driver substrate with the circuit engraved inside; (2) coating photoresist on the CMOS driver substrate; (3) exposing the coated portion on the CMOS driver substrate and removing the exposed photoresist; (4) depositing a buffer layer material on the surface of the CMOS drive substrate in the form of a coating to form a buffer layer, and stripping off the remaining photoresist; (5) Then, the photoresist is spin-coated, and the buffer layer is exposed through a photolithography process. The material suitable for chip bonding is deposited on the CMOS surface in the form of a coating to form a metal electrode. The photoresist is removed, and the coating of the material suitable for chip bonding is completed.

9. The film coating method of the material suitable for chip bonding according to claim 8, characterized in that: In step (4), the buffer layer material is any one of Cr, Ni, Ti, Pt, and Au. The coating process is to pre-melt the buffer layer material first, and then control the PID parameters to deposit the buffer layer material atoms on the surface of the CMOS driver substrate. The buffer layer thickness is 0 to 1.5 μm.

10. The method for coating a material suitable for chip bonding according to claim 8, characterized in that: The coating process in step (5) is to pre-melt the material suitable for chip bonding, and then control the PID parameters to deposit the buffer layer material atoms on the surface of the CMOS drive substrate. The thickness of the metal electrode is 3-6 μm.

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