Semiconductor test structure and test method of semiconductor structure

Abstract

The invention relates to a semiconductor test structure and a test method of a semiconductor structure. The semiconductor test structure comprises a main test structure and an auxiliary test structure which are mutually insulated; the main test structure comprises a main resistor structure, a first bonding pad and a second bonding pad, the first bonding pad is connected with the head end of the main resistor structure, and the second bonding pad is connected to the tail end of the main resistor structure; the auxiliary test structure comprises an auxiliary resistor structure and a third bonding pad, and the third bonding pad is connected with the auxiliary resistor structure; wherein the auxiliary resistor structure comprises a plurality of jumper structures, and the orthographic projection of the jumper structures at least partially coincides with the orthographic projection of the main resistor structure. The semiconductor test structure can monitor the resistor and the capacitor on the same layer at the same time, only occupies the area of three bonding pads, can effectively save the chip area, reduces the research and development cost, can monitor the resistance value and the capacitance value of the semiconductor structure with the same density under the same actual process, and improves the test efficiency. Therefore, the fitting precision of the simulation of the resistor-capacitor file in the process design suite and the actual process is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor test structure and a semiconductor structure test method. Background Art

[0002] As the advancement of semiconductor process nodes continues, the cost of tape-out continues to increase. As a result, the requirements for the simulation accuracy of parasitic parameters of semiconductor process design kits (PDKs) are becoming higher and higher for modules designed based on advanced processes.

[0003] However, resistors of the same density and capacitors of the same layer can only be monitored separately, and the resistance and capacitance values ​​of the same density under the same process cannot be monitored, which affects the fitting accuracy between the capacitor and resistor file simulation in the process design kit and the actual process. In addition, the test structure for discretely monitoring resistors and capacitors usually wastes chip area and increases R&D costs. Summary of the invention

[0004] Based on this, an embodiment of the present application provides a semiconductor test structure and a semiconductor structure testing method.

[0005] According to some embodiments, the present application provides a semiconductor test structure, which includes a main test structure and a sub-test structure insulated from each other; the main test structure includes a main resistance structure, a first pad and a second pad, the first pad is connected to the head end of the main resistance structure, and the second pad is connected to the end of the main resistance structure; the sub-test structure includes a sub-resistance structure and a third pad, the third pad is connected to the sub-resistance structure; wherein the sub-resistance structure includes multiple jumper structures, and the orthographic projection of the jumper structure at least partially overlaps with the orthographic projection of the main resistance structure.

[0006] In the semiconductor test structure of the above embodiment, the semiconductor test structure includes a main test structure and a sub-test structure that are insulated from each other, the sub-resistance structure includes a plurality of jumper structures, the orthographic projection of the jumper structure overlaps at least partially with the orthographic projection of the main resistance structure, the main resistance structure of the main test structure is connected to the first pad and the second pad, and the sub-resistance structure of the sub-test structure is connected to the third pad. In this way, the sub-test structure can not only provide a density environment for the main test structure, but also can be combined into a semiconductor test structure by combining the two test structures, so as to directly test the resistance and same-layer capacitance of the semiconductor structure through the first pad, the second pad and / or the third pad, so as to realize a test structure that can simultaneously monitor the resistance and the same-layer capacitance. Since the semiconductor test structure only occupies the area of ​​three pads, it can effectively save chip area and reduce R&D costs. In addition, the above-mentioned semiconductor test structure can monitor the resistance value and capacitance value of the semiconductor structure of the same density under the same actual process, thereby improving the fitting accuracy of the resistance and capacitance file simulation and the actual process in the process design kit.

[0007] In some embodiments, the main resistance structure includes a first branch resistor, an end branch resistor, and multiple main resistance units connected end to end, and the first branch resistor and the end branch resistor are located on the same side of the main resistance unit; one end of the first branch resistor is connected to the first end of the first main resistance unit, and the other end is connected to the first pad; one end of the end branch resistor is connected to the end of the last main resistance unit, and the other end is connected to the second pad.

[0008] In some embodiments, the main resistor unit includes a U-shaped resistor structure and two strip branch resistors connected end to end to the U-shaped resistor structure; the strip branch resistors extend along a first direction and are at least connected to the strip branch resistor in the previous or next main resistor unit.

[0009] In some embodiments, the jumper structure includes a first jumper resistor and a second jumper resistor extending along the second direction; the first jumper resistor is located above the first strip branch resistor along the third direction, and the second jumper resistor is located above the last strip branch resistor along the third direction, and the third direction and the second direction are all perpendicular to the first direction.

[0010] In some embodiments, the secondary resistance structure also includes a first sub-resistance structure and a second sub-resistance structure, and the orthographic projections of the first sub-resistance structure and the second sub-resistance structure do not overlap with the orthographic projection of the main resistance structure; the first jumper resistor is located between the beginning of the first sub-resistance structure and the beginning of the second sub-resistance structure; the second jumper resistor is located between the end of the first sub-resistance structure and the end of the second sub-resistance structure.

[0011] In some embodiments, the first sub-resistance structure includes multiple first sub-resistance units and a first extension branch extending along a first direction, and the head ends of the multiple first sub-resistance units are respectively connected to the first extension branches; the second sub-resistance structure includes multiple second sub-resistance units and a second extension branch extending along the first direction, and the head ends of the multiple second sub-resistance units are respectively connected to the second extension branches; the first sub-resistance unit extends along the second direction and is located on both sides of the adjacent main resistance unit; the second sub-resistance unit extends along the second direction into the main resistance unit.

[0012] In some embodiments, the second sub-resistance structure also includes an intermediate extension branch, which is located on the symmetry axis of the second extension branch and extends along the second direction; the head end of the intermediate extension branch is connected to the second extension branch, and the end of the intermediate extension branch is connected to the third pad.

[0013] In some embodiments, the first sub-resistance structure also includes a first contact electrode and a second contact electrode, the first contact electrode is located at the end of the first first sub-resistance unit, and the second contact electrode is located at the beginning of the second extension branch; the second sub-resistance structure also includes a third contact electrode and a fourth contact electrode, the third contact electrode is located at the end of the last first sub-resistance unit, and the fourth contact electrode is located at the end of the second extension branch; the first and second ends of the first jumper resistor are respectively connected to the first contact electrode and the second contact electrode, and the first and second ends of the second jumper resistor are respectively connected to the third contact electrode and the fourth contact electrode.

[0014] According to some embodiments, the present application further provides a method for testing a semiconductor structure, wherein the semiconductor test structure in the above embodiment is used to test the method for testing the semiconductor structure, and the method includes:

[0015] Applying a first voltage to the first pad, applying a second voltage to the second pad, applying a third voltage to the third pad, obtaining a current of the second pad, so as to test the resistance of the semiconductor structure test method; and / or

[0016] A fourth voltage is applied to the first pad, a fifth voltage is applied to the second pad, a sixth voltage is applied to the third pad, and a current of the third pad is obtained to test the capacitance of the semiconductor structure test method.

[0017] In the semiconductor structure test method of the above embodiment, by applying a first voltage to the first pad, applying a second voltage to the second pad, applying a third voltage to the third pad, obtaining the current of the second pad, so as to test the resistance of the semiconductor structure test method, and by applying a fourth voltage to the first pad, applying a fifth voltage to the second pad, applying a sixth voltage to the third pad, obtaining the current of the third pad, so as to test the capacitance of the semiconductor structure test method, the resistance and the same-layer capacitance of the semiconductor structure can be directly tested based on the same semiconductor test structure. In addition, the above test method can monitor the resistance and capacitance values ​​of semiconductor structures of the same density under the same actual process, thereby improving the fitting accuracy of the resistance and capacitance file simulation in the process design kit and the actual process.

[0018] In some embodiments, the first voltage is 0V, the second voltage is 1.8V, and the third voltage is 0V; and / or the first voltage is 0V, the second voltage is 0V, and the third voltage is 1.8V. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic top view of a semiconductor test structure;

[0020] Figure 2 is a schematic top view of another semiconductor test structure;

[0021] Figure 3 A schematic top view of a semiconductor test structure provided in one embodiment of the present application;

[0022] Figure 4 A schematic diagram of a flow chart of a semiconductor structure testing method provided in one embodiment of the present application.

[0023] Explanation of the accompanying drawings: 100, main test structure; 110, main resistance structure; 111, head branch resistance; 112, end branch resistance; 113, main resistance unit; 1131, U-shaped resistance structure; 1132, strip branch resistance; 120, first solder pad; 130, second solder pad; 200, auxiliary test structure; 210, auxiliary resistance structure; 211, jumper structure; 2111, first jumper resistance; 2112, second jumper resistance; 220, third solder pad; 230, first sub-resistance structure; 231, first auxiliary resistance unit; 232, first extended branch; 233, first contact electrode; 234, second contact electrode; 240, second sub-resistance structure; 241, second auxiliary resistance unit; 242, second extended branch; 243, middle extended branch; 244, third contact electrode; 245, fourth contact electrode. DETAILED DESCRIPTION

[0024] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0026] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0027] In addition, in order to clearly indicate the multiple layers and regions in the drawings, the thickness of each layer and each region in the drawings are enlarged to clearly illustrate the relative positions between the layers and the distribution of each region. When a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, the expression includes not only the case where it is "directly" above the other part, but also the case where there are other layers in between. And, it is understood that when a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, it generally refers to the side located directly above the other part.

[0028] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0029] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0030] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.

[0031] See also Figure 1 and Figure 2 When developing capacitor and resistor files, the semiconductor process design kit (PDK) needs to test the actual process resistance and capacitance values, and derive the actual size and thickness information under different densities based on the comprehensive test results of resistance and capacitance. Usually, for the same density resistor test structure, such as Figure 1 As shown, the same-layer capacitor test structure with the same density is as follows Figure 2 As shown. That is, based on the limitations of existing resistor and capacitor structures, the resistor test structure of the same density and the capacitor test structure of the same layer can only be monitored separately, which greatly wastes the chip area. In addition, there are process deviations at different positions of the chip, which will cause the resistance and capacitance values ​​of the test structure of the same density to be tested at different positions to be mismatched, and it is impossible to fully monitor the resistance and capacitance values ​​of the same density under the same actual process, thereby affecting the fitting accuracy of the capacitor and resistor file simulation in the semiconductor process design kit and the actual process.

[0032] Based on this, in order to solve the above problems, an embodiment of the present application provides a semiconductor test structure and a semiconductor structure testing method.

[0033] Figure 3Schematic diagram of a top view of a semiconductor test structure in some embodiments of the present application is shown. Figure 3 The present application provides a semiconductor test structure. The semiconductor test structure includes a main test structure 100 and a sub-test structure 200 that are insulated from each other. The main test structure 100 includes a main resistance structure 110, a first pad 120 and a second pad 130, wherein the first pad 120 is connected to the head end of the main resistance structure 110, and the second pad 130 is connected to the end of the main resistance structure 110; the sub-test structure 200 includes a sub-resistance structure 210 and a third pad 220, wherein the third pad 220 is connected to the sub-resistance structure 210; wherein the sub-resistance structure 210 includes a plurality of jumper structures 211, and the orthographic projection of the jumper structure 211 at least partially overlaps with the orthographic projection of the main resistance structure 110.

[0034] In the semiconductor test structure of the above embodiment, the semiconductor test structure includes a main test structure 100 and a sub-test structure 200 which are insulated from each other, the sub-resistance structure 210 includes a plurality of jumper structures 211, the orthographic projection of the jumper structure 211 at least partially overlaps with the orthographic projection of the main resistance structure 110, the main resistance structure 110 of the main test structure 100 is connected to the first pad 120 and the second pad 130, and the sub-resistance structure 210 of the sub-test structure 200 is connected to the third pad 220. In this way, the sub-test structure 200 can not only provide a density environment for the main test structure 100, but also combine the two test structures into a semiconductor test structure, so that the resistance and the same-layer capacitance of the semiconductor structure can be directly tested through the first pad 120, the second pad 130 and / or the third pad 220, so as to realize a test structure that can monitor the resistance and the same-layer capacitance at the same time. Since the semiconductor test structure only occupies the area of ​​three pads, it can effectively save the chip area and reduce the R&D cost. Furthermore, the semiconductor test structure can monitor the resistance and capacitance values ​​of semiconductor structures with the same density under the same actual process, thereby improving the fitting accuracy between the resistance and capacitance file simulation in the process design kit and the actual process.

[0035] It should be noted that the orthographic projection of the jumper structure 211 can be understood as a vertical projection. Figure 3 The x direction shown and perpendicular to Figure 3 The orthographic projection of the jumper structure 211 at least partially overlaps with the orthographic projection of the main resistor structure 110 , which can be understood as the jumper structure 211 is located in the upper structure of the main resistor structure 110 .

[0036] For example, the main test structure 100 and the subsidiary test structure 200 are insulated from each other, which can be understood as an insulating film layer being provided between the main test structure 100 and the subsidiary test structure 200 .

[0037] For example, the jumper structure 211 and the main resistor structure 110 are insulated from each other, which can be understood as an insulating film layer being provided between the jumper structure 211 and the main resistor structure 110 .

[0038] In some embodiments, the main resistance structure 110 includes a head branch resistor 111, an end branch resistor 112, and a plurality of main resistance units 113 connected end to end, wherein the head branch resistor 111 and the end branch resistor 112 are located on the same side of the main resistance unit 113; one end of the head branch resistor 111 is connected to the head end of the first main resistance unit 113, and the other end is connected to the first pad 120; one end of the end branch resistor 112 is connected to the end of the last main resistance unit 113, and the other end is connected to the second pad 130.

[0039] For example, the number of the main resistance units 113 is 3-5. For example, the number of the main resistance units 113 can be 3, 4 or 5. Figure 3 In the figure, four main resistance units 113 are used as an example for illustration.

[0040] For example, the first-end branch resistor 111 and the terminal branch resistor 112 are both rectangular and extend along the second direction. The second direction can be understood as follows: Figure 3 Since the first branch resistor 111 and the terminal branch resistor 112 are located on the same side of the main resistor unit 113 , the first pad 120 and the second pad 130 are also located on the same side of the main resistor unit 113 .

[0041] In some embodiments, the first pad 120, the second pad 130 and the third pad 220 are all made of a conductive material. For example, the conductive material may be a metal material, such as tin, titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten or a combination thereof, for example, ruthenium, tungsten, gold or silver are all low-resistance metals, which can reduce the resistance of the first pad 120, the second pad 130 and the third pad 220, and are conducive to improving the test accuracy of the semiconductor test structure.

[0042] In some embodiments, the main resistance unit 113 includes a U-shaped resistance structure 1131 and two strip branch resistors 1132 connected end to end to the U-shaped resistance structure 1131; the strip branch resistors 1132 extend along a first direction and are at least connected to the strip branch resistor 1132 in the previous or next main resistance unit 113.

[0043] For example, two adjacent main resistance units 113 share a strip branch resistor 1132 therebetween. Each main resistance unit 113 includes a U-shaped resistance structure 1131. In some embodiments, the number of all strip branch resistors 1132 in the main resistance structure 110 is greater than the number of main resistance units 113. For example, the number of all strip branch resistors 1132 in the main resistance structure 110 is one more than the number of main resistance units 113. For example, the number of strip branch resistors 1132 is 4-6. For example, the number of strip branch resistors 1132 is 4, 5, or 6. Figure 3 As shown, in the embodiment where there are four main resistance units 113 , the number of the strip branch resistors 1132 is five.

[0044] For example, the opening of the U-shaped resistor structure 1131 faces the first branch resistor 111 or the last branch resistor 112. The first direction can be understood as follows: Figure 3 The x direction is shown.

[0045] In some embodiments, the first strip branch resistor 1132 is connected to the end of the first branch resistor 111 away from the first pad 120, and the last strip branch resistor 1132 is connected to the end of the terminal branch resistor 112 away from the second pad 130. For example, the strip branch resistor 1132 is rectangular. Figure 3 As shown, in the embodiment where the number of strip branch resistors 1132 is 5, the first strip branch resistor 1132 is connected to the end of the head branch resistor 111 away from the first pad 120, and the fifth strip branch resistor 1132 is connected to the end of the terminal branch resistor 112 away from the second pad 130.

[0046] In some embodiments, the jumper structure 211 includes a first jumper resistor 2111 and a second jumper resistor 2112 extending along the second direction; the first jumper resistor 2111 is located above the first strip branch resistor 1132 along the third direction, and the second jumper resistor 2112 is located above the last strip branch resistor 1132 along the third direction, and the third direction, the second direction and the first direction are all perpendicular. For example, the third direction can be understood as the positive projection direction of the jumper structure 211.

[0047] For example, the first jumper resistor 2111 and the second jumper resistor 2112 are both rectangular and parallel to the head-end branch resistor 111 or the end-end branch resistor 112 .

[0048] In some embodiments, the secondary resistance structure 210 also includes a first sub-resistance structure 230 and a second sub-resistance structure 240, and the orthographic projections of the first sub-resistance structure 230 and the second sub-resistance structure 240 do not overlap with the orthographic projection of the main resistance structure 110; the first jumper resistor 2111 is located between the beginning of the first sub-resistance structure 230 and the beginning of the second sub-resistance structure 240; the second jumper resistor 2112 is located between the end of the first sub-resistance structure 230 and the end of the second sub-resistance structure 240.

[0049] In some embodiments, the first sub-resistance structure 230 includes a plurality of first sub-resistance units 231 and a first extension branch 232 extending along a first direction, and the head ends of the plurality of first sub-resistance units 231 are respectively connected to the first extension branch 232; the first sub-resistance units 231 extend along a second direction and are located on both sides of adjacent main resistance units 113.

[0050] In some embodiments, the second sub-resistance structure 240 includes multiple second sub-resistance units 241 and second extension branches 242 extending along the first direction, and the head ends of the multiple second sub-resistance units 241 are respectively connected to the second extension branches 242; the second sub-resistance units 241 extend into the main resistance unit 113 along the second direction.

[0051] In some embodiments, the number of first sub-resistance units 231 is greater than the number of second sub-resistance units 241. For example, the number of second sub-resistance units 241 is the same as the number of main resistance units 113, and the number of first sub-resistance units 231 is one more than the number of second sub-resistance units 241.

[0052] In some embodiments, the second sub-resistance structure 240 also includes an intermediate extension branch 243, which is located on the symmetry axis of the second extension branch 242 and extends along the second direction; the head end of the intermediate extension branch 243 is connected to the second extension branch 242, and the end of the intermediate extension branch 243 is connected to the third solder pad 220.

[0053] For example, the third pad 220 is located between the first pad 120 and the second pad 130. For example, the third pad 220 is located at the midpoint of the connection line between the first pad 120 and the second pad 130, so as to save the area of ​​the semiconductor test structure.

[0054] In some embodiments, the first sub-resistance structure 230 also includes a first contact electrode 233 and a second contact electrode 234, the first contact electrode 233 is located at the end of the first first sub-resistance unit 231, and the second contact electrode 234 is located at the beginning of the second extension branch 242; the second sub-resistance structure 240 also includes a third contact electrode 244 and a fourth contact electrode 245, the third contact electrode 244 is located at the end of the last first sub-resistance unit 231, and the fourth contact electrode 245 is located at the end of the second extension branch 242; the first jumper resistor 2111 is connected to the first contact electrode 233 and the second contact electrode 234 at both ends, and the second jumper resistor 2112 is connected to the third contact electrode 244 and the fourth contact electrode 245 at both ends.

[0055] In some embodiments, the first contact electrode 233, the second contact electrode 234, the third contact electrode 244, and the fourth contact electrode 245 are all made of a conductive material. For example, the conductive material may be a metal material, for example, the metal material may include tin, titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, or a combination thereof, for example, ruthenium, tungsten, gold, or silver are all low-resistance metals, which can reduce the resistance of the first contact electrode 233, the second contact electrode 234, the third contact electrode 244, and the fourth contact electrode 245, and is conducive to improving the test accuracy of the semiconductor test structure.

[0056] See also Figure 4 According to some embodiments, the present application also provides a method for testing a semiconductor structure, comprising the following steps.

[0057] Step S10, applying a first voltage to the first pad, applying a second voltage to the second pad, applying a third voltage to the third pad, obtaining a current of the second pad to test the resistance of the semiconductor structure test method; and / or

[0058] Step S30, applying a fourth voltage to the first pad, applying a fifth voltage to the second pad, applying a sixth voltage to the third pad, obtaining a current of the third pad, so as to test the capacitance of the semiconductor structure test method.

[0059] In the semiconductor structure test method of the above embodiment, by applying a first voltage to the first pad, applying a second voltage to the second pad, applying a third voltage to the third pad, obtaining the current of the second pad, so as to test the resistance of the semiconductor structure test method, and by applying a fourth voltage to the first pad, applying a fifth voltage to the second pad, applying a sixth voltage to the third pad, obtaining the current of the third pad, so as to test the capacitance of the semiconductor structure test method, the resistance and the same-layer capacitance of the semiconductor structure can be directly tested based on the same semiconductor test structure. In addition, the above test method can monitor the resistance and capacitance values ​​of semiconductor structures of the same density under the same actual process, thereby improving the fitting accuracy of the resistance and capacitance file simulation in the process design kit and the actual process.

[0060] In the above embodiments of the present disclosure, unless otherwise specified herein, the execution of each step in the method is not strictly limited in order, and these steps may not necessarily be executed in the order described, and may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0061] In some embodiments, the first voltage is 0V, the second voltage is 1.8V, and the third voltage is 0V; and / or the first voltage is 0V, the second voltage is 0V, and the third voltage is 1.8V.

[0062] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor test structure, characterized in that: It includes a main test structure and a sub-test structure which are insulated from each other; The main test structure includes a main resistance structure, a first pad and a second pad, wherein the first pad is connected to the head end of the main resistance structure, and the second pad is connected to the end of the main resistance structure; The secondary test structure includes a secondary resistance structure and a third pad, and the third pad is connected to the secondary resistance structure; The secondary resistor structure includes a plurality of jumper structures, and the orthographic projection of the jumper structure at least partially overlaps with the orthographic projection of the main resistor structure.

2. The semiconductor test structure according to claim 1, characterized in that: The main resistance structure comprises a head-end branch resistance, a terminal branch resistance and a plurality of head-to-tail connected main resistance units, wherein the head-end branch resistance and the terminal branch resistance are located on the same side of the main resistance unit; One end of the first-end branch resistor is connected to the first end of the first main resistor unit, and the other end is connected to the first pad; One end of the terminal branch resistor is connected to the end of the last main resistor unit, and the other end is connected to the second pad.

3. The semiconductor test structure according to claim 2, characterized in that: The main resistor unit includes a U-shaped resistor structure and two strip-shaped branch resistors connected end to end with the U-shaped resistor structure; The strip-shaped branch resistors extend along a first direction and are connected to at least the strip-shaped branch resistors in a previous or next main resistor unit.

4. The semiconductor test structure according to claim 3, characterized in that: The jumper structure comprises a first jumper resistor and a second jumper resistor extending along the second direction; The first jumper resistor is located above the first strip branch resistor along the third direction, and the second jumper resistor is located above the last strip branch resistor along the third direction. The third direction and the second direction are perpendicular to the first direction.

5. The semiconductor test structure according to claim 4, characterized in that: The auxiliary resistor structure further includes a first sub-resistance structure and a second sub-resistance structure, and the orthographic projections of the first sub-resistance structure and the second sub-resistance structure do not overlap with the orthographic projection of the main resistor structure; The first jumper resistor is located between the first sub-resistance structure and the second sub-resistance structure; the second jumper resistor is located between the first sub-resistance structure and the second sub-resistance structure.

6. The semiconductor test structure according to claim 5, characterized in that: The first sub-resistance structure comprises a plurality of first sub-resistance units and a first extension branch extending along the first direction, and the head ends of the plurality of first sub-resistance units are respectively connected to the first extension branch; The second sub-resistance structure comprises a plurality of second sub-resistance units and a second extension branch extending along the first direction, and the head ends of the plurality of second sub-resistance units are respectively connected to the second extension branch; The first auxiliary resistance unit extends along the second direction and is located on two sides of the adjacent main resistance unit; The second auxiliary resistance unit extends into the main resistance unit along the second direction.

7. The semiconductor test structure according to claim 6, characterized in that: The second sub-resistance structure further includes a middle extension branch, the middle extension branch is located on the symmetry axis of the second extension branch and extends along the second direction; A head end of the middle extension branch is connected to the second extension branch, and a tail end of the middle extension branch is connected to the third pad.

8. The semiconductor test structure according to claim 6, characterized in that: The first sub-resistance structure further includes a first contact electrode and a second contact electrode, the first contact electrode is located at the end of the first first sub-resistance unit, and the second contact electrode is located at the head end of the second extension branch; The second sub-resistance structure further includes a third contact electrode and a fourth contact electrode, the third contact electrode is located at the end of the last first sub-resistance unit, and the fourth contact electrode is located at the end of the second extension branch; Both ends of the first jumper resistor are connected to the first contact electrode and the second contact electrode respectively, and both ends of the second jumper resistor are connected to the third contact electrode and the fourth contact electrode respectively.

9. A method for testing a semiconductor structure, characterized in that: A method for testing a semiconductor structure is performed using the semiconductor test structure according to any one of claims 1 to 8, the method comprising: Applying a first voltage to the first pad, applying a second voltage to the second pad, applying a third voltage to the third pad, obtaining a current of the second pad to test the resistance of the semiconductor structure test method; and / or A fourth voltage is applied to the first pad, a fifth voltage is applied to the second pad, a sixth voltage is applied to the third pad, and a current of the third pad is obtained to test the capacitance of the semiconductor structure test method.

10. The method for testing a semiconductor structure according to claim 9, characterized in that: The first voltage is 0V, the second voltage is 1.8V, and the third voltage is 0V; and / or The first voltage is 0V, the second voltage is 0V, and the third voltage is 1.8V.

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