Dual-power supply circuit, control signal transmission circuit, chip, dual-power supply method and control signal transmission method

Abstract

The invention provides a dual-power supply circuit, a control signal transmission circuit, a chip, a dual-power supply method and a control signal transmission method. A dual power supply circuit may include: a first power supply circuit powered using a first power supply; a second power supply circuit which supplies power by using a second power supply different from the first power supply; the first anomaly detection circuit is used for obtaining a first anomaly signal indicating whether the first power supply is abnormal or not; the logic circuit is used for obtaining an abnormal control signal based on the first abnormal signal; and a first level conversion circuit for obtaining a control signal for delivery to the second power supply circuit based on an output of the first power supply circuit and based on the abnormal control signal.

Description

Technical Field

[0001] The present disclosure relates to a dual power supply circuit, a control signal transmission circuit, a chip, a dual power supply method, and a control signal transmission method. Background Art

[0002] More and more circuits or chips are powered by dual power supplies. In the case of dual power supplies, control signals may need to be transmitted between two power domains. A circuit or method is desired to monitor abnormal conditions of the power supply to ensure the safety of the circuit. Summary of the invention

[0003] According to one aspect of the present disclosure, a dual power supply circuit is provided, comprising: a first power supply circuit, the first power supply circuit being powered by a first power supply; a second power supply circuit, the second power supply circuit being powered by a second power supply different from the first power supply; a first abnormality detection circuit, the first abnormality detection circuit being used to obtain a first abnormality signal indicating whether the first power supply is abnormal; a logic circuit, the logic circuit being used to obtain an abnormality control signal based on the first abnormality signal; and a first level conversion circuit, the first level conversion circuit being used to obtain a control signal for transmission to the second power supply circuit based on an output of the first power supply circuit and based on the abnormality control signal.

[0004] According to another aspect of the present disclosure, a control signal transmission circuit for a dual power supply circuit is provided, comprising: a first abnormality detection circuit, the first abnormality detection circuit being used to obtain a first abnormality signal indicating whether a first power supply is abnormal; a logic circuit, the logic circuit being used to obtain an abnormality control signal based on the first abnormality signal; and a first level conversion circuit, the first level conversion circuit being used to obtain a control signal for transmission to a second power supply circuit based on an output of a first power supply circuit and based on the abnormal control signal, wherein the first power supply circuit is powered by the first power supply and the second power supply circuit is powered by a second power supply different from the first power supply.

[0005] According to yet another aspect of the present disclosure, a chip is provided, including the dual power supply circuit according to the embodiment of the present disclosure or the control signal transmission circuit for the dual power supply circuit according to the embodiment of the present disclosure.

[0006] According to yet another aspect of the present disclosure, a dual power supply method is provided, comprising: using a first power supply to power a first power supply circuit; using a second power supply different from the first power supply to power a second power supply circuit; obtaining a first abnormality signal indicating whether the first power supply is abnormal; obtaining the abnormality control signal based on the first abnormality signal; and obtaining a control signal for transmission to the second power supply circuit based on the output of the first power supply circuit and based on the abnormality control signal.

[0007] According to another aspect of the present disclosure, a control signal transmission method for a dual power supply circuit is provided, comprising: obtaining a first abnormal signal indicating whether a first power supply is abnormal; obtaining an abnormal control signal based on the first abnormal signal; and obtaining a control signal for transmission to a second power supply circuit based on an output of a first power supply circuit and based on the abnormal control signal, wherein the first power supply circuit is powered by the first power supply and the second power supply circuit is powered by a second power supply different from the first power supply.

[0008] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic circuit diagram illustrating a dual power supply according to one or more embodiments of the present disclosure;

[0011] Figure 2A-2G is a schematic diagram illustrating a first level converter for a dual power supply circuit according to one or more embodiments of the present disclosure;

[0012] Figure 3 is a schematic diagram illustrating a second level converter for a dual power supply circuit according to one or more embodiments of the present disclosure;

[0013] Figure 4 is a flow chart illustrating a dual power supply method according to an exemplary embodiment of the present disclosure;

[0014] Figure 5 is a flowchart illustrating a control signal transfer method according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part without departing from the teaching of the present disclosure.

[0016] Spatially relative terms such as "below," "beneath," "lower," "below," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figure. It will be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is flipped, the element described as "below other elements or features" or "below other elements or features" or "below other elements or features" will be oriented to "above other elements or features." Therefore, the exemplary terms "below" and "below" can cover both orientations above and below. Terms such as "before" or "before" and "after" or "followed by" can be similarly used, for example, to indicate the order in which light passes through the elements. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used in this article are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between two layers,” it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0017] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "one" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" specify the existence of the features, integral bodies, steps, operations, elements and / or parts when used in this specification, but do not exclude the existence of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups or add one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" includes only A, only B, and both A and B.

[0018] It will be understood that when an element or layer is referred to as being "on another element or layer," "connected to another element or layer," "coupled to another element or layer," or "adjacent to another element or layer," it may be directly on another element or layer, directly connected to another element or layer, directly coupled to another element or layer, or directly adjacent to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on another element or layer," "directly connected to another element or layer," "directly coupled to another element or layer," or "directly adjacent to another element or layer," there are no intermediate elements or layers. However, in no case should "on..." or "directly on..." be interpreted as requiring that one layer completely cover the layer below.

[0019] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the zones illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the zones of the device and are not intended to limit the scope of the present disclosure.

[0020] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0021] Reference below Figure 1 The circuit implementation of the dual power supply scheme according to one or more embodiments of the present disclosure is described. Figure 1 As shown, the dual power supply circuit 100 may include a first power supply circuit 110 , a second power supply circuit 120 , a first abnormality detection circuit 130 , a logic circuit 140 and a first level conversion circuit 150 .

[0022] The first power supply circuit 110 can be powered by a first power supply, and the second power supply circuit 120 can be powered by a second power supply different from the first power supply. The first abnormality detection circuit 130 can be used to obtain a first abnormality signal indicating whether the first power supply is abnormal. The logic circuit 140 can be used to obtain an abnormality control signal based on the first abnormality signal. The first level conversion circuit (levelshift1) 150 can be used to obtain a control signal for transmission to the second power supply circuit based on the output of the first power supply circuit and based on the abnormality control signal.

[0023] Exemplarily, the first power supply circuit 110 can be used as a control part, which can be, for example, a digital circuit, which can be responsible for communication and logical operations. The second power supply circuit 120 can be used as an execution part, which can be, for example, an analog circuit, which can use a higher analog voltage, and is responsible for the output and execution of analog quantities. The output of the first power supply circuit can be used as an intermediate signal for generating a control signal, and the control signal is input to the second power supply circuit. In other words, the execution of the second power supply circuit can be controlled by the first power supply circuit, and through the design of the abnormal control signal, the execution of the second power supply circuit can be guaranteed when an abnormality occurs in the first power supply, thereby ensuring the safety of the circuit.

[0024] In various fields, such as in more and more chips used in industry and automobiles, dual power supply solutions are adopted. For example, the part powered by the first power supply, such as the digital part, is responsible for communication and logical operations, and is powered by the first power supply, such as the digital power supply VLOGIC; the part powered by the second power supply, such as the execution part, is responsible for the output and execution of analog quantities, and is powered by the second voltage, such as the analog high voltage power supply VDD. The control signal needs to be transferred from the first power supply domain (such as the digital domain) to the second power supply domain (such as the analog domain), and it is necessary to consider that the two power supplies can also make the execution unit of the analog domain meet functional safety under different power-on and power-off conditions.

[0025] Return to reference Figure 1 , and continuing the example described above where the first power supply circuit 110 is a digital circuit connected to the digital power signal VLOGIC and the second power supply circuit 120 is an analog circuit connected to the analog power signal VDD, at this time, the first abnormality detection circuit 130 can also be called a digital power normal check circuit, which outputs the first abnormality signal VLOGIC_OK. As an example, VLOGIC_OK=1 indicates that power-on is completed, and VLOGIC_OK=0 indicates that power-on is abnormal, and the present disclosure is not limited thereto.

[0026] Exemplarily, the first level conversion circuit can be used to: when the abnormal control signal indicates no abnormality, perform a level conversion function based on the output of the first power supply to obtain a converted signal as the control signal; and when the abnormal control signal indicates the presence of an abnormality, obtain a default level value as the control signal. Return to reference Figure 1 , the logic circuit 140 can obtain the abnormal control signal ALL_Power_OK based on the first abnormal signal VLOGIC_OK, which is used to input the abnormal control pin default value keep of the first level conversion circuit 150. The abnormal control pin default value keep can be used to make the first level conversion circuit output a default value when an abnormality exists.

[0027] According to the embodiments of the present disclosure, by monitoring the analog power supply VDD and the digital power supply VLOGIC, a power supply monitoring signal is generated and acts on the digital-to-analog interface for control signal transmission. When a power supply abnormality occurs, the control signal received by the execution unit will be fixed in a functionally safe state, thereby eliminating the hidden danger of danger when the power supply is abnormally cut off. At the same time, the instructions in the digital register can be executed normally after the power is restored.

[0028] For dual-power-supply chips, if the digital module loses power abnormally, the signal transmitted at the digital-to-analog interface will be uncontrollably disordered. If the uncontrollable signal is transmitted to the analog execution part (the VDD power supply of the execution part is normal), uncontrolled execution will occur, which is very dangerous for subsequent circuits and application scenarios. Usually, the manual of the dual-power chip will require a power-on sequence and a power-off sequence, but does not provide possible situations in the event of an abnormal power failure. According to an embodiment of the present disclosure, during the control signal transmission process, the power supply condition is monitored, and instructions that comply with functional safety are given at the digital-to-analog interface. Exemplarily, this can include signal transmission when the power supply is normal, and resetting the signal default value in the event of an abnormal power supply condition.

[0029] According to one or more embodiments of the present disclosure, a solution is proposed for resetting an execution unit to a safe state in the event of power anomaly.

[0030] Combine the following Figure 2A-2D A specific implementation of a first level shifting circuit (levelshift1) according to a specific non-limiting embodiment of the present disclosure is described. Figure 2A A schematic circuit diagram 200 of a first level conversion circuit according to a specific non-limiting embodiment of the present disclosure is shown. The first level conversion circuit can be used to convert control signals at different voltages. The abnormal control signal is represented as an EN signal, and the first level conversion circuit may include an EN pin, which corresponds to Figure 1The default value keep pin in the circuit makes the output value of the first level conversion circuit at the default level value when it is set to the voltage level corresponding to the circuit abnormality. As a specific non-limiting example, the voltage level corresponding to the circuit abnormality can be a low level. In such an example, when EN=1, the level conversion circuit works normally, and when EN=0, the level conversion circuit outputs the default value. Figure 2B As shown, EN can be converted into an inverted signal ENB through an inverter, and then converted into a secondary inverted signal ENBB, so as to be input to Figure 2A In the circuit 200 shown in FIG. Figure 2C As shown, IN can be converted into an inverted signal INB through an inverter, and then converted into a secondary inverted signal INBB, so as to be input to Figure 2A In the circuit 200 shown.

[0031] Return to reference Figure 2A As shown, the circuit can realize control signal conversion under different voltages, and control its working state through the EN pin (or as shown in the figure, the corresponding inverted signal ENB and the secondary inverted signal ENBB). The first level conversion circuit may include an inverter circuit, but the present disclosure is not limited to this. It can be seen that this circuit has no static power consumption.

[0032] Exemplarily, the first level conversion circuit includes a first field effect transistor and a second field effect transistor, and the first field effect transistor and the second field effect transistor are used to make the output value of the first level conversion circuit be at the default level value when the abnormal control signal indicates that an abnormality exists.

[0033] Exemplarily, the first field effect transistor may be a P-type field effect transistor, the second field effect transistor may be an N-type field effect transistor, and the default level value is 0. As can be understood by those skilled in the art, by changing the circuit form, the default level value may also be a high level 1, and the present disclosure is not limited thereto. Figure 2A As shown in the figure, when EN=0, the ENB signal controls the switch states of the NMOS and PMOS connected to the output terminal OUT, and the PMOS is turned off, so that the path connected to VDD is closed to prevent the high level from being transmitted to the output. At the same time, by turning on the NMOS connected to the output terminal OUT, the output OUT is forced to be pulled down to VSS (low level).

[0034] Continuing with the example of the default value = 0, in this case, the normal level conversion function can be performed when EN = 1, and when EN = 0, the output will be forced to 0 regardless of whether the input is 1 or 0. Figure 2DThe logic table shows the effect of the input combination of EN and IN on the output OUT. It can be seen that when EN=0, that is, when the control signal indicates that there is an abnormality, the output OUT is always 0 regardless of the value of IN. When EN=1 and IN=1, the output OUT is 1. When EN=1 and IN=0, the output OUT is 0. Figure 2E A simplified schematic diagram of this situation is shown, where 1 represents a high level and 0 represents a low level.

[0035] As another example, there may be a default value=1. Figure 2F An example of a circuit diagram 210 of a first level shifter having a default value of defaultvalue=1 is shown, and Figure 2G The following table shows the effect of the input combination of EN and IN on the output OUT in this case. It can be understood that the same Figure 2B-2C Similar circuit diagrams are used to obtain inverted signals ENB, ENBB, INB, INBB, etc., and are not described again in detail. Figure 2G It can be seen that when EN=0, that is, when the control signal indicates that there is an abnormality, the output OUT is always 1 regardless of the value of IN. When EN=1 and IN=1, the output OUT is 1. When EN=1 and IN=0, the output OUT is 0.

[0036] Return to reference Figure 2A , it can also be seen that when the control pin EN=1, the circuit performs the normal level conversion function. At this time, the circuit determines the level of the output OUT according to the state of the input signal IN (1 or 0), completing the level conversion task. When the control pin EN=0**, regardless of whether the input IN is high level (1) or low level (0), the output OUT will be forced to low level (0), that is, "default value=0". This design is used to ensure that the circuit can be locked to the default state under certain circumstances to prevent the output from showing uncertain signals.

[0037] Exemplarily, the dual power supply circuit according to the embodiment of the present disclosure may further include a second power supply detection circuit. Figure 1 The dual power supply circuit 100 may further include a second power supply detection circuit 160, which is used to obtain a second abnormality signal VDD_OK indicating whether the second power supply is abnormal. In such an embodiment, the logic circuit 140 may also be used to obtain the abnormality control signal based on the first abnormality signal VLOGIC_OK and the second abnormality signal VDD_OK.

[0038] Return to reference Figure 1The control signal transmission scheme provided for the dual power supply system according to the embodiment of the present disclosure is further described, which can still meet the functional safety design under the condition of power supply abnormality. Figure 1 As shown, the second power supply detection circuit 160, which can also be referred to as an analog power normal detection circuit, outputs a second abnormal signal VDD_OK. Exemplarily, VDD_OK=1 indicates that power-on is complete, and VDD_OK=0 indicates that power-on is abnormal. The logic circuit 140 can process the first abnormal signal VLOGIC_OK of the first power domain (e.g., the VLOGIC domain) and the second abnormal signal VDD_OK of the second power domain (e.g., the VDD domain). The first abnormal analog signal VLOGIC_OK_A (not shown) that reaches the analog domain through the second level converter can be obtained, and a logical AND operation is performed with VDD_OK to generate an ALL_Power_OK signal.

[0039] The following situations may occur when the power supply is in use:

[0040] VLOGIC Power Supply VDD power supply Control section Execution 1 normal normal normal normal 2 normal abnormal normal Not Executed 3 abnormal normal abnormal Locked state 4 abnormal abnormal abnormal Not Executed

[0041] Case 1 corresponds to a completely normal situation. For case 2, when VDD is abnormal, the execution part will not output the instructions of the control unit, so it complies with functional safety. For case 3, when VLOGIC is abnormal, the control part is abnormal, the VLOGIC power check unit will detect the VLOGIC abnormality and output a low level. At this time, the ALL_Power_OK signal is low, and the default value keep signal in the second level converter is controlled to allow the execution part to read the pre-defined default value of the control that complies with functional safety. At this time, the control signal read by the execution unit is a safety signal and has nothing to do with the abnormal signal output by the control part. For case 4, VLGOIC and VDD are abnormal at the same time, and the execution part does not execute, which also meets the requirements of functional safety.

[0042] It can be seen that according to the exemplary embodiments of the present disclosure, a safe dual-power supply circuit can be implemented.

[0043] According to some embodiments, the logic circuit may include a second level conversion circuit. Figure 1 As shown in , the exemplary second level conversion circuit levelshift2 can be used to lock the output level of the second level conversion circuit to a predetermined value for indicating an abnormal control signal when the input level of the second level conversion circuit is lower than a threshold, which can be achieved by including a self-locking circuit.

[0044] Figure 3 According to some exemplary embodiments, Figure 1The specific implementation of the second level converter (levelshift2) shown in FIG. 1 , wherein VDD represents the second power supply (high level power supply) of the circuit, VSS, VSS1, and VSS2 represent the low level ground of the circuit as the reference voltage of the circuit, IN represents the input signal, and OUT represents the output signal. Figure 3 As shown, the circuit can realize the high-low level conversion function. As an optional embodiment, the second level converter can be designed so that when VLOGIC is powered off, the output will be 0 regardless of the input. Thus, the problem that the output of the first level converter circuit is uncertain when VLOGIC is powered off can be solved. Thus, the ALL_Power_OK signal can be kept at 0, thereby realizing the function of keeping the default value in the first level converter.

[0045] Exemplarily, the self-locking circuit may include a third field effect transistor. Exemplarily, the self-locking circuit may be a circuit with a pull-down function, such as a pull-down NMOS, so that when the first power supply is powered off, the output is forced to 0. In such an example, the third field effect transistor is an N-type field effect transistor, and the predetermined value is 0.

[0046] According to some exemplary embodiments, the second level conversion circuit further includes a resistor connected in series with the self-locking circuit. Figure 3 , a resistor can also be connected in series at node A. In particular, a large resistor can be connected in series to reduce power consumption. When the input is 1 and the voltage of the first power supply VLOGIC is low, the PMOS may be normally open, resulting in continuous current consumption. The large resistor limits the size of this current, thereby reducing power consumption. By connecting a large resistor in series, the problem of normally open current that occurs when the first power supply (VLOGIC) is lower than the second power supply (VDD) and the input signal IN is 1 can be solved.

[0047] Optionally, a pull-down NMOS can also be added at point B. In such an embodiment, the function of the pull-down NMOS is to enhance the pull-down capability when the input is 0. Since a large resistor is connected in series with the PMOS, when the input is 0, the shutdown of the PMOS may be affected by the large resistor, resulting in a weak pull-down capability. Adding a pull-down NMOS can ensure that when the input is 0, the output is effectively pulled down to 0, and the output can be kept at 0 regardless of whether VLOGIC is powered off, thereby ensuring the reliability of the circuit. When the input signal IN is 0, the problem of weak pull-down capability will be caused due to the addition of a large resistor to the PMOS. After adding the resistor, normal conversion function can be achieved regardless of whether VLOGIC is greater than VDD or VLOGIC is less than VDD. And when VLOGIC is powered off, the output will be forced to 0, and the power consumption is extremely low.

[0048] When VLOGIC is powered off, the output will be forced to 0 regardless of whether the input is high or low. This function is achieved by the pull-down NMOS at node B. When VLOGIC is powered off, the PMOS may not work properly, and the pull-down NMOS ensures that the output is forced to 0, avoiding the dangerous situation of high and low uncertainties. This design also ensures that the power consumption of the circuit is extremely low when it is powered off.

[0049] According to some exemplary embodiments, the first power supply circuit is a digital circuit, and the second power supply circuit is an analog circuit. Exemplarily, the voltage of the first power supply may be lower than the voltage of the second power supply.

[0050] According to one or more embodiments of the present disclosure, there is also provided a control signal transmission circuit for a dual power supply circuit, comprising: a first abnormality detection circuit, the first abnormality detection circuit being used to obtain a first abnormality signal indicating whether a first power supply is abnormal; a logic circuit, the logic circuit being used to obtain an abnormality control signal based on the first abnormality signal; and a first level conversion circuit, the first level conversion circuit being used to obtain a control signal for transmission to a second power supply circuit based on an output of a first power supply circuit and based on the abnormal control signal, wherein the first power supply circuit is powered by the first power supply and the second power supply circuit is powered by a second power supply different from the first power supply.

[0051] According to one or more embodiments of the present disclosure, by cleverly designing control signal transmission in a dual power system and using different types of level converters, the system can maintain functional safety control under different power supply conditions, including abnormal power failure conditions. The chip can be safely used in industry and automobiles, especially in situations where the execution unit is high voltage or ultra-high voltage. The safety and adaptability of the chip are greatly enhanced.

[0052] According to some alternative embodiments of the present disclosure, first level converters with different structures may be used, as long as they have a default value retention function under the first power domain.

[0053] According to some alternative embodiments of the present disclosure, a second level converter with a different structure may be used, and it is only necessary to keep the output forced to a default value (eg, 0) when VLOGIC is powered off.

[0054] According to some alternative embodiments of the present disclosure, different types of logic combinations may be used to allow the VLOGIC and VDD check circuits to recognize the ALL_Power_OK signal.

[0055] According to some alternative embodiments of the present disclosure, different power supply check circuits may be used.

[0056] According to some embodiments of the present disclosure, a control signal can be transmitted through a level converter by using a dual power supply control signal transmission method, while maintaining zero power consumption.

[0057] According to some embodiments of the present disclosure, it is possible to identify power signal abnormality in a dual power system, and control the level converter to work normally or execute a default value through a power abnormality control signal.

[0058] According to some embodiments of the present disclosure, the level conversion portion does not consume additional power consumption.

[0059] According to some embodiments of the present disclosure, the functional safety characteristics of the execution part can be realized.

[0060] refer to Figure 1-Figure 3 The described circuit may be used to implement the dual power supply method 400 according to one or more embodiments of the present disclosure. Figure 4 As shown, the various steps of the dual power supply method 400 are shown. It can be understood that, as will be further described below, Figure 1 As described, the various steps of the dual power supply method 400 can be implemented using corresponding parts or elements of the circuit to be described below, and the description of other embodiments or variations of the dual power supply circuit 100 can also be applied to the dual power supply method 400, which will not be repeated in this article.

[0061] refer to Figure 4 , at step 410, using a first power supply to power a first power supply circuit;

[0062] At step 420, a second power supply circuit is powered using a second power supply different from the first power supply;

[0063] At step 430, a first abnormality signal indicating whether the first power supply is abnormal is obtained;

[0064] At step 440, the abnormal control signal is obtained based on the first abnormal signal; and

[0065] At step 450, a control signal for transmission to the second power supply circuit is obtained based on the output of the first power supply circuit and based on the abnormal control signal.

[0066] refer to Figure 1-Figure 3 The described circuit and its variations may also be used to implement the control signal transmission method 500 for a dual power supply circuit according to one or more embodiments of the present disclosure.

[0067] refer to Figure 5 , at step 510, obtaining a first abnormal signal indicating whether the first power supply is abnormal;

[0068] At step 520, an abnormal control signal is obtained based on the first abnormal signal; and

[0069] At step 530, a control signal for transmission to a second power supply circuit is obtained based on an output of a first power supply circuit and based on the abnormal control signal, wherein the first power supply circuit is powered by the first power supply and the second power supply circuit is powered by a second power supply different from the first power supply.

[0070] It will be appreciated that although the steps are described in a particular order, Figure 4 and Figure 5 The steps in the embodiment of the present invention are shown in the following order, but this does not require that the steps must be performed in such an order. For example, some of the steps can be performed in a reverse order, and / or some of the steps can be combined for execution.

[0071] According to one or more embodiments of the present disclosure, a chip is further provided, including the dual power supply circuit according to the embodiment of the present disclosure or the control signal transmission circuit for the dual power supply circuit according to the embodiment of the present disclosure.

[0072] According to one or more embodiments of the present disclosure, a control method or a control signal transmission method that complies with functional safety can be provided for a dual power supply system.

[0073] Although the present disclosure has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description should be considered illustrative and schematic, not restrictive; the present disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure and the appended claims, those skilled in the art will be able to understand and implement variations to the disclosed embodiments when practicing the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps that are not listed, the indefinite article "a" or "an" does not exclude a plurality, the term "plurality" means two or more, and the term "based on" should be interpreted as "based at least in part on". The mere fact that certain measures are recorded in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A dual power supply circuit, comprising: A first power supply circuit, wherein the first power supply circuit is powered by a first power supply; a second power supply circuit, wherein the second power supply circuit is powered by a second power supply different from the first power supply; a first abnormality detection circuit, the first abnormality detection circuit being used to obtain a first abnormality signal indicating whether the first power supply is abnormal; a logic circuit, the logic circuit being configured to obtain an abnormal control signal based on the first abnormal signal; as well as A first level conversion circuit is configured to obtain a control signal for transmitting to the second power supply circuit based on the output of the first power supply circuit and based on the abnormal control signal.

2. The dual power supply circuit according to claim 1, wherein: The first level conversion circuit is used for: When the abnormality control signal indicates no abnormality, performing a level conversion function based on the output of the first power supply to obtain a converted signal as the control signal; and When the abnormal control signal indicates that an abnormality exists, a default level value is obtained as the control signal.

3. The dual power supply circuit according to claim 2, wherein: The first level conversion circuit includes a first field effect transistor and a second field effect transistor, and the first field effect transistor and the second field effect transistor are used to make the output value of the first level conversion circuit be at the default level value when the abnormality control signal indicates that an abnormality exists.

4. The dual power supply circuit according to claim 3, wherein: The first field effect transistor is a P-type field effect transistor, the second field effect transistor is an N-type field effect transistor, and the default level value is 0.

5. The dual power supply circuit according to any one of claims 1 to 4, further comprising: a second power supply detection circuit, the second power supply detection circuit being used to obtain a second abnormality signal indicating whether the second power supply is abnormal; and The logic circuit is used to obtain the abnormal control signal based on the first abnormal signal and the second abnormal signal.

6. The dual power supply circuit according to any one of claims 1 to 4, wherein: The logic circuit includes a second level conversion circuit, and the second level conversion circuit includes a self-locking circuit, and the self-locking circuit is used to lock the output level of the second level conversion circuit to a predetermined value for indicating an abnormal control signal when the input level of the second level conversion circuit is lower than a threshold.

7. The dual power supply circuit according to claim 6, wherein: The self-locking circuit includes a third field effect transistor.

8. The dual power supply circuit according to claim 7, wherein: The third field effect transistor is an N-type field effect transistor, and the predetermined value is 0.

9. The dual power supply circuit according to claim 6, wherein: The second level conversion circuit further includes a resistor connected in series with the self-locking circuit.

10. The dual power supply circuit according to any one of claims 1 to 4, wherein: The first power supply circuit is a digital circuit, and the second power supply circuit is an analog circuit.

11. A control signal transmission circuit for a dual power supply circuit, comprising: a first abnormality detection circuit, the first abnormality detection circuit being used to obtain a first abnormality signal indicating whether the first power supply is abnormal; a logic circuit, the logic circuit being configured to obtain an abnormal control signal based on the first abnormal signal; as well as A first level conversion circuit, the first level conversion circuit is used to obtain a control signal for transmission to a second power supply circuit based on an output of a first power supply circuit and based on the abnormal control signal, wherein the first power supply circuit is powered by the first power supply and the second power supply circuit is powered by a second power supply different from the first power supply.

12. A chip, comprising the dual power supply circuit according to any one of claims 1 to 10 or the control signal transmission circuit for a dual power supply circuit according to claim 7.

13. A dual power supply method, comprising: Using a first power supply to supply power to a first power supply circuit; using a second power supply different from the first power supply to power a second power supply circuit; Obtaining a first abnormality signal indicating whether the first power supply is abnormal; obtaining the abnormal control signal based on the first abnormal signal; as well as Based on the output of the first power supply circuit and based on the abnormal control signal, a control signal for transmission to the second power supply circuit is obtained.

14. A control signal transmission method for a dual power supply circuit, comprising: obtaining a first abnormality signal indicating whether the first power supply is abnormal; obtaining an abnormal control signal based on the first abnormal signal; as well as Based on the output of a first power supply circuit and based on the abnormal control signal, a control signal for transmission to a second power supply circuit is obtained, wherein the first power supply circuit is powered by the first power supply and the second power supply circuit is powered by a second power supply different from the first power supply.

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