Optical interconnection system, optical communication control method, device and equipment, medium and product

Abstract

The invention discloses an optical interconnection system, an optical communication control method, device and equipment, a medium and a product, and relates to the technical field of communication, the optical interconnection system comprises first optical communication equipment and second optical communication equipment, the first optical communication equipment comprises a first chip, a first optical module and a first control module which are mutually connected, the second optical communication equipment comprises a second chip, a second optical module and a second control module which are connected with one another, and the first control module is used for detecting that the first optical module is in place through the first control signal and detecting the state of a driver chip in the first optical module through the second control signal so as to judge whether a driver in the first optical module works normally or not; and if yes, controlling a port corresponding to the first chip to exit from the electrical idle state through a third control signal, controlling the first chip to start link training, and after the link training is completed, establishing communication between the first chip and the second chip. According to the invention, the optical interconnection system is prevented from running in a speed reduction state.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and more specifically, to an optical interconnection system, an optical communication control method, a device and equipment, a medium and a product. Background Art

[0002] Optical interconnect technology has the characteristics of low loss and can support long-distance transmission of PCIe (Peripheral Component Interconnect Express) signals. When the device is connected, the PCIe link will start link training until a specific rate. However, after the optical module is inserted, it will be powered on. It takes a certain amount of time for the internal driver and other chips to enter the normal working state, and the time for different drivers inside the optical module to enter the normal working state from power-on is also inconsistent. Before the optical module enters the normal working state, it may cause abnormalities in the electro-optical conversion process of high-speed signals, resulting in bit errors. PCIe link training starts from low speed to high speed, and the link rate will be adjusted according to the link state. That is, if the PCIe chip determines in the link that the current link cannot support the highest rate supported by the chip, it will reduce the link rate. Therefore, for the PCIe optical interconnect system, it is very easy to cause the PCIe link to complete link training and reduce the link rate before the chip inside the optical module reaches the normal working state, that is, it fails to enter the highest rate state supported by the link, so that the system runs in a reduced speed state.

[0003] Therefore, how to prevent the optical interconnection system from operating in a reduced speed state is a technical problem that needs to be solved by those skilled in the art. Summary of the invention

[0004] The object of the present invention is to provide an optical interconnection system, an optical communication control method, a device and equipment, a medium and a product, which prevent the optical interconnection system from running in a reduced speed state.

[0005] To achieve the above-mentioned object, the present invention provides an optical interconnection system, comprising a first optical communication device and a second optical communication device, the first optical communication device comprising a first chip, a first optical module, and a first control module connected to each other, the second optical communication device comprising a second chip, a second optical module, and a second control module connected to each other, the first optical communication device and the second optical communication device are connected via the first optical module and the second optical module, and the first optical module and the second optical module communicate with each other via optical signals;

[0006] The first control module is used for, in the case where the first optical module is not in place and the second optical module is in place, after the first optical module is inserted, detecting the presence of the first optical module through a first control signal, detecting the state of the internal driver chip of the first optical module through a second control signal, and judging whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module; if so, controlling the port corresponding to the first chip to exit the electrical idle state and controlling the first chip to start link training through a third control signal, and when the link training is completed, the first chip establishes communication with the second chip.

[0007] Wherein, when both the first optical module and the second optical module are in place, when the first optical module is unplugged, the port corresponding to the first chip enters an electrical idle state;

[0008] The first control module is further used for: detecting through the first control signal that the first optical module is not in place, and controlling the first chip to stop receiving end detection through the third control signal.

[0009] Among them, the first control module is also used for: when the first optical module is in place and the port corresponding to the first chip enters an electrical idle state, detecting whether there is an input optical signal at the receiving end of the first optical module through a second control signal; if so, restoring the power supply of the internal driver of the first optical module through the second control signal; detecting the internal driver state of the first optical module through the second control signal, and judging whether the internal driver of the first optical module is working normally according to the internal driver state of the first optical module; if so, controlling the port corresponding to the first chip to exit the electrical idle state and start link training through a third control signal, and when the link training is completed, the first chip establishes communication with the second chip.

[0010] Wherein, when both the first optical module and the second optical module are in place, when the second optical module is unplugged, the port corresponding to the first chip enters an electrical idle state;

[0011] The first control module is also used to: after detecting that the first chip enters an electrical idle state through a third control signal, detect that the first optical module is in place through a first control signal, and shut down the power supply of the internal driver of the first optical module and maintain the power supply of the receiving end of the first optical module through a second control signal.

[0012] Among them, the first control module is also used for: when neither the first optical module nor the second optical module is in place, after the first optical module is inserted, detecting that the first optical module is in place through the first control signal; detecting the state of the internal driver chip of the first optical module through the second control signal, and judging whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module; if so, detecting whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if so, controlling the first chip to exit the electrical idle state and start link training through the third control signal, and when the link training is completed, the first chip establishes communication with the second chip.

[0013] Among them, the first control module is connected to the in-position pin of the first optical module through a first control signal, the first control module is connected to the integrated circuit pin of the first optical module through a second control signal, and the first control module is connected to the integrated circuit pin and / or serial communication pin of the first chip through a third control signal, and the serial communication pin includes a serial data bus pin and / or a universal asynchronous receiver / transmitter serial communication pin.

[0014] The first control module is integrated into the first chip, or the first control module is a chip independent of the first chip;

[0015] If the first control module is a chip independent of the first chip, the first control module includes a complex programmable logic device and / or a field programmable gate array.

[0016] To achieve the above object, the present invention provides an optical communication control method, which is applied to a first optical communication device, and the method includes:

[0017] In the case where the first optical module is not in place and the second optical module is in place, when the first optical module is inserted, the first control module in the first optical communication device detects that the first optical module is in place through a first control signal; wherein the first optical module is an optical module in the first optical communication device, and the second optical module is an optical module in the second optical communication device connected to the first optical communication device;

[0018] The first control module detects the state of the driver chip inside the first optical module through the second control signal, and determines whether the driver inside the first optical module works normally according to the state of the driver chip inside the first optical module;

[0019] If so, the first control module controls the port corresponding to the first chip in the first optical communication device to exit the electrical idle state and controls the first chip in the first optical communication device to start link training through the third control signal. When the link training is completed, the first chip in the first optical communication device establishes communication with the second chip in the second optical communication device.

[0020] Among them, it also includes:

[0021] During the link training process of the first chip, the communication rate between the first chip and the second chip is increased.

[0022] Among them, it also includes:

[0023] When both the first optical module and the second optical module are in place, when the first optical module is unplugged, the port corresponding to the first chip enters an electrically idle state, the first control module detects through the first control signal that the first optical module is not in place, and controls the first chip to stop receiving end detection through the third control signal.

[0024] Wherein, if the first optical module is unplugged and then inserted, after the link training is completed, the first chip in the first optical communication device establishes communication with the second chip in the second optical communication device, including:

[0025] When the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, the first optical module communicates with the second optical module through optical signals, and the communication rate between the first chip in the first optical communication device and the second chip in the second optical communication device is restored to the rate before the first optical module is unplugged.

[0026] Among them, it also includes:

[0027] When the first optical module is in place and the port corresponding to the first chip enters an electrical idle state, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal;

[0028] If it exists, the first control module restores the power supply of the internal driver of the first optical module through the second control signal;

[0029] The first control module detects the internal driver state of the first optical module through the second control signal, and determines whether the internal driver of the first optical module works normally according to the internal driver state of the first optical module;

[0030] If so, the first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal. When the link training is completed, the first chip establishes communication with the second chip.

[0031] Among them, it also includes:

[0032] When both the first optical module and the second optical module are in place, when the second optical module is unplugged, the port corresponding to the first chip enters an electrical idle state;

[0033] After the first control module detects through the third control signal that the first chip enters the electrical idle state, it detects through the first control signal that the first optical module is in place, and through the second control signal turns off the power supply of the internal driver of the first optical module and keeps the receiving end of the first optical module powered.

[0034] Wherein, if the second optical module is unplugged and then inserted, after the link training is completed, the first chip establishes communication with the second chip, including:

[0035] When the link training is completed, the first chip communicates with the first optical module via electrical signals, the first optical module communicates with the second optical module via optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the second optical module is unplugged.

[0036] Among them, it also includes:

[0037] In the case that neither the first optical module nor the second optical module is in place, when the first optical module is inserted, the first control module detects that the first optical module is in place through the first control signal;

[0038] The first control module detects the state of the driver chip inside the first optical module through the second control signal, and determines whether the driver inside the first optical module works normally according to the state of the driver chip inside the first optical module;

[0039] If so, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal;

[0040] If so, the first control module controls the first chip to exit the electrical idle state and start link training through the third control signal. When the link training is completed, the first chip establishes communication with the second chip.

[0041] If both the first optical module and the second optical module are unplugged and then inserted, when the link training is completed, the first chip establishes communication with the second chip, including:

[0042] When the link training is completed, the first chip communicates with the first optical module via electrical signals, and the first optical module communicates with the second optical module via optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the first optical module and the second optical module are unplugged.

[0043] To achieve the above object, the present invention provides an optical communication control device, which is applied to a first optical communication device, and the device includes:

[0044] A first detection unit is used to detect that the first optical module is in place through a first control signal when the first optical module is pulled out and then inserted when the first optical module is not in place and the second optical module is in place; wherein the first optical module is an optical module in the first optical communication device, and the second optical module is an optical module in the second optical communication device connected to the first optical communication device;

[0045] The first judgment unit is used to detect the state of the driver chip inside the first optical module through the second control signal, and judge whether the driver inside the first optical module works normally according to the state of the driver chip inside the first optical module; if so, start the working process of the first control unit;

[0046] The first control unit is used to control the port corresponding to the first chip in the first optical communication device to exit the electrical idle state and control the first chip in the first optical communication device to start link training through a third control signal. When the link training is completed, the first chip in the first optical communication device establishes communication with the second chip in the second optical communication device.

[0047] To achieve the above object, the present invention provides an electronic device, comprising:

[0048] Memory for storing computer programs;

[0049] The processor is used to implement the steps performed by the above-mentioned optical communication control method when executing the computer program.

[0050] To achieve the above object, the present invention provides a non-volatile storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps performed by the above optical communication control method are implemented.

[0051] To achieve the above object, the present invention provides a computer program product, including a computer program, which implements the steps performed by the above optical communication control method when executed by a processor.

[0052] It can be seen from the above scheme that an optical interconnection system provided by the present invention includes a first optical communication device and a second optical communication device, the first optical communication device includes a first chip, a first optical module, and a first control module connected to each other, the second optical communication device includes a second chip, a second optical module, and a second control module connected to each other, the first optical communication device and the second optical communication device are connected through the first optical module and the second optical module, and the first optical module and the second optical module communicate through optical signals; the first control module is used for detecting the presence of the first optical module through a first control signal when the first optical module is not in place and the second optical module is in place, detecting the state of the internal driver chip of the first optical module through a second control signal after the first optical module is inserted, and judging whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module; if so, controlling the port corresponding to the first chip to exit the electrical idle state and controlling the first chip to start link training through a third control signal, and when the link training is completed, the first chip establishes communication with the second chip.

[0053] The beneficial effect of the present invention is that: in the optical interconnection system provided by the present invention, when the first optical module is not in place and the second optical module is in place, after the first optical module is inserted, the first control module in the first optical communication device controls the first chip to start link training after detecting that the first optical module is in place and the internal driver of the first optical module is working normally, thereby avoiding the first chip starting link training when the first optical module fails to enter the working state normally, resulting in failure to enter the highest rate state supported by the link, so that the communication rate between the first chip and the second chip can reach the maximum rate through training, avoiding the optical interconnection system from running in a reduced speed state. The present invention also discloses an optical communication control method, device, electronic device, non-volatile storage medium and computer program product, which can also achieve the above technical effects.

[0054] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific implementation methods, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:

[0056] Figure 1is a structural diagram of an optical interconnection system according to an exemplary embodiment;

[0057] Figure 2 is a flow chart of a first optical communication control method according to an exemplary embodiment;

[0058] Figure 3 is a flow chart of a second optical communication control method according to an exemplary embodiment;

[0059] Figure 4 is a flow chart of a third optical communication control method according to an exemplary embodiment;

[0060] Figure 5 is a structural diagram of an optical communication control device according to an exemplary embodiment;

[0061] Figure 6 The figure is a structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. In addition, in the embodiments of the present invention, "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0063] This embodiment discloses an optical interconnection system. Figure 1 , which shows an architecture diagram of an optical interconnection system provided by an embodiment of the present invention, such as Figure 1 As shown, the optical interconnection system includes a first optical communication device 10 and a second optical communication device 20. The first optical communication device 10 includes a first chip 101, a first optical module 102, and a first control module 103 that are interconnected. The second optical communication device 20 includes a second chip 201, a second optical module 202, and a second control module 203 that are interconnected. The first optical communication device 10 and the second optical communication device 20 are connected via the first optical module 102 and the second optical module 202, and the first optical module 102 and the second optical module 202 communicate via optical signals.

[0064] In a specific implementation, the first control module 103 controls the first chip 101 and the first optical module 102 respectively through electrical signals, and data is transmitted between the first chip 101 and the first optical module 102 through electrical signals. The second control module 203 controls the second chip 201 and the second optical module 202 respectively through electrical signals, and data is transmitted between the second chip 201 and the second optical module 202 through electrical signals.

[0065] The first optical communication device 10 and the second optical communication device 20 can be devices that comply with the PCIe protocol. Accordingly, the first chip 101 and the second chip 201 can be chips that comply with the PCIe protocol. Data is transmitted between the first chip 101 and the first optical module 102 via electrical signals that comply with the PCIe protocol, and data is transmitted between the second chip 201 and the second optical module 202 via electrical signals that comply with the PCIe protocol.

[0066] The first control module 103 controls the first optical module 102 through the first control signal and the second control signal, and the first control signal and the second control signal are electrical signals. The first control signal is used to detect the in-position state of the first optical module 102, whether it is in position or not in position. As a feasible implementation, the first control module is connected to the in-position pin of the first optical module through the first control signal. In a specific implementation, the first control module 103 is connected to the in-position pin of the first optical module 102 through the first control signal, and the first control module 103 detects the in-position pin of the first optical module 102 through the first control signal, and determines the in-position state of the first optical module 102 according to the level state of the in-position pin. If the in-position pin is a high level, it is determined that the first optical module 102 is in position, and if the in-position pin is a low level, it is determined that the first optical module 102 is not in position. The second control signal is used to detect the state of the internal driver chip of the first optical module 102, and judge whether the internal driver of the first optical module 102 is working normally according to the state of the internal driver chip of the first optical module 102. The internal driver chip of the first optical module 102 can be specifically a microcontroller unit (MCU). As a feasible implementation, the first control module is connected to the integrated circuit pin of the first optical module through the second control signal. In a specific implementation, the first control module 103 is connected to the integrated circuit (Inter-Integrated Circuit, I2C) pin of the first optical module 102 through the second control signal, and the first control module 103 accesses the integrated circuit pin of the first optical module 102 through the second control signal to obtain the internal driver chip state of the first optical module 102.

[0067] The first control module 103 controls the first chip 101 through the third control signal, including controlling the first chip 101 to stop receiving end detection, exit the electrical idle state, start link training, etc. As a feasible implementation, the first control module is connected to the integrated circuit pin and / or serial communication pin of the first chip through the third control signal. In a specific implementation, the first control module 103 is connected to the integrated circuit (I2C) pin or other serial communication pin of the first chip 101 through the third control signal, and the serial communication pin may include a serial data bus (Serial Data Bus, SDB) pin, a universal asynchronous receiver / transmitter (UART) serial communication pin, etc.

[0068] As a feasible implementation, the first control module is integrated into the first chip. In a specific implementation, the first control module 103 can be integrated into the first chip 101 as a functional module. As another feasible implementation, the first control module is a chip independent of the first chip. In a specific implementation, the first control module 103 can also be independent of the first chip 101. If the first control module 103 is independent of the chip 101 of the first chip, the first control module can be a complex programmable logic device (CPLD), a field programmable gate array (FPGA), etc.

[0069] The second control module 203 controls the second optical module 202 through the first control signal and the second control signal, and the first control signal and the second control signal are electrical signals. The first control signal is used to detect the in-position state of the second optical module 202, whether it is in position or not in position. As a feasible implementation, the second control module is connected to the in-position pin of the second optical module through the first control signal. In a specific implementation, the second control module 203 is connected to the in-position pin of the second optical module 202 through the first control signal, and the second control module 203 detects the in-position pin of the second optical module 202 through the first control signal, and determines the in-position state of the second optical module 202 according to the level state of the in-position pin. If the in-position pin is a high level, it is determined that the second optical module 202 is in position, and if the in-position pin is a low level, it is determined that the second optical module 202 is not in position. The second control signal is used to detect the state of the internal driver chip of the second optical module 202, and judge whether the internal driver of the second optical module 202 is working normally according to the state of the internal driver chip of the second optical module 202. The internal driver chip of the second optical module 202 can be specifically a micro control unit. As a feasible implementation, the second control module is connected to the I2C pin of the second optical module through the second control signal. In a specific implementation, the second control module 203 is connected to the I2C pin of the second optical module 202 through the second control signal, and the second control module 203 accesses the I2C pin of the second optical module 202 through the second control signal to obtain the internal driver chip state of the second optical module 202.

[0070] The second control module 203 controls the second chip 201 through the third control signal, including controlling the second chip 201 to stop receiving end detection, exit the electrical idle state, start link training, etc. As a feasible implementation, the second control module is connected to the I2C pin and / or serial communication pin of the second chip through the third control signal. In a specific implementation, the second control module 203 is connected to the I2C pin or other serial communication pin of the second chip 201 through the third control signal, and the serial communication pin may include an SDB pin, a UART serial communication pin, etc.

[0071] As a feasible implementation, the second control module is integrated into the second chip. In a specific implementation, the second control module 203 can be integrated into the second chip 201 as a functional module. As another feasible implementation, the second control module is a chip independent of the second chip. In a specific implementation, the second control module 203 can also be independent of the second chip 201. If the second control module 203 is independent of the chip 201 of the second chip, the second control module can be a CPLD, an FPGA, etc.

[0072] As a feasible implementation mode, when the first optical module and the second optical module are both in place, when the first optical module is unplugged, the port corresponding to the first chip enters an electrically idle state; the first control module is also used to: detect through a first control signal that the first optical module is not in place, and control the first chip to stop receiving end detection through a third control signal.

[0073] From the perspective of the first optical communication device, when the optical modules at both ends are in place, after the optical module at this end (that is, the first optical module) is unplugged, the port in the first chip connected to the first optical module enters an electrically idle state, and after the first control module detects through the first control signal that the first optical module is not in place, it controls the first chip to stop receiving end detection through the third control signal, which helps to reduce the power consumption of the first chip.

[0074] As a feasible implementation mode, the first control module is used for, in the case where the first optical module is not in place and the second optical module is in place, after the first optical module is inserted, detecting the presence of the first optical module through a first control signal, detecting the state of the internal driver chip of the first optical module through a second control signal, and judging whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module; if so, controlling the port corresponding to the first chip to exit the electrical idle state and controlling the first chip to start link training through a third control signal, and when the link training is completed, the first chip establishes communication with the second chip.

[0075] In a specific implementation, from the perspective of the first optical communication device, when the optical module at the other end (i.e., the second optical module) is in place, after the optical module at the local end (i.e., the first optical module) is inserted, the first control module detects that the first optical module is in place through a first control signal, and detects the state of the internal driver chip of the first optical module through a second control signal, including the input end state, the output end state, etc. of the internal driver chip, and determines whether the internal driver of the first optical module is working normally based on the state of the internal driver chip of the first optical module. If the internal driver of the first optical module is working normally, the first chip is controlled to start link training through a third control signal, otherwise the state of the internal driver chip of the first optical module is redetected until the internal driver of the first optical module is working normally.

[0076] During the link training process of the first chip, the communication rate between the first chip and the second chip is gradually increased until the communication rate between the first chip and the second chip reaches the maximum rate. When the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, and the first optical module communicates with the second optical module through optical signals. If the first optical module is plugged in after being unplugged, that is, hot-plugged, when the link training is completed, the communication rate between the first chip and the second chip is restored to the rate before the first optical module is unplugged.

[0077] As a feasible implementation method, when both the first optical module and the second optical module are in place, when the second optical module is unplugged, the port corresponding to the first chip enters an electrically idle state; the first control module is also used to: after detecting through a third control signal that the first chip enters an electrically idle state, detect through a first control signal that the first optical module is in place, and through a second control signal turn off the power supply of the internal driver of the first optical module and keep the receiving end of the first optical module powered.

[0078] In a specific implementation, when the first optical module is in place, after the second optical module is unplugged, the optical signal communication between the first optical module and the second optical module is interrupted, and the electrical signal communication between the first chip and the first optical module is interrupted. The port in the first chip connected to the first optical module enters an electrically idle state. After the first control module detects that the first chip enters an electrically idle state through a third control signal and detects that the first optical module is in place through a first control signal, it turns off the power supply of the internal driver of the first optical module through a second control signal and keeps the power supply to the receiving end of the first optical module. Turning off the power supply of the internal driver of the first optical module is beneficial to reducing the power consumption of the first optical communication device, and keeping the receiving end of the first optical module powered is to be able to detect whether the second optical module is inserted again.

[0079] As a feasible implementation mode, the first control module is also used for: when the first optical module is in place and the port corresponding to the first chip enters an electrically idle state, detecting whether there is an input optical signal at the receiving end of the first optical module through a second control signal; if so, restoring the power supply of the internal driver of the first optical module through the second control signal; detecting the internal driver state of the first optical module through the second control signal, and judging whether the internal driver of the first optical module is working normally according to the internal driver state of the first optical module; if so, controlling the port corresponding to the first chip to exit the electrically idle state and start link training through a third control signal, and when the link training is completed, the first chip establishes communication with the second chip.

[0080] In a specific implementation, when the first optical module is in place and the port corresponding to the first chip enters an electrical idle state, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through a second control signal. If not, it means that the second optical module is not inserted and the current state is maintained. If yes, it means that the second optical module is inserted again. The first control module restores the power supply of the internal driver of the first optical module through the second control signal, detects the state of the internal driver chip of the first optical module through the second control signal, and determines whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module. If the internal driver of the first optical module is working normally, the port corresponding to the first chip is controlled to exit the electrical idle state and start link training through a third control signal. Otherwise, the state of the internal driver chip of the first optical module is redetected until the internal driver of the first optical module is working normally.

[0081] During the link training of the first chip, the communication rate between the first chip and the second chip is gradually increased until the communication rate between the first chip and the second chip reaches the maximum rate. When the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, and the first optical module communicates with the second optical module through optical signals. If the first optical module is plugged in after being unplugged, that is, hot-plugged, when the link training is completed, the communication rate between the first chip and the second chip is restored to the rate before the second optical module is unplugged.

[0082] As a feasible implementation mode, the first control module is also used for: when neither the first optical module nor the second optical module is in place, after the first optical module is inserted, detecting that the first optical module is in place is performed through a first control signal; detecting the state of the internal driver chip of the first optical module is performed through a second control signal, and judging whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module; if so, detecting whether there is an input optical signal at the receiving end of the first optical module through a second control signal; if so, controlling the first chip to exit the electrical idle state and start link training through a third control signal, and when the link training is completed, the first chip establishes communication with the second chip.

[0083] In a specific implementation, when both the first optical module and the second optical module are not in place, the first optical module is inserted first. After the first control module detects that the first optical module is in place through the first control signal, the first control module detects the state of the internal driver chip of the first optical module through the second control signal, and determines whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module. If the internal driver of the first optical module is working normally, the second control signal is used to detect whether there is an input optical signal at the receiving end of the first optical module. If the internal driver of the first optical module is not working normally, the state of the internal driver chip of the first optical module is re-detected until the internal driver of the first optical module is working normally. If there is no input optical signal at the receiving end of the first optical module, it means that the second optical module is not inserted, and the current state is maintained. If there is an input optical signal at the receiving end of the first optical module, it means that the second optical module is inserted again, and the first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal.

[0084] It should be noted that after the second optical module is inserted again, the second control module in the second optical communication device detects that the second optical module is in place through the first control signal, and then the second control module detects the state of the internal driver chip of the second optical module through the second control signal, and determines whether the internal driver of the second optical module is working normally according to the state of the internal driver chip of the second optical module; if so, the second control module controls the port corresponding to the second chip to exit the electrical idle state through the third control signal, and the second optical module can send an optical signal to the first optical module, that is, there is an input optical signal at the receiving end of the first optical module.

[0085] During the link training process, the communication rate between the first chip and the second chip is gradually increased until the communication rate between the first chip and the second chip reaches the maximum rate. When the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, and the first optical module communicates with the second optical module through optical signals. If the first optical module and the second optical module are plugged in after being unplugged, that is, hot-plugged, when the link training is completed, the communication rate between the first chip and the second chip is restored to the rate before the first optical module and the second optical module are unplugged.

[0086] The optical interconnection system provided by the embodiment of the present invention confirms that the local optical module has entered the normal working state according to the in-place state of the optical module and the internal chip state, and judges that the opposite optical module has entered the normal working state according to the receiving end state of the optical module, thereby controlling the local chip to start link training, thereby avoiding the chip starting link training when the optical module link fails to enter the working state normally, resulting in failure to enter the highest rate state supported by the link, thereby avoiding the optical interconnection system from running in a reduced speed state.

[0087] The embodiment of the invention discloses an optical communication control method, which prevents an optical interconnection system from running in a reduced speed state.

[0088] See also Figure 2 , a flowchart of a first optical communication control method according to an exemplary embodiment is shown, as Figure 2 As shown, including:

[0089] S101: When the first optical module and the second optical module are both in place, when the first optical module is unplugged, the port corresponding to the first chip enters an electrical idle state, the first control module detects through a first control signal that the first optical module is not in place, and controls the first chip to stop receiving end detection through a third control signal;

[0090] This embodiment introduces the control process of hot-swapping the first optical module when the second optical module is in place from the perspective of the first optical communication device in the above-mentioned optical interconnection system, that is, the control process of hot-swapping the local optical module. The executor of this embodiment is the first control module in the first optical communication device.

[0091] In this step, when the second optical module is in place, when the first optical module is unplugged, the port in the first chip connected to the first optical module enters an electrically idle state, and after the first control module detects through the first control signal that the first optical module is not in place, the first control module controls the first chip to stop receiving end detection through the third control signal, which helps to reduce the power consumption of the first chip.

[0092] S102: After the first optical module is inserted, the first control module detects that the first optical module is in place through a first control signal;

[0093] In this step, when the first optical module is inserted again, the first control module detects that the first optical module is in place through the first control signal, and then enters S103.

[0094] S103: The first control module detects the state of the driver chip inside the first optical module through the second control signal, and determines whether the driver inside the first optical module works normally according to the state of the driver chip inside the first optical module; if so, enter S104; if not, re-enter S103;

[0095] In this step, the first control module detects the state of the internal driver chip of the first optical module through the second control signal, and determines whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module. If the internal driver of the first optical module is working normally, enter S104, otherwise re-enter S103 and re-detect the state of the internal driver chip of the first optical module until the internal driver of the first optical module is working normally.

[0096] S104: The first control module controls the port corresponding to the first chip to exit the electrical idle state and controls the first chip to start link training through the third control signal. When the link training is completed, the first chip establishes communication with the second chip.

[0097] In this step, if the internal driver of the first optical module has been working normally, the first control module controls the port of the first chip connected to the first optical module to exit the electrical idle state through the third control signal, and controls the first chip to start link training.

[0098] As a feasible implementation, the present embodiment further includes: during the link training process of the first chip, increasing the communication rate between the first chip and the second chip. In a specific implementation, during the link training process of the first chip, gradually increasing the communication rate between the first chip and the second chip until the communication rate between the first chip and the second chip reaches a maximum rate.

[0099] When the link training is completed, the first chip communicates with the first optical module via electrical signals, the first optical module communicates with the second optical module via optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the first optical module is unplugged.

[0100] As a feasible implementation, if the first optical module is plugged in after being unplugged, after the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, the first optical module communicates with the second optical module through optical signals, and the communication rate between the first chip in the first optical communication device and the second chip in the second optical communication device is restored to the rate before the first optical module was unplugged. In a specific implementation, if the first optical module is plugged in after being unplugged, that is, hot-plugged, after the link training is completed, the communication rate between the first chip and the second chip is restored to the rate before the first optical module was unplugged.

[0101] The communication control method provided by the embodiment of the present invention controls the first chip to stop receiving end detection through a third control signal when the first optical module is unplugged, which is beneficial to reducing the power consumption of the first chip. When the first optical module is inserted again, after detecting that the first optical module is in place and the internal driver of the first optical module is working normally, the first chip is controlled to start link training, thereby avoiding the first chip starting link training when the first optical module fails to enter the working state normally, resulting in failure to enter the highest rate state supported by the link, so that the communication rate between the first chip and the second chip is restored to the rate before the first optical module is unplugged, avoiding the optical interconnection system from running in a reduced speed state after the optical module is hot-plugged.

[0102] The embodiment of the present invention discloses an optical communication control method, see Figure 3 , a flowchart of a second optical communication control method according to an exemplary embodiment is shown, as Figure 3 As shown, including:

[0103] S201: When the first optical module and the second optical module are both in place, when the second optical module is unplugged, the port corresponding to the first chip enters an electrical idle state;

[0104] This embodiment introduces the control process of the first optical communication device when the second optical module is hot-plugged while the first optical module is in place, from the perspective of the first optical communication device in the above-mentioned optical interconnection system, that is, the control process of hot-plugging the opposite optical module. The executor of this embodiment is the first control module in the first optical communication device.

[0105] In this step, when the first optical module is in place and the second optical module is unplugged, the optical signal communication between the first optical module and the second optical module is interrupted, and the electrical signal communication between the first chip and the first optical module is interrupted. The port in the first chip connected to the first optical module enters an electrical idle state.

[0106] S202: After the first control module detects through the third control signal that the first chip enters the electrical idle state, it detects through the first control signal that the first optical module is in place, and turns off the power supply of the internal driver of the first optical module and keeps the power supply of the receiving end of the first optical module through the second control signal;

[0107] In this step, after the first control module detects that the first chip enters an electrical idle state through the third control signal and detects that the first optical module is in place through the first control signal, it turns off the power supply of the internal driver of the first optical module through the second control signal and keeps the power supply of the receiving end of the first optical module. Turning off the power supply of the internal driver of the first optical module is conducive to reducing the power consumption of the first optical communication device, and keeping the power supply of the receiving end of the first optical module is to be able to detect whether the second optical module is inserted again.

[0108] S203: The first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if there is, enter S204; if not, re-enter S203;

[0109] In this step, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal. If not, it means that the second optical module is not inserted and the S203 state is maintained. If so, it means that the second optical module is inserted again and enters S204.

[0110] S204: The first control module restores power supply to the internal driver of the first optical module through the second control signal;

[0111] In this step, after the second optical module is inserted again, the first control module restores the power supply of the internal driver of the first optical module through the second control signal.

[0112] S205: The first control module detects the internal driver state of the first optical module through the second control signal, and determines whether the internal driver of the first optical module works normally according to the internal driver state of the first optical module; if so, enter S206; if not, re-enter S205;

[0113] In this step, the first control module detects the state of the internal driver chip of the first optical module through the second control signal, and determines whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module. If the internal driver of the first optical module is working normally, enter S206, otherwise return to S305, re-detect the state of the internal driver chip of the first optical module until the internal driver of the first optical module is working normally.

[0114] S206: The first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal. When the link training is completed, the first chip establishes communication with the second chip.

[0115] In this step, if the internal driver of the first optical module is already working normally, the first control module controls the first chip to start link training through the third control signal. During the link training of the first chip, the communication rate between the first chip and the second chip is gradually increased until the communication rate between the first chip and the second chip reaches the maximum rate.

[0116] When the link training is completed, the first chip in the first optical communication device communicates with the first optical module via electrical signals, and the first optical module communicates with the second optical module via optical signals.

[0117] As a feasible implementation, if the second optical module is inserted after being unplugged, after the link training is completed, the first chip and the first optical module communicate via electrical signals, the first optical module and the second optical module communicate via optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the second optical module is unplugged. In a specific implementation, if the first optical module is inserted after being unplugged, that is, hot-plugged, after the link training is completed, the communication rate between the first chip and the second chip is restored to the rate before the second optical module is unplugged.

[0118] The communication control method provided by the embodiment of the present invention controls the first chip to start link training after detecting that the first optical module is in place, the internal driver of the first optical module is operating normally, and there is an input optical signal at the receiving end of the first optical module when the second optical module is unplugged and then inserted again, thereby avoiding the first chip from starting link training when the first optical module and the second optical module fail to enter the working state normally, resulting in failure to enter the highest rate state supported by the link, so that the communication rate between the first chip and the second chip is restored to the rate before the second optical module is unplugged, and avoiding the optical interconnection system from running in a reduced speed state after the optical module is hot-plugged.

[0119] The embodiment of the present invention discloses an optical communication control method, see Figure 4 , a flow chart of a third optical communication control method according to an exemplary embodiment is shown, as Figure 4 As shown, including:

[0120] S301: When neither the first optical module nor the second optical module is in place, after the first optical module is inserted, the first control module detects that the first optical module is in place through a first control signal;

[0121] This embodiment introduces the control process of hot-plugging the first optical module and the second optical module from the perspective of the first optical communication device in the optical interconnection system. The execution subject of this embodiment is the first control module in the first optical communication device.

[0122] In this step, after the first optical module and the second optical module are both unplugged, the first optical module and the second optical module are not in place, the port connected to the first optical module in the first chip enters an electrical idle state, and the port connected to the second optical module in the second chip enters an electrical idle state. At this time, the first optical module is inserted first, and after the first control module detects that the first optical module is in place through the first control signal, it enters S302.

[0123] S302: The first control module detects the state of the driver chip inside the first optical module through the second control signal, and determines whether the driver inside the first optical module works normally according to the state of the driver chip inside the first optical module; if yes, enter S303; if no, re-enter S302;

[0124] In this step, the first control module detects the state of the internal driver chip of the first optical module through the second control signal, and determines whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module. If the internal driver of the first optical module is working normally, enter S303, otherwise re-enter S302 and re-detect the state of the internal driver chip of the first optical module until the internal driver of the first optical module is working normally.

[0125] S303: The first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if there is, enter S304; if not, re-enter S303;

[0126] In this step, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal. If not, it means that the second optical module is not inserted and the S303 state is maintained. If so, it means that the second optical module is inserted again and enters S304.

[0127] It should be noted that after the second optical module is inserted again, the second control module in the second optical communication device detects that the second optical module is in place through the first control signal, and then the second control module detects the state of the internal driver chip of the second optical module through the second control signal, and determines whether the internal driver of the second optical module is working normally according to the state of the internal driver chip of the second optical module; if so, the second control module controls the port corresponding to the second chip to exit the electrical idle state through the third control signal, and the second optical module can send an optical signal to the first optical module, that is, there is an input optical signal at the receiving end of the first optical module.

[0128] S304: The first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal. When the link training is completed, the first chip establishes communication with the second chip.

[0129] In this step, if there is an input optical signal at the receiving end of the first optical module, the first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal. During the link training process, the communication rate between the first chip and the second chip is gradually increased until the communication rate between the first chip and the second chip reaches the maximum rate. When the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, and the first optical module communicates with the second optical module through optical signals.

[0130] As a feasible implementation, if the first optical module and the second optical module are both unplugged and then inserted, then after the link training is completed, the first chip and the first optical module communicate via electrical signals, and the first optical module and the second optical module communicate via optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the first optical module and the second optical module are unplugged. In a specific implementation, if the first optical module and the second optical module are unplugged and then inserted, that is, hot-plugged, after the link training is completed, the communication rate between the first chip and the second chip is restored to the rate before the first optical module and the second optical module are unplugged.

[0131] It can be seen that this embodiment detects the in-place state of the optical module, the internal driver chip state and the receiving end state, determines the optical link state according to the in-place state of the optical module and the receiving end state, and controls the corresponding chip whether to start link training according to the internal driver chip state of the optical module, thereby realizing the function of hot plugging of optical modules at both ends of the optical interconnection link. According to the in-place state of the optical module and the internal chip state, it is confirmed that the optical module at the local end has entered the normal working state, and according to the receiving end state of the optical module, it is determined that the optical module at the opposite end has entered the normal working state, thereby controlling the chip at the local end to start link training, thereby avoiding the chip starting link training when the optical module link fails to enter the working state normally, resulting in failure to enter the highest rate state supported by the link, thereby avoiding the system running in a reduced speed state.

[0132] An optical communication control device provided by an embodiment of the present invention is introduced below, which is applied to the first optical communication device in the above optical interconnection system. The optical communication control device described below and the optical communication control method described above can be referenced to each other.

[0133] See also Figure 5 , a structural diagram of an optical communication control device according to an exemplary embodiment is shown, such as Figure 5 As shown, including:

[0134] The first detection unit 100 is used to detect that the first optical module is in place through a first control signal when the first optical module is pulled out and then inserted, when the first optical module is not in place and the second optical module is in place; wherein the first optical module is an optical module in the first optical communication device, and the second optical module is an optical module in the second optical communication device connected to the first optical communication device;

[0135] The first judgment unit 200 is used to detect the state of the driver chip inside the first optical module through the second control signal, and judge whether the driver inside the first optical module works normally according to the state of the driver chip inside the first optical module; if so, start the working process of the first control unit;

[0136] The first control unit 300 is used to control the port corresponding to the first chip in the first optical communication device to exit the electrical idle state and control the first chip in the first optical communication device to start link training through a third control signal. When the link training is completed, the first chip in the first optical communication device establishes communication with the second chip in the second optical communication device.

[0137] The communication control device provided by the embodiment of the present invention, in the case where the first optical module is not in place and the second optical module is in place, after the first optical module is inserted, the first control module in the first optical communication device controls the first chip to start link training after detecting that the first optical module is in place and the internal driver of the first optical module is operating normally, thereby avoiding the first chip from starting link training when the first optical module fails to enter the working state normally, resulting in failure to enter the highest rate state supported by the link, so that the communication rate between the first chip and the second chip can reach the maximum rate through training, thereby avoiding the optical interconnection system from operating in a reduced speed state.

[0138] Based on the above embodiment, as a preferred implementation, it also includes:

[0139] The training unit is used to improve the communication rate between the first chip and the second chip during the link training process of the first chip.

[0140] Based on the above embodiment, as a preferred implementation, it also includes:

[0141] The second control unit is used for, when the first optical module and the second optical module are both in place, when the first optical module is pulled out, the port corresponding to the first chip enters an electrical idle state, the first control module detects through the first control signal that the first optical module is not in place, and controls the first chip to stop receiving end detection through the third control signal.

[0142] On the basis of the above embodiments, as a preferred implementation mode, if the first optical module is unplugged and then inserted, after the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, the first optical module communicates with the second optical module through optical signals, and the communication rate between the first chip in the first optical communication device and the second chip in the second optical communication device is restored to the rate before the first optical module is unplugged.

[0143] Based on the above embodiment, as a preferred implementation, it also includes:

[0144] The second detection unit is used for, when the first optical module is in place and the port corresponding to the first chip enters an electrical idle state, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if there is, the working process of the power supply unit is started;

[0145] A power supply recovery unit, used for the first control module to recover the power supply of the internal driver of the first optical module through the second control signal;

[0146] The second judgment unit is used to detect the internal driver state of the first optical module through the second control signal, and judge whether the internal driver of the first optical module works normally according to the internal driver state of the first optical module; if so, start the working process of the third control unit;

[0147] The third control unit is used to control the port corresponding to the first chip to exit the electrical idle state and start link training through a third control signal. When the link training is completed, the first chip resumes communication with the second chip.

[0148] Based on the above embodiment, as a preferred implementation, it also includes:

[0149] The power supply unit is shut down, which is used to detect that the first chip enters an electrical idle state through a third control signal, detect that the first optical module is in place through a first control signal, shut down the power supply of the internal driver of the first optical module through a second control signal, and maintain the power supply of the receiving end of the first optical module.

[0150] On the basis of the above embodiments, as a preferred implementation mode, if the second optical module is unplugged and then inserted, after the link training is completed, the first chip and the first optical module communicate through electrical signals, and the first optical module and the second optical module communicate through optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the second optical module is unplugged.

[0151] Based on the above embodiment, as a preferred implementation, it also includes:

[0152] A third detection unit is used to detect that the first optical module is in place through a first control signal when the first optical module is inserted when both the first optical module and the second optical module are not in place;

[0153] The third judgment unit is used to detect the state of the driver chip inside the first optical module through the second control signal, and judge whether the driver inside the first optical module works normally according to the state of the driver chip inside the first optical module; if so, start the working process of the fourth detection unit;

[0154] A fourth detection unit, configured to detect whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if there is an input optical signal, a working process of the fourth control unit is started;

[0155] The fourth control unit is used to control the first chip to exit the electrical idle state and start link training through the third control signal. When the link training is completed, the first chip resumes communication with the second chip.

[0156] On the basis of the above embodiments, as a preferred implementation mode, if the first optical module and the second optical module are both unplugged and then inserted, then after the link training is completed, the first chip and the first optical module communicate through electrical signals, and the first optical module and the second optical module communicate through optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the first optical module and the second optical module are unplugged.

[0157] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0158] Based on the hardware implementation of the above program modules and in order to implement the method of the embodiment of the present invention, the embodiment of the present invention further provides an electronic device, Figure 6 FIG. 1 is a structural diagram of an electronic device according to an exemplary embodiment. Figure 6 As shown, the electronic equipment includes:

[0159] Communication interface 1, capable of exchanging information with other devices such as network devices;

[0160] The processor 2 is connected to the communication interface 1 to implement information exchange with other devices and is used to execute the optical communication control method provided by one or more technical solutions when running a computer program. The computer program is stored in the memory 3.

[0161] Of course, in actual application, the various components in the electronic device are coupled together through the bus system 4. It can be understood that the bus system 4 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 4 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 6 Various buses are labeled as bus system 4 .

[0162] The memory 3 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program used to operate on the electronic device.

[0163] It can be understood that the memory 3 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 3 described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable types of memories.

[0164] The method disclosed in the above embodiment of the present invention can be applied to the processor 2, or implemented by the processor 2. The processor 2 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 2 or the instruction in the form of software. The above processor 2 can be a general-purpose processor, a DSP, or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 2 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general-purpose processor can be a microprocessor or any conventional processor, etc. In combination with the steps of the method disclosed in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in the memory 3. The processor 2 reads the program in the memory 3 and completes the steps of the above method in combination with its hardware.

[0165] When the processor 2 executes the program, the corresponding processes in the various methods of the embodiments of the present invention are implemented, which will not be described in detail here for the sake of brevity.

[0166] In an exemplary embodiment, the present invention further provides a non-volatile storage medium storing a computer program, which can be executed by the processor 2 to complete the aforementioned method steps.

[0167] In an exemplary embodiment, the present invention further provides a computer program product, including a computer program, which is executed by the processor 2 to complete the aforementioned method steps.

[0168] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to computer program instructions, and the aforementioned computer program can be stored in a non-volatile storage medium. When the computer program is executed, it executes the steps of the above method embodiments. Alternatively, if the above-mentioned integrated unit of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the embodiment of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a non-volatile storage medium and includes a number of instructions for an electronic device (which can be a personal computer, a server, a network device, etc.) to execute all or part of the methods of each embodiment of the present invention.

[0169] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. An optical interconnection system, characterized in that: The device comprises a first optical communication device and a second optical communication device, wherein the first optical communication device comprises a first chip, a first optical module, and a first control module connected to each other, and the second optical communication device comprises a second chip, a second optical module, and a second control module connected to each other, wherein the first optical communication device and the second optical communication device are connected via the first optical module and the second optical module, and the first optical module and the second optical module communicate via optical signals; The first control module is used for, when the first optical module is not in place and the second optical module is in place, detecting the presence of the first optical module through a first control signal after the first optical module is inserted, detecting the state of the internal driver chip of the first optical module through a second control signal, and judging whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module; if so, controlling the port corresponding to the first chip to exit the electrical idle state and controlling the first chip to start link training through a third control signal, and when the link training is completed, the first chip establishes communication with the second chip.

2. The optical interconnection system according to claim 1, characterized in that: When both the first optical module and the second optical module are in place, when the first optical module is unplugged, the port corresponding to the first chip enters an electrical idle state; The first control module is further used to: detect through a first control signal that the first optical module is not in place, and control the first chip to stop receiving end detection through a third control signal.

3. The optical interconnection system according to claim 1, characterized in that: The first control module is further used to: when the first optical module is in place and the port corresponding to the first chip enters an electrical idle state, detect whether there is an input optical signal at the receiving end of the first optical module through the second control signal; If it exists, the power supply of the internal driver of the first optical module is restored through the second control signal; the state of the internal driver of the first optical module is detected through the second control signal, and whether the internal driver of the first optical module is working normally is determined according to the state of the internal driver of the first optical module; if so, the port corresponding to the first chip is controlled to exit the electrical idle state and start link training through the third control signal. When the link training is completed, the first chip establishes communication with the second chip.

4. The optical interconnection system according to claim 3, characterized in that: When both the first optical module and the second optical module are in place, when the second optical module is unplugged, the port corresponding to the first chip enters an electrical idle state; The first control module is also used for: after detecting through the third control signal that the first chip enters an electrical idle state, detecting through the first control signal that the first optical module is in place, and shutting off the power supply of the internal driver of the first optical module and maintaining the power supply of the receiving end of the first optical module through the second control signal.

5. The optical interconnection system according to claim 1, characterized in that: The first control module is also used for: when neither the first optical module nor the second optical module is in place, after the first optical module is inserted, detecting that the first optical module is in place through the first control signal; detecting the state of the internal driver chip of the first optical module through the second control signal, and judging whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module; if so, detecting whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if so, controlling the first chip to exit the electrical idle state and start link training through the third control signal, and when the link training is completed, the first chip establishes communication with the second chip.

6. The optical interconnection system according to claim 1, characterized in that: The first control module is connected to the in-position pin of the first optical module through the first control signal, the first control module is connected to the integrated circuit pin of the first optical module through the second control signal, and the first control module is connected to the integrated circuit pin and / or the serial communication pin of the first chip through the third control signal, and the serial communication pin includes a serial data bus pin and / or a universal asynchronous receiver / transmitter serial communication pin.

7. The optical interconnection system according to claim 1, characterized in that: The first control module is integrated into the first chip, or the first control module is a chip independent of the first chip; If the first control module is a chip independent of the first chip, the first control module includes a complex programmable logic device and / or a field programmable gate array.

8. An optical communication control method, characterized in that: Applied to a first optical communication device, the method comprises: In the case where the first optical module is not in place and the second optical module is in place, when the first optical module is inserted, the first control module in the first optical communication device detects that the first optical module is in place through a first control signal; wherein the first optical module is an optical module in the first optical communication device, and the second optical module is an optical module in the second optical communication device connected to the first optical communication device; The first control module detects the state of the driver chip inside the first optical module through the second control signal, and determines whether the driver inside the first optical module works normally according to the state of the driver chip inside the first optical module; If so, the first control module controls the port corresponding to the first chip in the first optical communication device to exit the electrical idle state and controls the first chip in the first optical communication device to start link training through a third control signal. When the link training is completed, the first chip in the first optical communication device establishes communication with the second chip in the second optical communication device.

9. The optical communication control method according to claim 8, characterized in that: Also includes: During the link training process of the first chip, the communication rate between the first chip and the second chip is increased.

10. The optical communication control method according to claim 9, characterized in that: Also includes: In the case where both the first optical module and the second optical module are in place, when the first optical module is unplugged, the port corresponding to the first chip enters an electrical idle state, the first control module detects through the first control signal that the first optical module is not in place, and controls the first chip to stop receiving end detection through the third control signal.

11. The optical communication control method according to claim 10, characterized in that: If the first optical module is unplugged and then inserted, after link training is completed, the first chip in the first optical communication device establishes communication with the second chip in the second optical communication device, including: When link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, the first optical module communicates with the second optical module through optical signals, and the communication rate between the first chip in the first optical communication device and the second chip in the second optical communication device is restored to the rate before the first optical module is unplugged.

12. The optical communication control method according to claim 8, characterized in that: Also includes: When the first optical module is in place and the port corresponding to the first chip enters an electrical idle state, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal; If so, the first control module restores the power supply of the internal driver of the first optical module through the second control signal; The first control module detects the internal driver state of the first optical module through the second control signal, and determines whether the internal driver of the first optical module works normally according to the internal driver state of the first optical module; If so, the first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal. When the link training is completed, the first chip establishes communication with the second chip.

13. The optical communication control method according to claim 12, characterized in that: Also includes: When both the first optical module and the second optical module are in place, when the second optical module is unplugged, the port corresponding to the first chip enters an electrical idle state; After the first control module detects through the third control signal that the first chip enters an electrical idle state, it detects through the first control signal that the first optical module is in place, and through the second control signal turns off the power supply of the internal driver of the first optical module and keeps the power supply of the receiving end of the first optical module.

14. The optical communication control method according to claim 13, characterized in that: If the second optical module is plugged in after being unplugged, after link training is completed, the first chip establishes communication with the second chip, including: When link training is completed, the first chip communicates with the first optical module via electrical signals, the first optical module communicates with the second optical module via optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the second optical module is unplugged.

15. The optical communication control method according to claim 8, characterized in that: Also includes: In the case that both the first optical module and the second optical module are not in place, when the first optical module is inserted, the first control module detects that the first optical module is in place through the first control signal; The first control module detects the state of the driver chip inside the first optical module through the second control signal, and determines whether the driver inside the first optical module works normally according to the state of the driver chip inside the first optical module; If yes, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal; If so, the first control module controls the first chip to exit the electrical idle state and start link training through the third control signal. When the link training is completed, the first chip establishes communication with the second chip.

16. The optical communication control method according to claim 15, characterized in that: If both the first optical module and the second optical module are unplugged and then plugged in, after link training is completed, the first chip establishes communication with the second chip, including: When link training is completed, the first chip communicates with the first optical module through electrical signals, the first optical module communicates with the second optical module through optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the first optical module and the second optical module are unplugged.

17. An optical communication control device, characterized in that: Applied to a first optical communication device, the device comprises: A first detection unit is used to detect that the first optical module is in place through a first control signal when the first optical module is pulled out and then inserted when the first optical module is not in place and the second optical module is in place; wherein the first optical module is an optical module in the first optical communication device, and the second optical module is an optical module in the second optical communication device connected to the first optical communication device; a first judgment unit, configured to detect the state of the driver chip inside the first optical module through a second control signal, and judge whether the driver inside the first optical module works normally according to the state of the driver chip inside the first optical module; if so, start the working process of the first control unit; The first control unit is used to control the port corresponding to the first chip in the first optical communication device to exit the electrical idle state and control the first chip in the first optical communication device to start link training through a third control signal. When the link training is completed, the first chip in the first optical communication device establishes communication with the second chip in the second optical communication device.

18. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps performed by the optical communication control method as claimed in any one of claims 8 to 16 when executing the computer program.

19. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, and when the computer program is executed, the steps performed by the optical communication control method according to any one of claims 8 to 16 are implemented.

20. A computer program product, characterized in that The invention comprises a computer program, which, when executed, implements the steps performed by the optical communication control method according to any one of claims 8 to 16.

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