Phase change memory and manufacturing method thereof

Abstract

The embodiment of the invention provides a phase change memory and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor structure which comprises a first storage unit; the isolation layers are arranged between the adjacent first storage units; the first conductive wire is arranged on one side of the first storage unit, the surface of the first conductive wire protrudes out of the surface of the isolation layer, and the adjacent first conductive wire and the isolation layer jointly form a first groove; forming a first dielectric layer which covers the side wall and the bottom of the first groove and covers the first conductive wire so as to form a second groove in the first groove; forming a second dielectric layer covering the side wall and the bottom of the second groove and covering the first dielectric layer; performing planarization processing to expose the first conductive wires; wherein in the planarization processing, the removal rate of the second dielectric layer is smaller than the removal rate of the first dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, including but not limited to a phase change memory and a manufacturing method thereof. Background Art

[0002] By improving the semiconductor manufacturing process, the planar memory cell can be reduced to a smaller size. However, as the critical dimension of the planar memory cell approaches the lower limit, the storage density of the planar memory architecture approaches the upper limit. The three-dimensional memory structure can solve the density limitation in the planar memory architecture.

[0003] Phase Change Memory (PCM) has become one of the most promising storage technologies. Phase change memory uses the conductivity difference exhibited by the phase change layer when it transforms between the crystalline state and the amorphous state to store data. Phase change memory may include a bottom memory cell array (Bottom Stack) and a top memory cell array (Top Stack) stacked to form a three-dimensional storage architecture. The bottom memory cell and the top memory cell can be connected by a shared conductive line (e.g., a shared word line). Therefore, the shared conductive line process becomes a key manufacturing process in phase change memory.

[0004] Currently, the manufacturing process of phase change memory still needs further improvement. Summary of the invention

[0005] In view of this, embodiments of the present disclosure provide a phase change memory and a method for manufacturing the same.

[0006] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0007] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a phase change memory, the method comprising: providing a semiconductor structure, comprising: a first memory cell; an isolation layer disposed between adjacent first memory cells; a first conductive wire disposed on one side of the first memory cell, the surface of the first conductive wire protruding from the surface of the isolation layer, the adjacent first conductive wire and the isolation layer jointly forming a first groove; forming a first dielectric layer covering the sidewalls and bottom of the first groove and covering the first conductive wire to form a second groove in the first groove; forming a second dielectric layer covering the sidewalls and bottom of the second groove and covering the first dielectric layer; performing a planarization process to expose the first conductive wire; wherein, in the planarization process, a removal rate of the second dielectric layer is less than a removal rate of the first dielectric layer.

[0008] In some embodiments, the density of the second dielectric layer is greater than the density of the first dielectric layer.

[0009] In some embodiments, the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

[0010] In some embodiments, the thickness of the second dielectric layer ranges from 150 to 200 angstroms, and the thickness of the first dielectric layer ranges from 50 to 100 angstroms.

[0011] In some embodiments, the process of forming the first dielectric layer includes a first atomic layer deposition process, and the process of forming the second dielectric layer includes a second atomic layer deposition process; wherein the RF power in the second atomic layer deposition process is greater than the RF power in the first atomic layer deposition process.

[0012] In some embodiments, the RF power in the first atomic layer deposition process ranges from 300 to 500 W; the RF power in the second atomic layer deposition process ranges from 800 to 1000 W.

[0013] In some embodiments, the ratio between the removal rates of the second dielectric layer and the first conductive line is in the range of 22-24.

[0014] In a second aspect, an embodiment of the present disclosure provides a phase change memory, which is manufactured by the manufacturing method in the above technical solution, and comprises: first storage units arranged at intervals along a first direction; first conductive lines arranged on one side of the first storage units and extending along a second direction, wherein the two directions intersect with the first direction; a first dielectric layer arranged between adjacent first conductive lines, wherein the first dielectric layer covers two side walls of the first conductive line arranged opposite to each other along the first direction; and a second dielectric layer arranged between the first dielectric layers on the side walls of adjacent first conductive lines.

[0015] In some embodiments, the density of the second dielectric layer is greater than the density of the first dielectric layer.

[0016] The disclosed embodiment provides a phase change memory and a manufacturing method thereof. In the disclosed embodiment, a first dielectric layer is formed to cover the side wall and top surface of the first conductive line to protect the side wall and top surface of the first conductive line in the subsequent process of forming the second dielectric layer; a second dielectric layer is formed to fill the gap between adjacent first conductive lines; in the process of flattening the second dielectric layer and the first dielectric layer, the removal rate of the second dielectric layer is greater than the removal rate of the first dielectric layer, which is beneficial to reducing the height difference between the top surface of the first conductive line and the surface of the second dielectric layer, so that the top surface of the first conductive line and the surface of the second dielectric layer are basically flush, thereby facilitating the improvement of the yield of the phase change memory and improving the electrical parameters of the phase change memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A A cross-sectional view 1 of a phase change memory during a manufacturing process provided in some embodiments;

[0018] Figure 1B Cross-sectional view of a phase change memory during manufacturing provided in some embodiments Figure 2 ;

[0019] Figure 2 A schematic diagram of a process for manufacturing a phase change memory provided by an embodiment of the present disclosure;

[0020] Figure 3A A first cross-sectional view of a phase change memory device during the manufacturing process provided by an embodiment of the present disclosure;

[0021] Figure 3B A cross-sectional view of a phase change memory during the manufacturing process provided by an embodiment of the present disclosure Figure 2 ;

[0022] Figure 3C A third cross-sectional view of the phase change memory during the manufacturing process provided by the embodiment of the present disclosure;

[0023] Figure 3D A cross-sectional view of a phase change memory during the manufacturing process provided by an embodiment of the present disclosure Figure 4 ;

[0024] Figure 4 It is a schematic diagram of the results of various parameters in Comparative Examples 1 and 2 and Examples 1 to 4;

[0025] Figure 5 A block diagram of a memory system provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0027] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0028] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0029] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0030] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0031] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0032] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0033] Before introducing the embodiments of the present disclosure, various directions that may be involved in the embodiments of the present disclosure are first defined. The directions in which the first storage units (or, second storage units) in the phase change memory are arranged at intervals are defined as the intersecting first direction (i.e., D1 direction) and the second direction (i.e., D2 direction), and the stacking direction of the first storage unit and the second storage unit in the phase change memory is defined as the third direction (i.e., D3 direction). Here, any two of the first direction, the second direction, and the third direction intersect. In some embodiments, any two of the first direction, the second direction, and the third direction are perpendicular to each other. The following will be described by taking the example that any two of the first direction, the second direction, and the third direction are perpendicular to each other.

[0034] Figure 1A and Figure 1B A cross-sectional view of a phase change memory during the manufacturing process provided in some embodiments. Figure 1A As shown, the phase change memory may include: bottom storage units 104 (such as Figure 1A The phase change memory may further include: a first oxide layer 112 covering the sidewalls and top surface of the first conductive line 108 and the surface of the isolation layer 106; and a second oxide layer 118 covering the first oxide layer 112.

[0035] like Figure 1B As shown, the second oxide layer 118 and the first oxide layer 112 are planarized to expose the top surface of the first conductive line 108. During the planarization process, the second oxide layer 118 and the first oxide layer 112 need to be removed, and the top surface of the first conductive line 108 remains. During the planarization process, the removal rate (RR) of the first oxide layer 112 is much greater than the removal rate of the first conductive line 108. Therefore, after the planarization process, the top surface of the first oxide layer 112 between adjacent first conductive lines 108 is lower than the top surface of the first conductive line 108, and the top surface of the first oxide layer 112 between adjacent first conductive lines 108 is concave (Dishing).

[0036] That is, the top surface of the first oxide layer between adjacent first conductive lines cannot be flush with the top surface of the first conductive line, making it difficult to continue to form a top memory cell on the bottom memory cell, and may cause leakage (LKG) in the phase change memory. Therefore, the manufacturing process of the phase change memory still needs to be further improved.

[0037] In view of this, embodiments of the present disclosure provide a phase change memory and a method for manufacturing the same.

[0038] refer to Figure 2 , Figure 2 The flowchart of the method for manufacturing the phase change memory provided by the embodiment of the present disclosure is as follows. Figure 2 As shown, the present disclosure provides a method for manufacturing a phase change memory, the method comprising:

[0039] Step S210: providing a semiconductor structure, including: a first memory cell; an isolation layer disposed between adjacent first memory cells; a first conductive line disposed on one side of the first memory cell, wherein a surface of the first conductive line protrudes from a surface of the isolation layer, and adjacent first conductive lines and the isolation layer jointly form a first groove;

[0040] Step S220: forming a first dielectric layer covering the sidewall and bottom of the first groove and covering the first conductive line, so as to form a second groove in the first groove;

[0041] Step S230: forming a second dielectric layer covering the sidewall and bottom of the second groove and covering the first dielectric layer;

[0042] Step S240: performing a planarization process to expose the first conductive line; wherein, during the planarization process, a removal rate of the second dielectric layer is lower than a removal rate of the first dielectric layer.

[0043] refer to FIG. 3A to FIG. 3D , FIG. 3A to FIG. 3D A cross-sectional view of a phase change memory device during the manufacturing process provided by an embodiment of the present disclosure. Figure 2 and FIG. 3A to FIG. 3D , the manufacturing process of the phase change memory provided by the embodiment of the present disclosure is described in detail.

[0044] In the embodiment of the present disclosure, in step S210, a semiconductor structure 302 is provided, including: a first storage unit 304; a first isolation layer 306 arranged between adjacent first storage units 304; a first conductive line 308 arranged on one side of the first storage unit 304, the surface of the first conductive line 308 protrudes from the surface of the first isolation layer 306, and the adjacent first conductive lines 308 and the first isolation layer 306 jointly form a first groove 310.

[0045] like Figure 3AAs shown, in some embodiments, step S210 includes: forming a second conductive line 320; forming a first storage unit 304 on one side of the second conductive line 320, and the first storage units 304 are arranged at intervals along the D1 direction and the D2 direction; forming a first conductive line 308 on a side of the first storage unit 304 away from the second conductive line 320; wherein the first conductive line 308 extends along the D2 direction, and the second conductive line 320 extends along the D1 direction.

[0046] Exemplarily, forming the second conductive line 320 may include the following steps: providing a substrate; forming a second conductive material layer on one side of the substrate; forming a first storage stack layer on a side of the second conductive material layer away from the substrate; etching the first storage stack layer and the second conductive material layer in sequence along the D3 direction to form a plurality of first grooves extending along the D1 direction; wherein the etched second conductive material layer forms the second conductive line 320 extending along the D1 direction, and the etched first storage stack layer forms the first storage stack strip extending along the D1 direction.

[0047] Here, the substrate may include a semiconductor substrate; specifically, at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material or other semiconductor materials known in the art, and may also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, a silicon-germanium substrate, etc.

[0048] Here, the first memory stack layer may include a first electrode layer, a phase change layer, a second electrode layer, a gate layer, and a third electrode layer which are sequentially stacked along the D3 direction.

[0049] Here, the first electrode layer, the second electrode layer and the third electrode layer can be used to transmit electrical signals and can include conductive materials, such as metal materials, metal nitrides or any combination thereof. The metal material can be, for example, platinum (Pt), tungsten (W), aluminum (Al), copper (Cu) or titanium (Ti). In some embodiments, the first electrode layer, the second electrode layer and the third electrode layer can include carbon electrodes.

[0050] Here, the phase change layer may include a phase change material. The phase change material may be an alloy of a chalcogenide compound, such as a germanium-antimony telluride compound (Ge-Sb-Te compound, GST), a germanium-antimony compound, an indium-germanium telluride compound, an aluminum-selenide telluride compound, an indium-selenide telluride compound, an aluminum-indium-selenide telluride compound, etc. In this embodiment, taking the material of the phase change layer as GST as an example, the GST material can realize a reversible transition between an amorphous state and a crystalline state. In the amorphous state, the GST material has a short-range atomic energy level and a low free electron density, so that it has a high resistivity; in the crystalline state, the GST material has a long-range atomic energy level and a high free electron density, so that it has a low resistivity. The phase change memory utilizes the resistance difference between the phase change material in different phases to realize information storage. By applying different voltage or current pulse signals to the phase change layer, the phase change material undergoes a physical phase change, that is, a reversible phase change occurs between the crystalline state (low resistance state) and the amorphous state (high resistance state) to convert each other, thereby realizing the writing and erasing operations of information to store data.

[0051] Here, the gating layer may include a threshold switch material, such as an Ovonic Threshold Switching (OTS) material. The OTS material may be a chalcogenide material, such as GeSeAs, GeTeAs, GeSeTeSe, GeSe, SeAs, GeTe, SiTe, etc. The bidirectional threshold switch uses an electrical signal to control the switch of the gating device. When the applied electrical signal is higher than the threshold voltage, the OTS material changes from a high resistance state to a low resistance state, and the OTS is in an on state; when the electrical signal is removed, the OTS material changes from a low resistance state to a high resistance state, and the OTS is in an off state. The gating layer is used to control the current flowing through the phase change layer, and remains in an on state when the phase change layer is erased and written, and remains in an off state after the erase and write operation is completed, so as to avoid read-write crosstalk between storage cells.

[0052] Here, the process of forming the first storage stack layer may include but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or any combination thereof.

[0053] Here, the material of the second conductive line 320 may include a conductive material, such as a metal material. For example, the second conductive line may include metal tungsten.

[0054] Here, the process of forming the second conductive material layer may include, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0055] Exemplarily, forming the first storage unit 304 and the first conductive line 308 on one side of the second conductive line 320 may include the following steps: filling a second isolation material in the first groove to form a second isolation layer so that the surface of the first storage stack bar and the surface of the second isolation layer are substantially flush; forming a first conductive material layer on the side of the first storage stack bar and the second isolation layer away from the second conductive line; etching the first conductive material layer and the first storage stack bar in sequence along the D3 direction to form a plurality of second grooves extending along the D2 direction and exposing the second conductive line 320; wherein the first conductive material layer after etching forms the first conductive line 308 extending along the D2 direction, and the first storage stack bar after etching forms a plurality of first storage units 304 spaced apart along the D1 direction and the D2 direction.

[0056] Here, the orthographic projection shape of the first storage unit 304 on the substrate plane may be a circle, a quadrilateral, or other shapes. Alternatively, the cross-sectional shape of the first storage unit 304 perpendicular to the D3 direction may be a circle, a quadrilateral, or other shapes. The present disclosure does not specifically limit the orthographic projection shape (or cross-sectional shape) of the first storage unit 304.

[0057] Here, the material of the first conductive line 308 may include a conductive material, such as a metal material. For example, the first conductive line 308 may include metal tungsten.

[0058] Here, the process of forming the first conductive material layer may include, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0059] Here, the material of the second isolation layer may include but is not limited to spin-on dielectric (Spin-On Dielectric, SOD).

[0060] Here, the first etching forms a first groove extending along the D1 direction, and the etching depth is the sum of the thicknesses of the second conductive material layer and the first storage stack layer; the second etching forms a second groove extending along the D2 direction, and the etching depth is the sum of the thicknesses of the first storage stack layer and the first conductive material layer.

[0061] Exemplarily, forming the semiconductor structure may further include the following steps: filling the second trench with a first isolation material to form a first isolation material layer, so that the surface of the first conductive line and the surface of the first isolation layer are substantially flush; etching back to remove a portion of the first isolation material layer to form a first isolation layer exposing the sidewall and top surface of the first conductive line. The first conductive line 308 extends along the D2 direction, and the first conductive line 308 includes two sidewalls arranged oppositely along the D1 direction and a bottom surface and a top surface arranged oppositely along the D3 direction. The bottom surface of the first conductive line 308 is close to the first storage unit 304, and the top surface of the first conductive line 308 is far away from the first storage unit 304.

[0062] Here, a second isolation layer is provided between adjacent first storage units 304 along the D2 direction, and a first isolation layer 306 is provided between adjacent first storage units 304 along the D1 direction. Exemplarily, the first storage units 304 spaced apart along the D1 direction and the D2 direction may be isolated by SOD.

[0063] It should be noted that before filling the second isolation material in the first trench, a barrier layer covering the sidewalls of the first storage stack strip may be formed; and / or before filling the first isolation material in the second trench, a barrier layer covering the sidewalls of the first storage unit may be formed.

[0064] Still Figure 3A As shown, the first isolation material layer is partially removed by etching back, and the barrier layer covering the sidewalls of the first conductive line 308 is partially removed to expose the top surface and part of the sidewalls of the first conductive line 308, and the remaining first isolation material layer forms the first isolation layer. At this time, the entire sidewalls of the first conductive line 308 are not exposed, and part of the sidewalls of the first conductive line 308 are still covered by the barrier layer 324. In other words, the surface of the first isolation layer 306 is higher than the bottom surface of the first conductive line 308 and the surface of the first isolation layer 306 is lower than the top surface of the first conductive line 308. The top surface of the first conductive line 308 protrudes from the surface of the first isolation layer 306, and after etching back, a first groove 310 can be formed between adjacent first conductive lines 308. The sidewalls of the first groove 310 are the two sidewalls of the first conductive line 308 that are arranged opposite to each other along the D1 direction, and the bottom of the first groove 310 exposes the surface of the first isolation layer 306.

[0065] Here, the material of the first isolation layer 306 may include, but is not limited to, SOD.

[0066] In addition, the substrate may include a chip area and a cutting path area surrounding the chip area. The chip area may be provided with a chip structure, such as a first conductive line, a second conductive line and a first storage unit; the cutting path area may be provided with a test structure for testing the chip structure. FIG. 3A to FIG. 3D The dashed line indicates the cutting path.

[0067] In the embodiment of the present disclosure, in step S220 , a first dielectric layer 312 is formed to cover the sidewall and bottom of the first groove 310 and the first conductive line 308 , so as to form a second groove 314 in the first groove 310 .

[0068] like Figure 3BAs shown, the first dielectric layer 312 covers the sidewalls of the first groove 310, that is, the first dielectric layer 312 covers the sidewalls of the first conductive line 308; the first dielectric layer 312 also covers the bottom of the first groove 310, that is, the first dielectric layer 312 also covers the surface of the first isolation layer 306; the first dielectric layer 312 also covers the first conductive line 308, that is, the first dielectric layer 312 also covers the top surface of the first conductive line 308. In other words, the first dielectric layer 312 covers the sidewalls and top surface of the first conductive line 308 and covers the surface of the first isolation layer 306. At this time, the thickness of the first dielectric layer 312 is relatively small, and the first dielectric layer 312 does not fill the first groove 310, but forms a second groove 314 in the first groove 310. Exemplarily, the thickness of the first dielectric layer 312 can be, for example, 50 angstroms.

[0069] Here, the first dielectric layer 312 may include but is not limited to silicon oxide material.

[0070] Here, the process of forming the first dielectric layer 312 may include ALD.

[0071] Here, the width of the first groove 310 along the D1 direction is recorded as W1, and the depth of the first groove 310 along the D3 direction is recorded as H1. The thickness of the first dielectric layer 312 is recorded as d, then the width of the second groove 314 along the D1 direction is (W1-2*d), and the depth of the second groove 314 along the D3 direction is H1.

[0072] In the embodiment of the present disclosure, in step S230 , a second dielectric layer 316 is formed to cover the sidewall and the bottom of the second groove 314 and the first dielectric layer 312 .

[0073] like Figure 3C As shown, the second dielectric layer 316 covers the second groove 314 and fills the second groove 314; a third dielectric layer 318 is formed to cover the second dielectric layer 316. At this time, compared with the first dielectric layer 312, the thickness of the second dielectric layer 316 is larger. Exemplarily, the thickness of the second dielectric layer 316 can be, for example, 200 angstroms; the thickness of the third dielectric layer 318 can be, for example, 5000 angstroms.

[0074] Here, the second dielectric layer 316 and the third dielectric layer 318 may both include, but are not limited to, silicon oxide materials.

[0075] Here, the process of forming the second dielectric layer 316 may include ALD.

[0076] Here, the process of forming the third dielectric layer 318 may include CVD. For example, the third dielectric layer 318 is formed using tetraethoxysilane (TEOS) as a raw material.

[0077] In the embodiment of the present disclosure, in step S240 , a planarization process is performed to expose the first conductive line 308 ; wherein, in the planarization process, a removal rate of the second dielectric layer 316 is lower than a removal rate of the first dielectric layer 312 .

[0078] like Figure 3D As shown, the third dielectric layer 318, the second dielectric layer 316 and the first dielectric layer 312 are planarized until the top surface of the first conductive line 308 is exposed, so that the top surface of the first conductive line 308 is substantially flush with the surface of the second dielectric layer 316. In the planarization process, the removal rate of the second dielectric layer 316 is lower than the removal rate of the first dielectric layer 312, which is conducive to making the top surface of the first conductive line 308 substantially flush with the surface of the second dielectric layer 316, thereby facilitating the improvement of the yield of the phase change memory and the improvement of the electrical parameters of the phase change memory.

[0079] Here, substantially flush means that the height difference between the top surface of the first conductive line 308 and the surface of the second dielectric layer 316 along the D3 direction is 0, or the height difference between the top surface of the first conductive line 308 and the surface of the second dielectric layer 316 along the D3 direction meets the process error range. Compared with the concavity on the surface of the first oxide layer between adjacent first conductive lines, in the embodiment of the present disclosure, the height difference between the surface of the second dielectric layer between adjacent first conductive layers and the top surface of the first conductive line is smaller (or the concavity formed on the surface of the second dielectric layer is smaller) or the height difference is 0.

[0080] Here, the planarization process may include a chemical mechanical polishing (CMP) process.

[0081] Illustratively, the polishing agent of the CMP process may be, for example, ceria.

[0082] In some embodiments, the pressure of the planarization process can be reduced to reduce the removal rate of the first conductive line 308 and the second dielectric layer 316 during the planarization process. That is, when other parameters remain unchanged, reducing the pressure during the planarization process can reduce the removal rate of the first conductive line 308, and reducing the pressure during the planarization process can also reduce the removal rate of the second dielectric layer 316.

[0083] In some embodiments, the ratio between the removal rates of the second dielectric layer 316 and the first conductive line 308 (ie, the selectivity ratio between the second dielectric layer 316 and the first conductive line 308 ) may range from 22 to 24.

[0084] It should be noted that reducing the pressure during the planarization process has different effects on the reduction of the removal rate of the first conductive line 308 and the second dielectric layer 316. In some embodiments, reducing the pressure during the planarization process also reduces the selectivity between the second dielectric layer 316 and the first conductive line 308.

[0085] In some embodiments, the process of forming the first dielectric layer 312 includes a first atomic layer deposition process, and the process of forming the second dielectric layer 316 includes a second atomic layer deposition process; wherein the radio frequency power in the second atomic layer deposition process is greater than the radio frequency power in the first atomic layer deposition process. In some embodiments, the density of the second dielectric layer 316 is greater than the density of the first dielectric layer 312.

[0086] Here, the reaction principle of forming the first dielectric layer 312 or the second dielectric layer 316 is to alternately introduce precursor pulses into the reaction chamber and cause a chemical adsorption reaction on the substrate surface to form an atomic-level thin film. Exemplarily, the following steps may be included: (1) After the precursor is adsorbed and the surface is pretreated, the primary precursor is introduced into the atmosphere and an adsorption layer is formed on the surface by chemical reaction; (2) an inert gas is introduced to flush the precursor away; (3) after the adsorption layer is formed, another precursor is introduced to form plasma under the action of alternating current, and react with it to generate a reaction layer; (4) an inert gas is introduced to flush away the reaction byproducts; (5) the above four steps are repeatedly performed until the desired thin film is formed. The reaction process is mainly carried out in step (3). By increasing the power of the alternating current and increasing the density of the plasma, the dissociation of the O2 precursor is more complete, thereby increasing the density of the film layer.

[0087] Here, the process of forming the first dielectric layer 312 may include a first atomic layer deposition process, in which case the radio frequency power in the first atomic layer deposition process is relatively small, and the density of forming the first dielectric layer 312 is relatively small. The process of forming the second dielectric layer 316 may include a second atomic layer deposition process, in which case the radio frequency power in the second atomic layer deposition process is relatively large, and the density of forming the second dielectric layer 316 is relatively large. Therefore, in the planarization process, the removal rate of the second dielectric layer 316 is lower than the removal rate of the first dielectric layer 312.

[0088] On the one hand, if the first dielectric layer is formed only between adjacent first conductive lines, then during the planarization process, the removal rate of the first conductive lines is greater than the removal rate of the first dielectric layer. After the planarization process, a large depression is formed on the surface of the first dielectric layer between adjacent first conductive lines, which is not conducive to the subsequent formation of the second storage unit. On the other hand, if the second dielectric layer is formed only between adjacent first conductive lines, the high RF power conditions in the formation of the second dielectric layer may cause damage to the first conductive line. In the embodiment of the present disclosure, the first dielectric layer covering the sidewalls and top surfaces of the first conductive lines is first formed, and the RF power in the first atomic layer deposition process is relatively small, which can protect the sidewalls and top surfaces of the first conductive lines; then the second dielectric layer filling the gaps between the adjacent first conductive lines is formed, and the RF power in the second atomic layer deposition process is relatively large, and the density of the formed second dielectric layer is greater. Since the density of the second dielectric layer is greater than that of the first dielectric layer, during the planarization process, the removal rate of the second dielectric layer is less than the removal rate of the first dielectric layer.

[0089] For example, the RF power in the first atomic layer deposition process may range from 300 to 500 W; and the RF power in the second atomic layer deposition process may range from 800 to 1000 W.

[0090] In some embodiments, the deposition time in the first atomic layer deposition process is less than the deposition time in the second atomic layer deposition process. In some embodiments, the thickness of the second dielectric layer 316 is greater than the thickness of the first dielectric layer 312. In some embodiments, the thickness of the second dielectric layer 316 ranges from 150 to 200 angstroms, and the thickness of the first dielectric layer 312 ranges from 50 to 100 angstroms.

[0091] Here, the deposition time in the first atomic layer deposition process is short, and the first dielectric layer 312 covering the sidewall and top surface of the first conductive line 308 and the surface of the first isolation layer 306 can be formed. At this time, the thickness of the first dielectric layer 312 is short. The deposition time in the second atomic layer deposition process is long, and the second dielectric layer 316 covering the first dielectric layer 312 can be formed. At this time, the thickness of the second dielectric layer 316 is long.

[0092] refer to Figure 4 , Figure 4 Schematic diagram of the results of various parameters in Comparative Examples 1 and 2 and Examples 1 to 4. Figure 4As shown, in Comparative Example 1, the first dielectric layer is formed only under the condition of low RF power, and the thickness of the first dielectric layer is 250 angstroms. At this time, in the planarization process, the removal rate of the first dielectric layer is greater than the removal rate of the first conductive line. After the planarization process, the maximum height of the depression formed on the surface of the first dielectric layer is 80 angstroms. In this way, after the planarization process, the first dielectric layer and the first conductive line cannot be flush, and it is difficult to continue to form the second memory cell on the first memory cell.

[0093] In Comparative Example 2, the second dielectric layer is formed only under the condition of high RF power, and the thickness of the second dielectric layer is 250 angstroms. At this time, during the planarization process, the removal rate of the second dielectric layer is lower than the removal rate of the first dielectric layer. After the planarization process, the maximum height of the depression formed on the surface of the second dielectric layer is 40 angstroms. In this way, the second dielectric layer and the first conductive line are substantially flush, and the second memory cell can be further formed on the first memory cell; however, the high RF power has caused damage to the first memory cell.

[0094] In Examples 1 to 4, the first dielectric layer is first formed under low RF power conditions, and then the second dielectric layer is formed under high RF power conditions, and the sum of the thicknesses of the first dielectric layer and the second dielectric layer is 250 angstroms. In this way, the first dielectric layer is first formed under low RF power conditions to avoid damage to the first storage unit, and then the second dielectric layer is formed under high RF power conditions to reduce the difference between the removal rates in the planarization process, so as to reduce the maximum height of the depression formed on the surface of the second dielectric layer, which is conducive to making the top surface of the first conductive line and the surface of the second dielectric layer substantially flush, thereby facilitating the improvement of the yield of the phase change memory and the improvement of the electrical parameters of the phase change memory.

[0095] In some embodiments, after step S240, the method further includes: forming a third conductive line on a side of the first conductive line 308 away from the first storage unit 304, the third conductive line extending along the D2 direction, and the first conductive line 308 and the third conductive line are connected one-to-one; forming a second storage unit on a side of the third conductive line away from the first conductive line 308, the second storage units are arranged at intervals along the D1 direction and the D2 direction; forming a fourth conductive line on a side of the second storage unit away from the third conductive line, the fourth conductive line extending along the D1 direction.

[0096] Exemplarily, forming the third conductive line may include the following steps: forming a third conductive material layer on a side of the first conductive line away from the first storage unit, the third conductive material layer covering the top surface of the first conductive line 308 and the surface of the second dielectric layer 316; forming a second storage stack layer on a side of the third conductive material layer away from the first conductive line; etching the second storage stack layer and the third conductive material layer in sequence along the D3 direction to form a plurality of third grooves extending along the D2 direction and exposing the second dielectric layer 316; wherein the etched third conductive material layer forms a third conductive line extending along the D2 direction, and the etched second storage stack layer forms a second storage stack strip extending along the D2 direction.

[0097] Here, the third conductive lines may be connected to the first conductive lines in a one-to-one correspondence.

[0098] Exemplarily, forming a second storage unit and a fourth conductive line on a side of the third conductive line away from the first conductive line may also include the following steps: filling a third isolation material in a third trench to form a third isolation layer, so that the surface of the second storage stack bar and the surface of the third isolation layer are substantially flush; forming a fourth conductive material layer on a side of the second storage stack bar and the third isolation layer away from the third conductive line; etching the fourth conductive material layer and the second storage stack bar in sequence along the D3 direction to form a plurality of fourth grooves extending along the D1 direction and exposing the third conductive line; wherein the etched fourth conductive material layer forms a fourth conductive line extending along the D1 direction, and the etched second storage stack bar forms a plurality of second storage units spaced apart in both the D1 direction and the D2 direction.

[0099] Here, the third etching forms a third groove extending along the D2 direction, and the etching depth is the sum of the thicknesses of the third conductive material layer and the second storage stack layer; the fourth etching forms a fourth groove extending along the D1 direction, and the etching depth is the sum of the thicknesses of the second storage stack layer and the fourth conductive material layer.

[0100] Here, the second storage stack layer and the second storage unit can refer to the above description of the first storage stack layer and the first storage unit, which will not be repeated here.

[0101] Here, the materials of the third conductive wire and the fourth conductive wire, and the process of forming the third conductive wire and the fourth conductive wire can refer to the above description of the first conductive wire and the second conductive wire, which will not be repeated here.

[0102] Exemplarily, forming the phase change memory may further include the following steps: filling a fourth isolation material in the fourth trench to form a fourth isolation layer, so that the surface of the fourth conductive line is substantially flush with the surface of the fourth isolation layer.

[0103] Here, the materials of the third isolation layer and the fourth isolation layer, and the processes for forming the third isolation layer and the fourth isolation layer can refer to the above descriptions of the first isolation layer and the second isolation layer, and will not be repeated here.

[0104] Here, a third isolation layer is provided between adjacent second storage cells along the D1 direction, and a fourth isolation layer is provided between adjacent second storage cells along the D2 direction. Exemplarily, the second storage cells spaced apart along the D1 direction and the D2 direction can be isolated by SOD.

[0105] Here, the first conductive line may also be referred to as a bottom bit line, the second conductive line may also be referred to as a bottom word line, and the first memory cell disposed at the intersection between the first conductive line and the second conductive line may also be referred to as a bottom memory cell. The third conductive line may also be referred to as a top word line, the fourth conductive line may also be referred to as a top bit line, and the second memory cell disposed at the intersection between the third conductive line and the fourth conductive line may also be referred to as a top memory cell.

[0106] like Figure 3D As shown, an embodiment of the present disclosure provides a phase change memory, which includes: first storage units 304 arranged at intervals along the D1 direction and the D2 direction; the D1 direction and the D2 direction intersect; a first conductive line 308 provided on one side of the first storage unit 304, and the first conductive line 308 extends along the D2 direction; a second conductive line 320 provided on a side of the first storage unit 304 away from the first conductive line 308, and the second conductive line 320 extends along the D1 direction; a first dielectric layer 312 provided between adjacent first conductive lines 308, and the first dielectric layer 312 covers two side walls of the first conductive line 308 that are oppositely arranged along the D1 direction; and a second dielectric layer 316 provided between the first dielectric layers 312 on the side walls of adjacent first conductive lines 308.

[0107] Here, the phase change memory 300 further includes: a first isolation layer 306 is further provided between adjacent first storage units 304 along the D1 direction. The first dielectric layer 312 includes a first portion and a second portion, the first portion of the first dielectric layer 312 covers two side walls of the first conductive line 308 that are oppositely arranged along the D1 direction, and the second portion of the first dielectric layer 312 covers the surface of the first isolation layer 306. The second dielectric layer 316 is provided between the first dielectric layers 312 of adjacent first conductive lines 308, and the second dielectric layer 316 is in contact with the first portion and the second portion of the first dielectric layer 312. The first dielectric layer 312 covers two side walls of the second dielectric layer 316 that are oppositely arranged along the D1 direction and covers the surface of the second dielectric layer 316 close to the first isolation layer 306, that is, the first dielectric layer 312 partially surrounds the second dielectric layer 316.

[0108] In some embodiments, the density of the second dielectric layer 316 is greater than the density of the first dielectric layer 312 .

[0109] In some embodiments, the phase change memory 300 also includes: a third conductive line arranged on a side of the first conductive line 308 away from the first storage unit 304, the third conductive line extends along the D2 direction, and the first conductive line and the third conductive line are connected one-to-one; a second storage unit arranged on a side of the third conductive line away from the first conductive line, the second storage unit is arranged at intervals along the D1 direction and the D2 direction; a fourth conductive line arranged on a side of the second storage unit away from the third conductive line, and the fourth conductive line extends along the D1 direction.

[0110] refer to Figure 5 , Figure 5 A block diagram of a memory system provided by an embodiment of the present disclosure. Figure 5 As shown, an embodiment of the present disclosure further provides a memory system, the memory system 400 comprising: the phase change memory 300 as in the above technical solution; and a controller 402 coupled to the phase change memory 300 and configured to control the phase change memory 300 .

[0111] The disclosed embodiment provides a phase change memory and a manufacturing method thereof. In the disclosed embodiment, a first dielectric layer is formed to cover the side wall and top surface of the first conductive line to protect the side wall and top surface of the first conductive line in the subsequent process of forming the second dielectric layer; a second dielectric layer is formed to fill the gap between adjacent first conductive lines; in the process of flattening the second dielectric layer and the first dielectric layer, the removal rate of the second dielectric layer is lower than the removal rate of the first dielectric layer, which is beneficial to reducing the height difference between the top surface of the first conductive line and the surface of the second dielectric layer, so that the top surface of the first conductive line and the surface of the second dielectric layer are basically flush, thereby facilitating the improvement of the yield of the phase change memory and improving the electrical parameters of the phase change memory.

[0112] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0113] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a phase change memory, characterized in that: The method comprises: A semiconductor structure is provided, comprising: a first memory cell; an isolation layer disposed between adjacent first memory cells; a first conductive line disposed on one side of the first memory cell, wherein a surface of the first conductive line protrudes from a surface of the isolation layer, and adjacent first conductive lines and the isolation layer jointly form a first groove; forming a first dielectric layer covering the sidewall and bottom of the first groove and covering the first conductive line to form a second groove in the first groove; forming a second dielectric layer covering the sidewall and bottom of the second groove and covering the first dielectric layer; A planarization process is performed to expose the first conductive line; wherein, during the planarization process, a removal rate of the second dielectric layer is lower than a removal rate of the first dielectric layer.

2. The manufacturing method according to claim 1, characterized in that: The density of the second dielectric layer is greater than the density of the first dielectric layer.

3. The manufacturing method according to claim 1, characterized in that: The thickness of the second dielectric layer is greater than that of the first dielectric layer.

4. The manufacturing method according to claim 1, characterized in that: The thickness of the second dielectric layer ranges from 150 to 200 angstroms, and the thickness of the first dielectric layer ranges from 50 to 100 angstroms.

5. The manufacturing method according to claim 1, characterized in that: The process of forming the first dielectric layer includes a first atomic layer deposition process, and the process of forming the second dielectric layer includes a second atomic layer deposition process; wherein the radio frequency power in the second atomic layer deposition process is greater than the radio frequency power in the first atomic layer deposition process.

6. The manufacturing method according to claim 5, characterized in that: The radio frequency power range in the first atomic layer deposition process is 300-500W; the radio frequency power range in the second atomic layer deposition process is 800-1000W.

7. The manufacturing method according to claim 5, characterized in that: The deposition time in the first atomic layer deposition process is shorter than the deposition time in the second atomic layer deposition process.

8. The manufacturing method according to claim 1, characterized in that: The ratio between the removal rates of the second dielectric layer and the first conductive line is in the range of 22-24.

9. A phase change memory, characterized in that: The phase change memory is manufactured by the manufacturing method according to any one of claims 1 to 8, and the phase change memory comprises: First storage units are arranged at intervals along a first direction; A first conductive line disposed at one side of the first storage unit and extending along a second direction, wherein the second direction intersects with the first direction; a first dielectric layer disposed between adjacent first conductive lines, the first dielectric layer covering two side walls of the first conductive line that are oppositely disposed along the first direction; A second dielectric layer is disposed between the first dielectric layers adjacent to the side walls of the first conductive line.

10. The memory according to claim 9, characterized in that: The density of the second dielectric layer is greater than the density of the first dielectric layer.

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