Vertical field effect transistor device and preparation method thereof
By forming multi-layer sacrificial layers on the substrate surface and etching to form pits, and forming control gates in the pits, the problems of poor performance and complex preparation processes of existing vertical field effect transistor devices are solved, and the channel length is achieved Accurate control and improvements in device performance.
Patent Information
- Application Number
- CN202411552312.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-02-07
AI Technical Summary
The existing vertical field effect transistor devices have poor performance and complex preparation processes, resulting in uneven channel lengths and unstable device performance.
By sequentially forming the first sacrificial layer, the second sacrificial layer and the third sacrificial layer on the substrate surface, and etching a portion of the third sacrificial layer and all the second sacrificial layers to be between the first sacrificial layer and the third sacrificial layer A pit is formed, a control gate is formed in the pit, and a side wall is formed on both sides of the channel to accurately define the channel length and gate length to reduce process deviation.
Accurate control of channel length is achieved, process deviations in the preparation of vertical field effect transistors are reduced, device performance is improved, and preparation process is simplified.
Smart Images
Figure CN119403156A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a vertical field effect transistor device and a preparation method thereof. Background Art
[0002] Field Effect Transistor (FET) has the advantages of high input resistance, low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, and wide safe operating area. It is widely used in integrated circuit design.
[0003] With the continuous development of the integrated circuit industry, the small size effect caused by the reduction of the size of the traditional planar MOSFET (metal-oxide semiconductor field effect transistor, metal-oxide semiconductor FET) has become more and more prominent, thus limiting the further integration of integrated circuits. In order to solve the small size effect of the traditional planar MOSFET, the researchers proposed the vertical field effect transistor (Vertical Field Effect Transistor, VFET) with its unique structural design. By vertically erecting the nanowire / nanosheet channel structure on the substrate, the source / drain (S / D) region is formed above and below the nanowire / nanosheet channel structure, respectively, thereby transferring the gate length, source and drain volume and other dimensional parameters of the traditional planar MOSFET to the vertical direction, thereby further reducing the area of the device in the planar direction, greatly improving the device's integration.
[0004] At present, VFET devices generally adopt the method of first depositing a sacrificial silicon layer and then etching to define the channel length in the channel preparation. However, the deposition thickness and etching depth of the sacrificial silicon layer are difficult to accurately control, resulting in uneven channel length, thus affecting the performance of the device. Moreover, the top-down preparation scheme currently used makes the top source / drain and the bottom source / drain of the VFET device structurally asymmetric, which in turn causes differences in the quality of the two regions during the preparation process. The upward lead-out of the bottom source / drain brings higher RC delay and isolation requirements, which has an adverse effect on the overall performance and reliability of the device. In addition, the existing VFET device structure is relatively complex and the manufacturing process is relatively cumbersome, which limits the realization of its large-scale integrated application. Summary of the invention
[0005] The object of the present invention is to provide a vertical field effect transistor device and a method for preparing the same, so as to solve the problems of poor performance and complicated preparation process of the existing vertical field effect transistor device.
[0006] In order to solve the above technical problems, the present invention provides a method for preparing a vertical field effect transistor device, comprising: providing a substrate; etching the substrate to form a channel; An interface oxide layer and a dielectric layer are sequentially formed on the channel surface; sequentially forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer on the surface of the substrate; etching a portion of the third sacrificial layer and removing the entire second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer; forming a control gate in the pit; Removing the interface oxide layer and dielectric layer at the top of the trench; removing the third sacrificial layer and forming first sidewall spacers on both sides of the trench; forming a source electrode on a surface of the channel; Forming a source metal interconnection on the top of the source, and forming a source isolation layer on the surface of the first sidewall and around the source; removing the substrate and the first sacrificial layer, and forming second sidewalls on both sides of the trench; forming a drain on a surface of the channel; A drain metal interconnection is formed on the top of the drain, and a drain isolation layer is formed on the surface of the second sidewall and around the drain.
[0007] Optionally, in the method for preparing the vertical field effect transistor device, the dielectric layer is a high-k dielectric layer.
[0008] Optionally, in the method for preparing the vertical field effect transistor device, the method for sequentially forming an interface oxide layer and a dielectric layer on the channel surface includes: Using an epitaxial growth process, epitaxially growing an interface oxide layer and a dielectric layer on the substrate and the channel surface in sequence; The interface oxide layer and the dielectric layer on the substrate are etched back until the substrate is exposed.
[0009] Optionally, in the method for preparing the vertical field effect transistor device, the etching selectivity of the second sacrificial layer is greater than the etching selectivity of the first sacrificial layer, and greater than the etching selectivity of the third sacrificial layer.
[0010] Optionally, in the preparation method of the vertical field effect transistor device, the material of the first sacrificial layer, the second sacrificial layer and the third sacrificial layer is SiGe; the Ge content of the second sacrificial layer is higher than the Ge content of the first sacrificial layer, and higher than the Ge content of the third sacrificial layer; the Ge content of the first sacrificial layer is consistent with the Ge content of the third sacrificial layer.
[0011] Optionally, in the method for preparing the vertical field effect transistor device, the method of etching part of the third sacrificial layer and removing the entire second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer includes: A pit area is defined on the surface of the third sacrificial layer using a photoresist; Photolithography the third sacrificial layer and a portion of the second sacrificial layer in the pit area using a photolithography process; Removing photoresist; The entire second sacrificial layer is removed.
[0012] Optionally, in the method for preparing the vertical field effect transistor device, the method for forming the control gate in the pit includes: The gate metal is epitaxially grown in the pit by using an epitaxial growth process to form a control gate.
[0013] Optionally, in the method for preparing the vertical field effect transistor device, the method for removing the interface oxide layer and the dielectric layer at the top of the channel includes: A chemical mechanical polishing process is adopted to remove the interface oxide layer and the dielectric layer on the top of the channel, and to make the channel surface flush with the surface of the third sacrificial layer.
[0014] Optionally, in the method for preparing the vertical field effect transistor device, the method for removing the third sacrificial layer and forming the first spacers on both sides of the channel includes: removing the third sacrificial layer; Depositing a sidewall dielectric layer, wherein the sidewall dielectric layer covers the channel, the gate metal layer, the dielectric layer and the interface oxide layer; The sidewall dielectric layer is etched back to expose the trench, thereby obtaining a first sidewall.
[0015] Optionally, in the method for preparing the vertical field effect transistor device, the material of the source and the drain is Si, SiGe, SiC or other III-V group or II-VI group compound semiconductor materials.
[0016] Optionally, in the method for preparing the vertical field effect transistor device, the source and the drain are doped with the same ions, and the doping concentration is heavy.
[0017] Optionally, in the method for preparing the vertical field effect transistor device, the material of the first sidewall spacer and the second sidewall spacer is an insulating low-k dielectric material.
[0018] Optionally, in the method for preparing the vertical field effect transistor device, the material of the first sidewall spacer and the second sidewall spacer is silicon nitride, SiCN or SiOCN.
[0019] Optionally, in the method for preparing the vertical field effect transistor device, the method further comprises: A through hole is formed in the source isolation layer and the drain isolation layer, and the bottom of the through hole exposes the gate metal layer.
[0020] In order to solve the above technical problems, the present invention also provides a vertical field effect transistor device, which is prepared using the preparation method of the vertical field effect transistor device as described in any of the above items, and the vertical field effect transistor device includes a drain, a channel and a source connected in sequence from top to bottom; and gates are formed on both sides of the channel.
[0021] Optionally, in the vertical field effect transistor device, the gate includes an interface oxide layer, a dielectric layer and a control gate; the interface oxide layer, the dielectric layer and the control gate are formed in sequence on both sides of the channel from the inside to the outside; the two ends of the interface oxide layer and the dielectric layer are in contact with the source and the drain respectively; the control gate is isolated from the source by a first side wall, and is isolated from the drain by a second side wall.
[0022] Optionally, in the vertical field effect transistor device, the channel is a nanowire channel or a nanosheet channel.
[0023] The vertical field effect transistor device and the preparation method thereof provided by the present invention include: providing a substrate; etching the substrate to form a channel; sequentially forming an interface oxide layer and a dielectric layer on the surface of the channel; sequentially forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer on the surface of the substrate; etching part of the third sacrificial layer and removing all of the second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer; forming a control gate in the pit; removing the interface oxide layer and the dielectric layer at the top of the channel; removing the third sacrificial layer and forming a first sidewall on both sides of the channel; forming a source on the surface of the channel; forming a source metal interconnection on the top of the source, and forming a source isolation layer on the surface of the first sidewall and around the source; removing the substrate and the first sacrificial layer, and forming a second sidewall on both sides of the channel; forming a drain on the surface of the channel; forming a drain metal interconnection on the top of the drain, and forming a drain isolation layer on the surface of the second sidewall and around the drain. The gate length of the transistor is precisely defined by the growth thickness of the second sacrificial layer, and the channel is protected from being affected in subsequent processes by the first and third sacrificial layers, thereby achieving precise control of the channel length and effectively reducing process deviations in the preparation of field effect transistors. This ensures the device performance of the field effect transistor while reducing the complexity of the preparation process, thus solving the problem of poor device performance and complex preparation process of existing vertical field effect transistors. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 A flow chart of a method for preparing a vertical field effect transistor device provided in this embodiment; Figures 2A to 2U A schematic diagram of the structure of a vertical field effect transistor device corresponding to each step in the preparation method provided in this embodiment; Figure 3A schematic diagram of the three-dimensional structure of a vertical field effect transistor device provided in this embodiment; The descriptions of the reference numerals are as follows: 100-substrate; 110-channel; 120-interface oxide layer; 130-dielectric layer; 140-first sacrificial layer; 150-second sacrificial layer; 160-third sacrificial layer; 170-pit; 180-control gate; 190-sidewall dielectric layer; 191-first sidewall; 200-source; 210-source metal interconnection; 220-source isolation layer; 230-second sidewall; 240-drain; 250-drain metal interconnection; 260-drain isolation layer; 270-through hole. DETAILED DESCRIPTION
[0025] The vertical field effect transistor device and the method for preparing the same proposed by the present invention are further described in detail below in combination with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often part of the actual structure. In particular, the emphasis of each accompanying drawing is different, and sometimes different proportions are used.
[0026] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0027] This embodiment provides a method for preparing a vertical field effect transistor device, such as Figure 1 As shown, including: S01, providing a substrate; S02, etching the substrate to form a channel; S03, forming an interface oxide layer and a dielectric layer in sequence on the channel surface; S04, sequentially forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer on the surface of the substrate; S05, etching a portion of the third sacrificial layer and removing the entire second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer; S06, forming a control gate in the pit; S07, removing the interface oxide layer and dielectric layer at the top of the channel; S08, removing the third sacrificial layer and forming first sidewall spacers on both sides of the trench; S09, forming a source electrode on the surface of the channel; S10, forming a source metal interconnection on the top of the source, and forming a source isolation layer on the surface of the first sidewall and around the source; S11, removing the substrate and the first sacrificial layer, and forming second sidewall spacers on both sides of the trench; S12, forming a drain on the channel surface; S13, forming a drain metal interconnection on the top of the drain, and forming a drain isolation layer on the surface of the second sidewall and around the drain.
[0028] The method for preparing a vertical field effect transistor device provided in this embodiment accurately defines the gate length of the transistor by the growth thickness of the second sacrificial layer, and protects the channel from being affected in subsequent processes by the first sacrificial layer and the third sacrificial layer, thereby achieving accurate control of the channel length and effectively reducing the process deviation in the preparation process of the vertical field effect transistor, thereby reducing the complexity of the preparation process while ensuring the device performance of the vertical field effect transistor, and solving the problem of poor performance and complex preparation process of existing vertical field effect transistor devices.
[0029] The method for preparing the vertical field effect transistor device provided in this embodiment adopts the gate-around technology, and the gate structure is surrounded by the sidewalls of the nanowire / nanosheet channel to achieve all-round gate control capability and has excellent electrostatic performance. The gate-around technology combined with the vertical field effect transistor can greatly improve the integration and device performance of the transistor.
[0030] The method for preparing the vertical field effect transistor device provided in this embodiment adopts back power supply and back signal technology, and utilizes the structural characteristics of the vertical gate field effect transistor that the source / drain region is located at the bottom of the device. Power routing and signal routing are realized by leading out metal interconnections at the source and drain of the vertical field effect transistor, which effectively alleviates the additional area sacrifice caused by wiring rules in the front routing, allows a wider power line width, reduces the RC delay of the back end, and improves the chip performance while reducing the chip area.
[0031] Specifically, in this embodiment, Figure 2A As shown, step S01, providing a substrate 100. Specifically, the substrate 100 can be a silicon substrate, so the material of the channel formed by etching in step S02 is also silicon. Of course, in practical applications, substrates of other materials can also be selected according to actual needs, and this application does not limit this.
[0032] Furthermore, in this embodiment, if Figure 2BAs shown, in step S02, the substrate 100 is etched to form a channel 110. The method of etching the substrate 100 to form the channel 110 is well known to those skilled in the art, and will not be described in detail in this application.
[0033] Furthermore, in this embodiment, in step S03 , an interface oxide layer 120 and a dielectric layer 130 are sequentially formed on the surface of the channel 110 .
[0034] Specifically, in this embodiment, first, Figure 2C As shown, an epitaxial growth process is used to sequentially epitaxially grow an interface oxide layer 120 and a dielectric layer 130 on the substrate and the channel surface; then, as shown in FIG. Figure 2D As shown, an etch-back process is used to etch back the interface oxide layer 120 and the dielectric layer 130 on the substrate 100 until the substrate 100 is exposed. In this way, the interface oxide layer 120 and the dielectric layer 130 are only formed on the surface of the channel 110 .
[0035] This embodiment can achieve self-alignment of the channel structure and reduce the requirement for overlay accuracy by selecting the back-etching process when preparing the interface oxide layer 120 and the dielectric layer 130; at the same time, it can also reduce the number of photolithography steps, thereby simplifying the process and reducing the difficulty of process integration.
[0036] In this embodiment, the interface oxide layer 120 may be made of silicon oxide or other materials. The dielectric layer 130 is a high-k dielectric layer. Here, k refers to the dielectric constant, and a high-k dielectric refers to a dielectric with a dielectric constant k greater than 3.9, including but not limited to hafnium dioxide, zirconium oxide, aluminum oxide, barium titanate, etc.
[0037] Furthermore, in this embodiment, if Figure 2E As shown, in step S04 , a first sacrificial layer 140 , a second sacrificial layer 150 and a third sacrificial layer 160 are sequentially formed on the surface of the substrate 100 .
[0038] Specifically, in this embodiment, an epitaxial growth process may be used to sequentially epitaxially grow the first sacrificial layer 140 , the second sacrificial layer 150 , and the third sacrificial layer 160 on the surface of the substrate 100 .
[0039] The etching selectivity of the second sacrificial layer 150 is greater than the etching selectivity of the first sacrificial layer 140, and greater than the etching selectivity of the third sacrificial layer 160. In this way, it is convenient to form a pit structure in the subsequent process.
[0040] In order to effectively distinguish the three sacrificial layers and reduce the process complexity as much as possible, in practical applications, the materials of the first sacrificial layer 140, the second sacrificial layer 150 and the third sacrificial layer 160 are SiGe; the Ge content of the second sacrificial layer 150 is higher than the Ge content of the first sacrificial layer 140, and higher than the Ge content of the third sacrificial layer 160; the Ge content of the first sacrificial layer 140 is consistent with the Ge content of the third sacrificial layer 160. For example, the material of the first sacrificial layer 140 is SiGe. 0.7 Ge 0.3 The material of the second sacrificial layer 150 is Si 0.5 Ge 0.5 The material of the third sacrificial layer 160 is Si 0.7 Ge 0.3 .
[0041] Furthermore, in this embodiment, in step S05 , a portion of the third sacrificial layer 160 is etched, and all of the second sacrificial layer 150 is removed, so as to form a pit 170 between the first sacrificial layer 140 and the third sacrificial layer 160 .
[0042] Specifically, in order to ensure the process accuracy, the photolithography process can also be used: first, a pit area is defined on the surface of the third sacrificial layer 160 using photoresist; then, as shown in FIG. Figure 2F As shown, the third sacrificial layer 160 and part of the second sacrificial layer 150 in the pit area are photolithographically processed; then, the photoresist is removed; finally, as shown in FIG. Figure 2G As shown, the entire second sacrificial layer 150 is removed, thereby obtaining a recess 170 .
[0043] At this time, the pit 170 has the first sacrificial layer 140 as the bottom, the dielectric layer 130 as the sidewall, and the third sacrificial layer 160 as the top, and has an open pit structure at the top. In addition, the second sacrificial layer 150 no longer exists in the semiconductor device at this time. Thanks to the etching selectivity of the three sacrificial layers, after the second sacrificial layer 150 is completely removed, the first sacrificial layer 140 and the third sacrificial layer 160 are retained, thereby ensuring that the channel 110 is not affected in the subsequent process, achieving precise control of the channel length, and effectively reducing the process deviation in the preparation process of the vertical field effect transistor.
[0044] Furthermore, in this embodiment, if Figure 2H As shown, in step S06 , a control gate 180 is formed in the pit 170 .
[0045] Specifically, in this embodiment, an epitaxial growth process may be used to epitaxially grow a gate metal in the pit 170 to form the control gate 180. The gate metal may be made of metal or semiconductor material.
[0046] Furthermore, in this embodiment, if Fig.2I As shown, in step S07 , the interface oxide layer 120 and the dielectric layer 130 on the top of the channel 110 are removed.
[0047] Specifically, in this embodiment, a chemical mechanical polishing process may be used to remove the interface oxide layer 120 and the dielectric layer 130 on the top of the channel 110 , and make the surface of the channel 114 flush with the surface of the third sacrificial layer 160 .
[0048] In practical applications, due to process influences, the formed control gate 180 may be higher than the surface of the third sacrificial layer 160 . In this case, a chemical mechanical polishing process may be used in this step to simultaneously make the surface of the control gate 180 flush with the surface of the third sacrificial layer 160 .
[0049] Furthermore, in this embodiment, in step S08 , the third sacrificial layer 160 is removed, and first spacers 191 are formed on both sides of the trench 110 .
[0050] Specifically, the first sidewall spacer 191 may be formed by using a deposition process and an etching back process: first, Figure 2J As shown, the third sacrificial layer 160 is removed, for example, the third sacrificial layer 160 can be removed by an etching process; then, as shown Figure 2K As shown, a spacer dielectric layer 190 is deposited on the surface of the semiconductor device, and the spacer dielectric layer 190 covers the channel 110, the interface oxide layer 160 and the gate metal layer 180; finally, as shown Figure 2L As shown, the spacer dielectric layer 190 is etched back to expose the trench 110 , thereby obtaining a first spacer 191 .
[0051] In practical applications, the material of the first sidewall 191 is an insulating low-k dielectric material, wherein k refers to the dielectric constant. The insulating low-k dielectric refers to a dielectric with a dielectric constant k less than 3.9 and insulating properties, such as silicon nitride, SiCN or SiOCN.
[0052] Of course, in practical applications, a photolithography process may be used to form the first sidewall 191. In this embodiment, by selecting the back-etching process when preparing the first sidewall 191, the self-alignment of the channel structure can be achieved, and the requirement for overlay accuracy can be reduced; at the same time, the photolithography steps can be reduced, thereby simplifying the process and reducing the difficulty of process integration.
[0053] It should be noted that if the photolithography process is adopted, the thickness of the first sidewall 191 can be guaranteed to be consistent with the thickness of the sidewall dielectric layer 190; and if the back-etching process is adopted, the thickness of the first sidewall 191 will be less than the thickness of the sidewall dielectric layer 190. Therefore, when the back-etching process is adopted, in order to ensure that the height of the first sidewall 191 in the vertical field effect transistor meets the design requirements, when the sidewall dielectric layer 190 is formed, its thickness should be greater than the designed height of the first sidewall 191.
[0054] Furthermore, in this embodiment, if Figure 2M As shown, in step S09 , a source 200 is formed on the surface of the channel 110 .
[0055] Specifically, an epitaxial growth process may be used to form the source 200 on the surface of the channel 110. The source 200 may be made of Si, SiGe, SiC or other III-V or II-VI compound semiconductor materials.
[0056] And, in this embodiment, if Figure 2N As shown, in step S10 , a source metal interconnection 210 is formed on the top of the source 200 , and a source isolation layer 220 is formed on the surface of the first spacer 191 and around the source 200 .
[0057] Specifically, a deposition process and an etching process may be selected to sequentially form the source metal interconnect 210 and the source isolation layer 220 . The specific implementation method is well known to those skilled in the art and will not be described in detail in this application.
[0058] In practical applications, after this step, a through hole 270 may be formed in the source isolation layer 220, and the bottom of the through hole 270 exposes the gate metal layer 180. Fig.2O As shown, the through hole 270 can be formed by using a photolithography process, and the specific process is well known to those skilled in the art, and will not be described in detail in this application.
[0059] Furthermore, in this embodiment, in step S11 , the substrate 100 and the first sacrificial layer 140 are removed, and a second spacer 230 is formed on both sides of the trench 110 .
[0060] In practical applications, in order to facilitate the implementation of the process, the semiconductor device can be turned over first, and the source metal interconnect 210 and the source isolation layer 220 are supported on the carrier silicon wafer so that the substrate 100 is located on the top. Figure 2P In this way, the reliable preparation of the second sidewall and the drain originally located at the bottom can be ensured, and at the same time, the arrangement and preparation of the back power line and the back signal line can be met, thereby further reducing the device area and improving the integration.
[0061] Afterwards, if Figure 2QAs shown, the substrate 100 and the first sacrificial layer 140 are removed by an etching process. Figure 2R As shown, similar to the formation of the first sidewall 191, the second sidewall 230 is formed on both sides of the channel 110. In this embodiment, by selecting the same back-etching process when preparing the second sidewall 230, the self-alignment of the channel structure can be achieved, and the requirement for overlay accuracy can be reduced; at the same time, the number of photolithography steps can be reduced, thereby simplifying the process and reducing the difficulty of process integration.
[0062] In practical applications, the material of the second sidewall spacer 230 can be consistent with the material of the first sidewall spacer 191 , that is, an insulating low-k dielectric material such as silicon nitride, SiCN or SiOCN.
[0063] Further, in this embodiment, step S12 is similar to step S09, such as Figure 2S As shown, a drain 240 is formed on the surface of the channel 110 .
[0064] In order to reduce the process complexity, in this embodiment, the material of the drain 240 is consistent with the material of the source 200, and can be Si, SiGe, SiC or other III-V group, II-VI group compound semiconductor materials. For example, in an N-type device, the material of the source 200 and the drain 240 is SiC; in a P-type device, the material of the source 200 and the drain 240 is SiGe.
[0065] In practical applications, the source 200 and the drain 240 are doped with the same ions, and the doping concentration is heavy doping (1e16 cm-3~1e22 cm-3). For example, in an N-type device, the source 200 and the drain 240 are doped with As (arsenic) ions, and the doping concentration is 5e20 cm-3; in a P-type device, the source 200 and the drain 240 are doped with B (boron) ions, and the doping concentration is 5e20 cm-3.
[0066] And, in this embodiment, step S13 is similar to step S10, such as Figure 2T As shown, a drain metal interconnection 250 is formed on the top of the drain 240 , and a drain isolation layer 260 is formed on the surface of the second spacer 230 and around the drain 240 .
[0067] In practical applications, after this step, a through hole 270 may be formed in the drain isolation layer 260, and the bottom of the through hole 270 exposes the control gate 180. Figure 2U As shown, the through hole 270 can be formed by using a photolithography process, and the specific process is well known to those skilled in the art, and will not be described in detail in this application.
[0068] This embodiment also provides a vertical field effect transistor device, which is prepared by the method for preparing the vertical field effect transistor device as described above. Figure 3 As shown, the vertical field effect transistor device includes a drain 240, a channel 110 and a source 200 connected in sequence from top to bottom; a gate is formed on both sides of the channel 110 Specifically, in the present embodiment, the gate includes an interface oxide layer 120, a dielectric layer 130 and a control gate 180; the interface oxide layer 120, the dielectric layer 130 and the control gate 180 are sequentially formed on both sides of the channel 110 from the inside to the outside; the two ends of the interface oxide layer 120 and the dielectric layer 130 are in contact with the source 200 and the drain 240 respectively; the control gate 180 is isolated from the source 200 by a first side wall 191, and is isolated from the drain 240 by a second side wall 230.
[0069] In this way, by utilizing the surround gate technology and surrounding the control gate structure around the sidewalls of the channel, all-round gate control capability is achieved, thereby enabling the vertical field effect transistor to have superior electrostatic performance and greatly improving the integration and device performance of the vertical field effect transistor.
[0070] Furthermore, in this embodiment, the channel 110 is a nanowire channel or a nanosheet channel.
[0071] In practical applications, the vertical field effect transistor can also form a source metal interconnection on the top of the source 200, and form a source isolation layer on the surface of the first side wall 191 and around the source 200; form a drain metal interconnection on the top of the drain 240, and form a drain isolation layer on the surface of the second side wall 230 and around the drain 240.
[0072] In this way, the back power supply and back signal technology can be used, and the structural characteristics of the source / drain region of the vertical gate field effect transistor being located at the bottom of the device can be utilized. The power routing and signal routing can be realized by leading out metal interconnections at the source and drain of the vertical field effect transistor, which effectively alleviates the additional area sacrifice caused by the wiring rules in the front routing, allows a wider power line width, reduces the RC delay at the back end, and improves the chip performance while reducing the chip area.
[0073] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.
[0074] The vertical field effect transistor device and the preparation method thereof provided in the present embodiment include: providing a substrate; etching the substrate to form a channel; sequentially forming an interface oxide layer and a dielectric layer on the surface of the channel; sequentially forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer on the surface of the substrate; etching part of the third sacrificial layer and removing all of the second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer; forming a control gate in the pit; removing the interface oxide layer and the dielectric layer at the top of the channel; removing the third sacrificial layer and forming a first sidewall on both sides of the channel; forming a source on the surface of the channel; forming a source metal interconnection on the top of the source, and forming a source isolation layer on the surface of the first sidewall and around the source; removing the substrate and the first sacrificial layer, and forming a second sidewall on both sides of the channel; forming a drain on the surface of the channel; forming a drain metal interconnection on the top of the drain, and forming a drain isolation layer on the surface of the second sidewall and around the drain. The gate length of the transistor is precisely defined by the growth thickness of the second sacrificial layer, and the channel is protected from being affected in subsequent processes by the first and third sacrificial layers, thereby achieving precise control of the channel length and effectively reducing the process deviation in the preparation process of the vertical field effect transistor, thereby reducing the complexity of the preparation process while ensuring the device performance of the vertical field effect transistor, solving the problem of poor device performance and complex preparation process of existing vertical field effect transistors.
[0075] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for preparing a vertical field effect transistor device, characterized in that: include: providing a substrate; etching the substrate to form a channel; An interface oxide layer and a dielectric layer are sequentially formed on the channel surface; sequentially forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer on the surface of the substrate; etching a portion of the third sacrificial layer and removing the entire second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer; forming a control gate in the pit; Removing the interface oxide layer and dielectric layer at the top of the trench; removing the third sacrificial layer and forming first sidewall spacers on both sides of the trench; forming a source electrode on a surface of the channel; Forming a source metal interconnection on the top of the source, and forming a source isolation layer on the surface of the first sidewall and around the source; removing the substrate and the first sacrificial layer, and forming second sidewalls on both sides of the trench; forming a drain on a surface of the channel; A drain metal interconnection is formed on the top of the drain, and a drain isolation layer is formed on the surface of the second sidewall and around the drain.
2. The method for preparing a vertical field effect transistor device according to claim 1, characterized in that: The dielectric layer is a high-k dielectric layer.
3. The method for preparing a vertical field effect transistor device according to claim 1, characterized in that: The method of sequentially forming an interface oxide layer and a dielectric layer on the channel surface comprises: Using an epitaxial growth process, epitaxially growing an interface oxide layer and a dielectric layer on the substrate and the channel surface in sequence; The interface oxide layer and the dielectric layer on the substrate are etched back until the substrate is exposed.
4. The method for preparing a vertical field effect transistor device according to claim 1, characterized in that: The etching selectivity of the second sacrificial layer is greater than the etching selectivity of the first sacrificial layer, and greater than the etching selectivity of the third sacrificial layer.
5. The method for preparing a vertical field effect transistor device according to claim 4, characterized in that: The materials of the first sacrificial layer, the second sacrificial layer and the third sacrificial layer are SiGe; the Ge content of the second sacrificial layer is higher than the Ge content of the first sacrificial layer and higher than the Ge content of the third sacrificial layer; the Ge content of the first sacrificial layer is consistent with the Ge content of the third sacrificial layer.
6. The method for preparing a vertical field effect transistor device according to claim 1, characterized in that: The method of etching part of the third sacrificial layer and removing all of the second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer includes: A pit area is defined on the surface of the third sacrificial layer using a photoresist; Photolithography the third sacrificial layer and a portion of the second sacrificial layer in the pit area using a photolithography process; Removing photoresist; The entire second sacrificial layer is removed.
7. The method for preparing a vertical field effect transistor device according to claim 1, characterized in that: The method for forming a control gate in a pit comprises: The gate metal is epitaxially grown in the pit by using an epitaxial growth process to form a control gate.
8. The method for preparing a vertical field effect transistor device according to claim 1, characterized in that: The method for removing the interface oxide layer and the dielectric layer at the top of the trench comprises: A chemical mechanical polishing process is adopted to remove the interface oxide layer and the dielectric layer on the top of the channel, and to make the channel surface flush with the surface of the third sacrificial layer.
9. The method for preparing a vertical field effect transistor device according to claim 1, characterized in that: The method of removing the third sacrificial layer and forming the first sidewall spacer on both sides of the trench includes: removing the third sacrificial layer; Depositing a sidewall dielectric layer, wherein the sidewall dielectric layer covers the channel, the gate metal layer, the dielectric layer and the interface oxide layer; The sidewall dielectric layer is etched back to expose the trench, thereby obtaining a first sidewall.
10. The method for preparing a vertical field effect transistor device according to claim 1, characterized in that: The source electrode and the drain electrode are made of Si, SiGe, SiC or other III-V group or II-VI group compound semiconductor materials.
11. The method for preparing a vertical field effect transistor device according to claim 1, characterized in that: The source and the drain are doped with the same ions, and the doping concentration is heavy.
12. The method for preparing a vertical field effect transistor device according to claim 1, characterized in that: The first sidewall spacer and the second sidewall spacer are made of insulating low-k dielectric material.
13. The method for preparing a vertical field effect transistor device according to claim 12, characterized in that: The first sidewall spacer and the second sidewall spacer are made of silicon nitride, SiCN or SiOCN.
14. The method for preparing a vertical field effect transistor device according to claim 1, characterized in that: The preparation method further comprises: A through hole is formed in the source isolation layer and the drain isolation layer, and the bottom of the through hole exposes the control gate.
15. A vertical field effect transistor device, prepared by the method for preparing a vertical field effect transistor device according to any one of claims 1 to 14, characterized in that: The vertical field effect transistor device comprises a drain, a channel and a source which are sequentially connected from top to bottom; and gates are formed on both sides of the channel.
16. The vertical field effect transistor device according to claim 15, characterized in that: The gate comprises an interface oxide layer, a dielectric layer and a control gate; the interface oxide layer, the dielectric layer and the control gate are formed in sequence from the inside to the outside on both sides of the channel; the two ends of the interface oxide layer and the dielectric layer are in contact with the source and the drain respectively; the control gate is isolated from the source by a first side wall and isolated from the drain by a second side wall.
17. The vertical field effect transistor device according to claim 15, characterized in that: The channel is a nanowire channel or a nanosheet channel.