Gallium nitride transistor based on polycrystalline silicon field plate and preparation method thereof

Abstract

The invention relates to a gallium nitride transistor based on a polycrystalline silicon field plate and a preparation method thereof, and belongs to the technical field of semiconductor devices. The transistor comprises a substrate, a GaN buffer layer, a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer which are sequentially arranged from bottom to top, a P-GaN cap layer and a first passivation layer are arranged on the upper side of the AlGaN barrier layer, a gate metal field plate is arranged on the upper side of the P-GaN cap layer, a second passivation layer is arranged on the upper sides of the gate metal field plate and the first passivation layer, and the second passivation layer is arranged on the upper side of the second passivation layer. Two sides of the GaN buffer layer are respectively provided with source electrode metal and drain electrode metal, the first passivation layer and the second passivation layer are provided with grooves, the bottoms of the grooves penetrate through the AlGaN barrier layer, and polycrystalline silicon field plates are arranged on the upper side of the source electrode metal, the upper side of the second passivation layer and in the grooves. By introducing the polycrystalline silicon field plate, interface charges are inhibited, and the electrical performance of the device is remarkably improved.

Description

Technical Field

[0001] The invention relates to a gallium nitride transistor based on a polysilicon field plate and a preparation method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] As the performance of Si-based materials gradually approaches the theoretical limit, third-generation semiconductors represented by GaN are gradually moving to the center of the semiconductor world. GaN materials have a series of excellent electrical properties such as high bandgap width, high electron mobility, high electron saturation velocity and high breakdown electric field. They show great application potential in the field of high-frequency, high-power and high-temperature electronic devices. They are widely used in power electronics and microwave radio frequency fields, and are also one of the core key technologies in the 5G field.

[0003] However, existing HEMT devices are susceptible to breakdown voltage limitations and interface charge in high-power, high-voltage environments, which reduces mobility, current performance, and withstand voltage. In device manufacturing, the process of forming the dielectric layer will introduce interface charges, such as PECVD plasma deposition. Traditional HEMT devices usually use metal field plates, but this structure cannot remove interface contamination charges, resulting in a significant reduction in channel mobility and current. In contrast, polysilicon field plates can deposit positive charges within themselves, thereby affecting and eliminating interface charges between oxides and semiconductors. They have significant advantages in suppressing interface charges and can maintain high mobility and current performance while increasing the breakdown voltage of the device. Therefore, the use of polysilicon field plates to replace metal field plates in high-power GaN HEMT devices has gradually attracted attention. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a gallium nitride transistor based on a polysilicon field plate, which suppresses interface charges and significantly improves the electrical performance of the device by introducing a polysilicon field plate.

[0005] The present invention also provides a method for preparing the above-mentioned gallium nitride transistor based on the polysilicon field plate.

[0006] The technical solution of the present invention is as follows: A gallium nitride transistor based on a polysilicon field plate comprises a substrate, a GaN buffer layer, a GaN channel layer, an AlN intercalation layer and an AlGaN barrier layer which are sequentially arranged from bottom to top, a P-GaN cap layer and a first passivation layer are arranged on the upper side of the AlGaN barrier layer, a gate metal field plate is arranged on the upper side of the P-GaN cap layer, a second passivation layer is arranged on the upper side of the gate metal field plate and the first passivation layer, a source metal and a drain metal are arranged on both sides of the GaN buffer layer respectively, a groove is arranged on the first passivation layer and the second passivation layer, the bottom of the groove penetrates to the AlGaN barrier layer, and a polysilicon field plate is arranged on the upper side of the source metal, the upper side of the second passivation layer and in the groove.

[0007] According to the present invention, preferably, the substrate material is silicon carbide, silicon or sapphire; The source metal and the drain metal materials are the same, which are metal stacks Ti / Al / Ni / Au, Ti / Al / Ti / Au or Ti / Al / Mo / Au; The material of the gate metal field plate is metal stack Ni / Au; The first passivation layer and the second passivation layer are made of the same material, namely SiN and SiO2.

[0008] According to the present invention, it is further preferred that the substrate material is silicon carbide; The source metal and drain metal are made of metal stack Ti / Al / Ni / Au; The material of the first passivation layer and the second passivation layer is SiO2.

[0009] Preferably, according to the present invention, the thickness of the GaN buffer layer is 0.8-3 μm; The thickness of the GaN channel layer is 10-300nm; The thickness of the AlN intercalation layer is 0.2-1.2nm; The thickness of the AlGaN barrier layer is 8-30 nm, wherein the molar ratio of Al is 10-26%; The thickness of the p-GaN cap layer is 1-1000nm and the doping concentration is 1×10 17 -1×10 20 cm -3 , the doping source is magnesium or boron; The thickness of the first passivation layer is 50-400nm; The length of the gate metal field plate is 1-5μm; The thickness of the second passivation layer is 50-300 nm.

[0010] According to the present invention, the thickness of the GaN buffer layer is further preferably 2 μm; The thickness of the GaN channel layer is 200nm; The thickness of the AlN intercalation layer is 0.5 nm; The thickness of the AlGaN barrier layer is 12.5 nm, wherein the molar ratio of Al is 18%; The thickness of the p-GaN cap layer is 100 nm and the doping concentration is 3×10 19 cm -3 ; The thickness of the first passivation layer is 260nm; The length of the gate metal field plate is 2 μm; The thickness of the second passivation layer is 100 nm.

[0011] Preferably according to the present invention, the gate-source spacing is 5 μm, the gate length is 2 μm, the gate-drain spacing is 13 μm, and the gate width is 100 μm.

[0012] The gate-source spacing is the distance from the gate electrode to the source electrode, the gate length is the length from the left end to the right end of the gate electrode, the gate-drain spacing is the distance from the gate electrode to the drain electrode, and the gate width is the side width of the gate electrode.

[0013] The method for preparing the gallium nitride transistor based on the polysilicon field plate comprises the following steps: S1, sequentially growing a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer and a p-GaN cap layer on a substrate; S2, dry etching the p-GaN cap layer except for the gate electrode position; S3, removing the GaN channel layer, AlN intercalation layer, and AlGaN barrier layer outside the device by dry etching to form a mesa; S4, evaporating source metal and drain metal at the mesa position respectively; S5, annealing the drain metal and source metal regions to form ohmic contacts; S6, depositing a first passivation layer on the P-GaN cap layer and the AlGaN barrier layer; S7, opening a hole in the first passivation layer in the gate electrode region by dry etching; S8, evaporating a gate metal field plate in the opening area, wherein the gate metal field plate extends to the first passivation layer on one side; S9, depositing a second passivation layer over the gate metal field plate and the first passivation layer; S10, performing dry etching on the first passivation layer and the second passivation layer on one side of the gate electrode to form a groove; S11, growing a source polysilicon field plate on the upper side of the source metal, the upper side of the second passivation layer and in the groove to complete the preparation.

[0014] Preferably according to the present invention, in step S1, the growth method of the GaN buffer layer, GaN channel layer, AlN intercalation layer, AlGaN barrier layer and p-GaN cap layer is a high-quality film formation method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0015] Preferably according to the present invention, the dry etching method in step S2, step S3, step S7 and step S10 is inductively coupled plasma etching (ICP) or reactive ion etching (RIE).

[0016] Preferably, according to the present invention, the deposition method in step S6 and step S9 is a high-quality film-forming method such as plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

[0017] Preferably according to the present invention, the annealing treatment method of the source metal and the drain metal in step S5 is laser selective annealing.

[0018] The beneficial effects of the present invention are: 1. The introduction of the polysilicon field plate of the present invention effectively eliminates the interface contamination charge and significantly improves the mobility and current performance of the device. Compared with the metal field plate, the polysilicon field plate device has a higher breakdown voltage, which enhances the stability and reliability of the device in high-voltage applications. Moreover, the polysilicon field plate has excellent interface charge processing capabilities, can maintain interface stability in high-power environments, and reduce performance degradation. At the same time, the use of polysilicon to replace the metal field plate effectively reduces production defects and scrap rates, reduces the overall manufacturing cost, reduces the degradation and damage problems of the device in long-term operation, and extends the service life of the device.

[0019] 2. The present invention embeds the polysilicon field plate into the groove, shortens the distance between the polysilicon field plate and the barrier layer, makes the polysilicon field plate closer to the interface charges of these interfaces, and covers a larger area, which can more effectively offset the negative effects of the interface charges, reduce the carrier scattering caused by the interface charges, and improve the mobility of channel electrons; improve the conduction performance, significantly enhance the current driving capability and response speed of the device; moreover, the polysilicon field plate is close to the barrier layer, so that the polysilicon field plate can more directly affect the electric field distribution near the barrier layer, and effectively reduce the electric field peak.

[0020] At the same time, the groove structure makes the coupling between the barrier layer and the polysilicon field plate stronger, which can not only neutralize the interface charge, but also reduce the possibility of new interface charge accumulation due to process or thermal stress. The interface charge problem is dynamic, and the embedded field plate design helps to maintain interface stability for a long time.

[0021] The heat generated by the device when working at high power needs to be effectively dissipated. The etched grooves not only provide a better heat dissipation path for the polysilicon field plate, but also reduce the additional thermal resistance of the field plate, thereby enhancing the thermal stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural schematic diagram of the present invention; Figure 2 A comparison diagram of the mobility of the polysilicon field plate device of the present invention; Figure 3 A comparison diagram of transfer curves (linear curves) of the polysilicon field plate device of the present invention; Figure 4 A comparison diagram of transfer curves (logarithmic curves) of the polysilicon field plate device of the present invention; Figure 5 This is a comparison diagram of the output curves of the polysilicon field plate device of the present invention; Figure 6 A comparison diagram of the breakdown voltage of the polysilicon field plate device of the present invention; In the figure: 1. substrate; 2. GaN buffer layer; 3. GaN channel layer; 4. AlN intercalation layer; 5. AlGaN barrier layer; 6. P-GaN cap layer; 7. first passivation layer; 8. source metal; 9. drain metal; 10. polysilicon field plate; 11. gate metal field plate; 12. second passivation layer. DETAILED DESCRIPTION

[0023] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings, but is not limited thereto.

[0024] Embodiment 1: like Figure 1 As shown, the present embodiment provides a gallium nitride transistor based on a polysilicon field plate, comprising a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, an AlN intercalation layer 4 and an AlGaN barrier layer 5 arranged in sequence from bottom to top, a P-GaN cap layer 6 and a first passivation layer 7 are arranged on the upper side of the AlGaN barrier layer 5, a gate metal field plate 11 is arranged on the upper side of the P-GaN cap layer 6, a second passivation layer 12 is arranged on the upper side of the gate metal field plate 11 and the first passivation layer 7, a source metal 8 and a drain metal 9 are arranged on both sides of the GaN buffer layer 2, a groove is arranged on the first passivation layer 7 and the second passivation layer 12, the bottom of the groove penetrates to the AlGaN barrier layer 5, and a polysilicon field plate 10 is arranged on the upper side of the source metal 8, the upper side of the second passivation layer 12 and in the groove.

[0025] The material of the substrate 1 is silicon carbide; the material of the gate metal field plate 11 is the metal stack Ni / Au; the material of the source metal 8 and the drain metal 9 is the metal stack Ti / Al / Ni / Au; the material of the first passivation layer 7 and the second passivation layer 12 is SiO2.

[0026] The thickness of the GaN buffer layer 2 is 2 μm; the thickness of the GaN channel layer 3 is 200 nm; the thickness of the AlN intercalation layer 4 is 0.5 nm; the thickness of the AlGaN barrier layer 5 is 12.5 nm, wherein the molar ratio of Al is 18%; the thickness of the p-GaN cap layer 6 is 100 nm, and the doping concentration is 3×10 19 cm -3 ; The thickness of the first passivation layer 7 is 260 nm; The length of the gate metal field plate 11 is 2 μm; The thickness of the second passivation layer 12 is 100 nm.

[0027] The gate-source spacing is 5μm, the gate length is 2μm, the gate-drain spacing is 13μm, and the gate width is 100μm.

[0028] The method for preparing the gallium nitride transistor based on the polysilicon field plate comprises the following steps: S1, sequentially growing a GaN buffer layer 2, a GaN channel layer 3, an AlN intercalation layer 4, an AlGaN barrier layer 5 and a p-GaN cap layer 6 on a substrate 1; S2, dry etching the p-GaN cap layer 6 except for the gate electrode position; S3, removing the GaN channel layer 3, the AlN intercalation layer 4, and the AlGaN barrier layer 5 outside the device by dry etching to form a mesa; S4, evaporating source metal 8 and drain metal 9 at the mesa position respectively; S5, annealing in the drain metal 9 and source metal 8 regions to form ohmic contacts; S6, depositing a first passivation layer 7 on the P-GaN cap layer 6 and the AlGaN barrier layer 5; S7, opening a hole in the first passivation layer 7 in the gate electrode region by dry etching; S8, evaporating a gate metal field plate 11 in the opening area, wherein the gate metal field plate 11 extends to the first passivation layer 7 on one side; S9, depositing a second passivation layer 12 on the gate metal field plate 11 and the first passivation layer 7; S10, performing dry etching on the first passivation layer 7 and the second passivation layer 12 on one side of the gate electrode to form a groove; S11 , growing a source polysilicon field plate 10 on the upper side of the source metal 8 , the upper side of the second passivation layer 12 and in the groove to complete the preparation.

[0029] In step S1 , the growth method of the GaN buffer layer 2 , the GaN channel layer 3 , the AlN intercalation layer 4 , the AlGaN barrier layer 5 and the p-GaN cap layer 6 is metal organic chemical vapor deposition (MOCVD).

[0030] The dry etching method in step S2, step S3, step S7 and step S10 is inductively coupled plasma etching (ICP).

[0031] The deposition method in step S6 and step S9 is a high-quality film-forming method such as low-pressure chemical vapor deposition (LPCVD).

[0032] In step S5, the annealing method of the source metal and the drain metal is laser selective annealing.

[0033] The performance of the device prepared in this embodiment was verified in Sentaurus TCAD simulation, and the steps were as follows: (1) Simulation model construction: construct a two-dimensional structural model in Sentaurus TCAD software; (2) Simulation parameter setting: Set boundary conditions and initial conditions, including voltage and current. For the transfer curve, first apply a drain voltage of 10 V, then apply a variable gate voltage. For the output curve, increase the drain voltage from 0 V to 10 V at different gate voltages. For breakdown, first apply a gate voltage of -6 V to ensure depletion, then apply a drain voltage until breakdown. (3) Simulation process: Perform simulation to observe the changes in electrical properties of polysilicon field plates compared with metal field plates; (4) Result analysis: Figure 2 It can be seen that the channel mobility of this embodiment is twice as high as that of the traditional metal field plate, from 1200 cm 2 / V·s increased to 2500 cm 2 / V·s, by Figure 3 , Figure 4 , Figure 5 It can be found that the saturation current of this embodiment has been greatly improved while the threshold voltage remains unchanged. Figure 6 In the breakdown curve, taking the critical breakdown field strength of GaN material 3.3MV / cm as the judgment standard, the breakdown voltage of the polysilicon field plate device in this embodiment reaches 1050V, which is better than the 950V of the traditional metal field plate. This shows that the polysilicon field plate plays an important role in eliminating interface charges, improving device stability, and optimizing device performance.

[0034] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A gallium nitride transistor based on a polysilicon field plate, characterized in that: The invention comprises a substrate, a GaN buffer layer, a GaN channel layer, an AlN intercalation layer and an AlGaN barrier layer which are arranged in sequence from bottom to top; a P-GaN cap layer and a first passivation layer are arranged on the upper side of the AlGaN barrier layer; a gate metal field plate is arranged on the upper side of the P-GaN cap layer; a second passivation layer is arranged on the upper side of the gate metal field plate and the first passivation layer; source metal and drain metal are arranged on both sides of the GaN buffer layer respectively; grooves are arranged on the first passivation layer and the second passivation layer, and the bottom of the grooves penetrates to the AlGaN barrier layer; polysilicon field plates are arranged on the upper side of the source metal, the upper side of the second passivation layer and in the grooves.

2. The gallium nitride transistor based on polysilicon field plate according to claim 1, characterized in that: The substrate material is silicon carbide, silicon or sapphire; The source metal and the drain metal materials are the same, which are metal stacks Ti / Al / Ni / Au, Ti / Al / Ti / Au or Ti / Al / Mo / Au; The material of the gate metal field plate is metal stack Ni / Au; The first passivation layer and the second passivation layer are made of the same material, namely SiN and SiO2.

3. The gallium nitride transistor based on polysilicon field plate according to claim 2, characterized in that: The substrate material is silicon carbide; The source metal and drain metal are made of metal stack Ti / Al / Ni / Au; The material of the first passivation layer and the second passivation layer is SiO2.

4. The gallium nitride transistor based on polysilicon field plate according to claim 1, characterized in that: The thickness of the GaN buffer layer is 0.8-3μm; The thickness of the GaN channel layer is 10-300nm; The thickness of the AlN intercalation layer is 0.2-1.2nm; The thickness of the AlGaN barrier layer is 8-30 nm, wherein the molar ratio of Al is 10-26%; The thickness of the p-GaN cap layer is 1-1000nm and the doping concentration is 1×10 17 -1×10 20 cm -3 , the doping source is magnesium or boron; The thickness of the first passivation layer is 50-400nm; The length of the gate metal field plate is 1-5μm; The thickness of the second passivation layer is 50-300 nm.

5. The gallium nitride transistor based on polysilicon field plate according to claim 4, characterized in that: The thickness of the GaN buffer layer is 2 μm; The thickness of the GaN channel layer is 200nm; The thickness of the AlN intercalation layer is 0.5 nm; The thickness of the AlGaN barrier layer is 12.5 nm, wherein the molar ratio of Al is 18%; The thickness of the p-GaN cap layer is 100 nm and the doping concentration is 3×10 19 cm -3 ; The thickness of the first passivation layer is 260nm; The length of the gate metal field plate is 2 μm; The thickness of the second passivation layer is 100 nm.

6. The gallium nitride transistor based on polysilicon field plate according to claim 1, characterized in that: The gate-source spacing is 5μm, the gate length is 2μm, the gate-drain spacing is 13μm, and the gate width is 100μm.

7. The method for preparing a gallium nitride transistor based on a polysilicon field plate according to any one of claims 1 to 6, characterized in that: Here are the steps: S1, sequentially growing a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer and a p-GaN cap layer on a substrate; S2, dry etching the p-GaN cap layer except for the gate electrode position; S3, removing the GaN channel layer, AlN intercalation layer, and AlGaN barrier layer outside the device by dry etching to form a mesa; S4, evaporating source metal and drain metal at the mesa position respectively; S5, annealing the drain metal and source metal regions to form ohmic contacts; S6, depositing a first passivation layer on the P-GaN cap layer and the AlGaN barrier layer; S7, opening a hole in the first passivation layer in the gate electrode region by dry etching; S8, evaporating a gate metal field plate in the opening area, wherein the gate metal field plate extends to the first passivation layer on one side; S9, depositing a second passivation layer over the gate metal field plate and the first passivation layer; S10, performing dry etching on the first passivation layer and the second passivation layer on one side of the gate electrode to form a groove; S11, growing a source polysilicon field plate on the upper side of the source metal, the upper side of the second passivation layer and in the groove to complete the preparation.

8. The method for preparing a gallium nitride transistor based on a polysilicon field plate according to claim 7, characterized in that: In step S1 , the growth method of the GaN buffer layer, the GaN channel layer, the AlN intercalation layer, the AlGaN barrier layer and the p-GaN cap layer is metal organic chemical vapor deposition or molecular beam epitaxy.

9. The method for preparing a gallium nitride transistor based on a polysilicon field plate according to claim 7, characterized in that: The dry etching method in step S2, step S3, step S7 and step S10 is inductively coupled plasma etching or reactive ion etching; The deposition method in step S6 and step S9 is plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

10. The method for preparing a gallium nitride transistor based on a polysilicon field plate according to claim 7, characterized in that: In step S5, the annealing method of the source metal and the drain metal is laser selective annealing.

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