Phased array front-end structure and preparation method thereof

Abstract

The invention discloses a phased array front-end structure and a preparation method thereof. Comprising a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a third metal layer, a third dielectric layer, a fourth metal layer and a solder mask which are sequentially arranged on a substrate, an SU8 chip slot of a built-in chip arranged on the substrate, and an antenna substrate which is located at the top and is electrically connected with the third dielectric layer through a ball grid array (BGA), the chip and the silicon substrate are electrically connected through the lead bonding technology, and meanwhile the silicon substrate and the antenna substrate are interconnected through the ball grid array packaging technology. By forming the slot position in the SU-8 photoresist and directly mounting the chip on the surface of the silicon substrate, not only is the heat dissipation capability of the system enhanced, but also the distance between the chip and the ground plane of the antenna substrate above is effectively increased, and the deterioration of the performance of the chip is prevented. According to the manufacturing scheme, the combination of high performance and high heat dissipation capability of the phased array front-end system under high-density packaging is realized.

Description

Technical Field

[0001] The present invention relates to a technology in the field of radio frequency devices, specifically a phased array front-end structure and a preparation method thereof. Background Art

[0002] As modern communication and navigation technologies place increasing demands on the performance of phased array front-ends, high-performance, miniaturized, and low-cost new phased arrays have become the main direction of current RF technology development. Existing new phased array front-ends such as silicon adapter three-dimensional stacking technology, low-temperature co-fired ceramic technology (LTCC), and fan-out wafer-level packaging technology (FOWLP) have complex structures, high production costs, low yields, and average performance. Summary of the invention

[0003] The present invention aims to solve the problem that the structure of the existing phased array packaged antenna is complex, resulting in greater signal loss in the interconnection path and deterioration of system performance. A phased array front-end structure and a preparation method thereof are proposed. The chip is electrically connected to the silicon substrate using wire bonding technology, and the silicon substrate and the antenna substrate are interconnected using ball grid array packaging technology. By opening a slot in the SU-8 photoresist and directly mounting the chip on the surface of the silicon substrate, the heat dissipation capacity of the system is enhanced, and the distance between the chip and the ground plane of the antenna substrate above is effectively increased, thereby preventing the deterioration of the chip performance. This manufacturing scheme realizes the combination of high performance and high heat dissipation capacity of the phased array front-end system under high-density packaging.

[0004] The present invention is achieved through the following technical solutions:

[0005] The present invention relates to a phased array front-end structure, comprising: a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a third metal layer, a third dielectric layer, a fourth metal layer and a solder resist layer sequentially arranged on a substrate, an SU8 chip slot with a built-in chip arranged on the substrate, and an antenna substrate located on the top and electrically connected to the third dielectric layer through a ball grid array (BGA), wherein: the chip is electrically connected to the fourth metal layer respectively, through holes are arranged on the first to third dielectric layers, the first metal layer, the first dielectric layer and the second metal layer constitute a first redistribution layer (RDL); the second dielectric layer and the third metal layer constitute a second redistribution layer; the third dielectric layer, the fourth metal layer and the solder resist layer constitute a third redistribution layer.

[0006] The first metal layer is used for ground plane shielding layer, the second metal layer is used for RF signal, control signal or power network wiring, the third metal layer is used for ground plane shielding layer, control signal or power network wiring, and the fourth metal layer is used for RF signal, control signal or power network wiring.

[0007] The depth of the SU8 chip slot is 120 μm, and the bottom of the chip slot is the first metal layer, which is used for grounding the back side of the chip.

[0008] The first to third metal layers are all electroplated with 3 μm Cu, and the fourth metal layer is electroplated with 3 μm Cu, 1 μm Ni and 1 μm Au.

[0009] The first to third dielectric layers are all made of SU-8 photoresist with a thickness of 40 μm.

[0010] The thickness of the solder resist layer is 6 μm.

[0011] The present invention relates to a method for preparing the phased array front-end structure, wherein three layers of thick film SU-8 material are spin-coated on the surface of a silicon substrate as a dielectric layer to form a four-layer RDL for signal wiring. The thick film RDL is conducive to multi-layer radio frequency wiring and realizes complex system interconnection, specifically comprising:

[0012] Step 1: first, on a silicon substrate as a substrate, a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a third metal layer, a third dielectric layer, a fourth metal layer and a solder resist layer for subsequent BGA ball planting are sequentially manufactured;

[0013] Step 2: Use a photosensitive dry film exposure process to imprint the dry film on the surface of the silicon substrate, and expose the area where the chip is mounted after photolithography and development;

[0014] Step 3: Use dry degumming to process the photosensitive dry film on the wafer surface on the silicon substrate and the exposed SU8 photoresist, so that the first metal layer is exposed and a chip slot is formed in the SU8. Clean the silicon substrate and completely remove the residual photosensitive dry film;

[0015] Step 4: Use a steel mesh to plant BGA balls on the surface of the silicon substrate, and perform preliminary reflow soldering to fix the BGA; embed the chip into the SU8 slot and fix it with conductive silver paste;

[0016] Step 5: Make electrical connection between the chip and the silicon substrate by wire bonding; use a steel mesh to print solder paste on the surface of the LTCC antenna substrate, and align and reflow solder it with the silicon substrate to complete the production of the phased array front end.

[0017] The first to fourth metal layers are all made by electroplating.

[0018] Interconnection through holes are made in the first to third dielectric layers and solidly filled by electroplating to achieve electrical connection between different metal layers.

[0019] The solder resist layer is made of a photosensitive initiator and is used to prevent overflow short circuits between BGA balls in the subsequent BGA ball planting process.

[0020] The photosensitive dry film is used as a mask for SU-8 dry stripping. The thickness of SU-8 is 120 μm, so a dry film with a thickness of more than 240 μm is used as a mask to ensure that the SU-8 in the target area is completely removed while the surface of the non-target area is still protected by the dry film.

[0021] The dry stripping process is performed until the metal or silicon at the bottom of the target area can be seen. The groove formed after the SU-8 in the target area is removed is the chip slot.

[0022] After the silicon substrate is processed, each functional chip is embedded and mounted in the chip slot. The thickness of each chip should not exceed 200 μm to ensure that there is enough distance between the chip surface and the top antenna substrate.

[0023] The surface of the silicon substrate is connected to the LTCC antenna substrate through a BGA ball. During BGA welding, a certain distance should be kept between the surface of the embedded chip and the upper LTCC antenna substrate. At the same time, the highest point of the bonding wire should not touch the ground of the antenna substrate. Technical Effects The present invention manufactures four-layer wiring on the surface of a silicon substrate for layout wiring of a complex phased array system; while performing multi-layer wiring according to the characteristics of SU8 photoresist, the characteristic of SU8 photoresist that thick films can be manufactured is utilized to realize the manufacture of a dielectric layer of more than 40 μm, and a copper electroplating process is used to solidly fill dielectric through holes between the multi-layer wiring; and chip grooves are formed on the surface of the silicon substrate by dry stripping and etching of the multi-layer SU8 dielectric layer, and chips are embedded in the chip grooves. After the chip is mounted on the surface of the silicon substrate, the antenna substrate is stacked on the surface of the silicon adapter board by BGA welding. Compared with the prior art, the present invention realizes the complex interconnection between the functional chips in the phased array system, avoids the use of other high-cost processes such as silicon through-holes, and significantly increases the thickness of the dielectric layer, which meets the multi-layer RF interconnection process while reducing the loss of RF interconnection. The dielectric vias between the multi-layer wirings are solidly filled with the electroplating copper process, which enhances the through-hole current capacity and the heat dissipation capacity of the system. The multi-layer SU8 dielectric layer is etched by dry degumming to form chip slots on the surface of the silicon substrate, and the chips are embedded in these chip slots. While improving the heat dissipation capacity of the system, the distance between the chip surface and the top antenna substrate is increased, avoiding the antenna substrate from affecting the chip performance. The antenna substrate is stacked on the surface of the silicon adapter board by BGA welding, which improves the front-end RF performance and further realizes the miniaturization of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a side view of the present invention;

[0025] In the figure: 1 silicon substrate, 2 first metal layer, 3 first dielectric layer through hole, 4 first dielectric layer, 5 second metal layer, 6 second dielectric layer through hole, 7 second dielectric layer, 8 third metal layer, 9 third dielectric layer through hole, 10 third dielectric layer, 11 solder resist layer, 12 SU8 chip slot, 13 chip, 14 conductive silver paste, 15 bonding gold wire, 16 BGA solder ball, 17 antenna substrate, 18 fourth metal layer;

[0026] Figure 2 This is a layout diagram of the present invention;

[0027] In the figure: A silicon-based beamforming chip, B gallium arsenide-based single-pole double-throw chip, C gallium arsenide-based transceiver chip, D gallium arsenide-based single-pole four-throw chip;

[0028] Figure 3 It is a circuit diagram of the present invention;

[0029] Figure 4 It is a three-dimensional schematic diagram of the present invention;

[0030] Figure 5 It is a cross-sectional schematic diagram of the present invention;

[0031] Figure 6-Figure 10 It is a schematic diagram of the process flow of the present invention;

[0032] Fig.11 This is a real picture of silicon wafer processing in the embodiment;

[0033] Figure 12-13 This is a physical picture of the silicon wafer after ball implantation in the embodiment;

[0034] Fig.14 This is a physical picture of the silicon wafer after bonding in the embodiment;

[0035] Figure 15-16 This is a physical picture of the silicon wafer and the LTCC antenna substrate after being stacked in the embodiment;

[0036] Fig.17 is a scanning pattern simulation result of the embodiment in the first dimension;

[0037] Fig.18 is a simulation result of the scanning direction pattern of the embodiment in the second dimension;

[0038] Fig.19 The noise coefficient and conversion gain simulation results of the embodiment in the receiving mode are shown;

[0039] Fig. 20 The conversion gain and EIRP simulation results in the transmit mode are shown in FIG. DETAILED DESCRIPTION

[0040] like Figure 1As shown, a 64-channel phased array front-end structure involved in the present embodiment includes: a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a third metal layer, a third dielectric layer, a fourth metal layer and a solder resist layer sequentially arranged on a substrate, an SU8 chip slot for a built-in chip arranged on the substrate, and an antenna substrate at the top electrically connected to the third dielectric layer through a ball grid array (BGA), wherein: the chips are electrically connected to the fourth metal layer respectively, through holes are arranged on the first to third dielectric layers, the first metal layer, the first dielectric layer and the second metal layer constitute a first redistribution layer (RDL); the second dielectric layer and the third metal layer constitute a second redistribution layer; the third dielectric layer, the fourth metal layer and the solder resist layer constitute a third redistribution layer.

[0041] like Figure 2 and Figure 3 As shown, the built-in chip includes: 1 silicon-based beamforming chip A, 8 gallium arsenide-based single-pole double-throw chips B, 16 gallium arsenide-based transceiver chips C, 16 gallium arsenide-based single-pole four-throw chips D, 1 8×8 scale LTCC antenna array, 1 8×8 scale Luneburg lens array and several flat capacitors, wherein: the silicon-based beamforming chip A of the 64-channel phased array transceiver front end is connected to the 8 gallium arsenide-based single-pole double-throw chips B, and the silicon-based beamforming chip A inputs 1 local oscillator signal and 1 intermediate The 8-channel RF signal is input into the GaAs-based single-pole double-throw chip B, and the amplitude and phase of the 8-channel RF signal are controlled. Each of the 8 GaAs-based single-pole double-throw chips B inputs 1 channel of RF signal and selects and outputs 1 channel of RF signal; the 8-channel signals from the silicon-based beamforming chip A are input into the GaAs-based single-pole double-throw chip B for channel switching; the 8-channel RF signals after channel switching are input into the GaAs-based transceiver chip C for power amplification; the 8-channel RF signals after power amplification are input into the GaAs-based single-pole four-throw chip D to complete further channel switching. Amplitude and phase control of the RF signal can enable the phased array front end to perform beam scanning in a certain direction, and channel switching of the RF signal can enable the phased array front end to perform beam scanning in another direction, thereby realizing two-dimensional beam scanning. Power amplification of the RF signal can increase the equivalent omnidirectional radiation power of the phased array front end.

[0042] like Figure 2 As shown, the chip layout of this embodiment makes the RF interconnection length of each channel the same to ensure the consistency of the phase and amplitude of the RF signal of each channel. Each channel should be independent, and necessary shielding structures should be added to reduce signal crosstalk between channels. Taking into account the chip pin position, chip size, and system heat dissipation requirements, the chip layout is completed in the smallest possible area to achieve high-density integration.

[0043] like Figure 4-Figure 10 As shown, the preparation method of the 64-channel phased array transceiver front end in this embodiment specifically includes:

[0044] Step 1: Select a 4-inch silicon nitride wafer with a thickness of more than 1000 μm, and the thickness of the silicon nitride on the surface of the silicon substrate is more than 1 μm.

[0045] Step 2: Make the first metal layer, such as Figure 6 As shown in (a), it specifically includes: using magnetron sputtering technology to sputter 15nm of chromium and 150nm of copper on the surface of the silicon wafer as the electroplating seed layer, defining the grid pattern through the photolithography process, and then using the electroplating process to deposit a 3μm thick copper layer; then using acetone to remove the photoresist, and using isopropyl alcohol to clean the silicon wafer. Finally, the seed layer is etched using the ion beam etching method. Ion beam etching will cause certain damage to silicon nitride, so the ion beam etching time should not be too long. After the ion beam is completed, a DC needle test is performed to complete the production of the first metal layer.

[0046] Step 3: Make the first dielectric layer, such as Figure 6 As shown in (b), it specifically includes: taking SU8 out of the refrigerator and fully warming it up, and then placing the silicon substrate that has completed step 2 on a 65°C baking plate and baking it for 30 minutes to remove moisture. Before spin coating SU8, most of the bubbles are removed by a disposable dropper after glue dripping and before glue leveling, and after glue leveling, a dispensing needle is used to further remove residual bubbles, and then a two-stage pre-bake (65°C for 5 minutes, then 90°C for 10 minutes) is performed, and then exposure is performed to define the through holes in the dielectric layer. After exposure, a two-stage post-bake is performed (same as the pre-bake conditions). After development, a hard film treatment is performed, including low-temperature baking at 65°C for 1 hour to volatilize the solvent, and then high-temperature baking at 200°C for 1 hour to ensure that SU8 is completely cross-linked and cured.

[0047] Step 4: sputtering a seed layer, such as Figure 6 As shown in (c), 30nm of chromium and 300nm of copper are sputtered on the surface of the silicon wafer in sequence using magnetron sputtering technology.

[0048] Step 5: Fill the metal vias in the first dielectric layer, such as Figure 6 As shown in (d), it specifically includes: first making a layer of electroplating mask to define the position of the through hole, using a suitable photolithography process to ensure that the through hole position can be completely developed and cleaned, and then electroplating filling is performed. Before electroplating, wetting treatment should be performed in a vacuum environment to ensure that all through holes are evenly plated. After the electroplating is completed and the mask is removed with acetone, a measuring microscope can be used to perform Z-axis measurement to observe the filling effect of the metal hole.

[0049] Step 6: electroplating the second metal layer, such as Figure 6 As shown in (e), in the phased array front end of multi-layer RF interconnection, this metal layer is generally used for RF wiring, and can also be used for power supply or low-frequency wiring. First, a plating mask is made to define the pattern of the second metal layer, and a 3μm thick copper layer is deposited by electroplating process;

[0050] Step 7: Etch the second metal layer, such as Figure 6 As shown in (f), the electroplating mask is first removed by soaking in acetone solution, and then the seed layer is removed by ion beam etching. After the ion beam is completed, a DC needle test is performed to complete the production of the second metal layer.

[0051] Step 8: Make a second dielectric layer, such as Figure 7 As shown in (a), the second dielectric layer is manufactured on the second metal layer by the same operation as step 3.

[0052] Step 9: Make a seed layer, such as Figure 7 As shown in (b), a seed layer is prepared on the second dielectric layer by the same operation as step 4.

[0053] Step 10: Figure 7 As shown in (c), the same operation as step 5 is performed on the seed layer to fill the metal vias in the second dielectric layer.

[0054] Step 11, electroplating the third metal layer, such as Figure 7 As shown in (d), the third metal layer is manufactured on the silicon wafer with the metal through holes in the second dielectric layer filled by the same operation as step 6, that is, firstly a plating mask corresponding to the pattern of the third metal layer is manufactured, and then a 3 μm thick copper layer is deposited by the electroplating process.

[0055] The third metal layer is used for ground plane shielding, power supply or low-frequency wiring in the phased array front end of multi-layer radio frequency interconnection.

[0056] Step 12: Etch the third metal layer, such as Figure 7 As shown in (e), the second redistribution layer is manufactured on the silicon wafer after the third metal layer is electroplated by using the same operation as step 7.

[0057] Step 13: Make a third dielectric layer, such as Figure 8 As shown in (a), a third dielectric layer is manufactured on the third metal layer by the same operation as step 3.

[0058] Step 14: Make a seed layer, such as Figure 8 As shown in (b), a seed layer is prepared on the third dielectric layer by the same operation as step 4.

[0059] Step 15: Figure 8 As shown in (c), the same operation as step 5 is performed on the seed layer to fill the metal vias in the third dielectric layer.

[0060] Step 16: Make the fourth metal layer, such as Figure 8As shown in (d), a plating mask is made on the silicon wafer filled with the third dielectric layer, and then a 3 μm thick copper layer is deposited by electroplating. Then, the plating mask is removed by soaking in acetone solution, and then the seed layer is removed by ion beam etching;

[0061] The fourth metal layer is used for RF wiring, power supply or low-frequency wiring in the phased array front end of multi-layer RF interconnection.

[0062] Step 17, make a welding metal layer. The pattern of the welding metal layer is the same as that of the fourth metal layer, and it is made by a stripping process. First, make a stripping mask on the silicon wafer after making the fourth metal layer. The exposed metal part of the mask has the same pattern as that of the fourth metal layer. Use electron beam evaporation to deposit a 0.2μm thick nickel layer and a 0.5μm thick gold layer on the surface of the silicon wafer; after the deposition is completed, soak the silicon wafer in acetone for about one hour, wait for the photoresist mask to fall off, and then a welding metal layer is formed on the surface of the fourth metal layer.

[0063] Step 18: Make solder mask, such as Figure 8 As shown in (f), a 6 μm photosensitive initiator is spin-coated on the silicon wafer, and all ball implantation positions, wire bonding positions and chip mounting positions are opened by exposure and development to obtain a solder mask layer.

[0064] Step 19: Make an etching mask for the chip slot, such as Fig. 9 As shown in (b), the etching mask generally uses two layers of negative photosensitive dry film with a thickness of more than 120μm (total thickness 240μm). The negative photosensitive dry film has a strong bonding force with the silicon wafer substrate. In the subsequent process of removing the dry film with acetone, it is very likely that the dry film on the surface of the metal pad cannot be removed cleanly, affecting the subsequent wire bonding and ball planting process. Therefore, an optimized process is used. Before making the dry film, a layer of easily removable negative photoresist is first made on the surface of the silicon wafer, and then the dry film is made. When making the dry film, lamination, exposure, and development are performed in sequence to complete the production of the etching mask.

[0065] Step 20, etching the chip groove, such as Fig. 9 As shown in (c), the silicon substrate is bombarded with a microwave plasma stripper to complete the etching of the groove body. Etching in the SU8 photoresist allows the chip to be directly mounted on the surface of the silicon wafer to improve the heat dissipation effect and avoid the chip being affected by the antenna substrate above.

[0066] The etching uses oxygen and carbon tetrafluoride, and the etching rate depends on the gas flow rate and microwave power. After the etching is completed, it is preferred to use a DC probe to confirm whether the bottom of the groove is etched cleanly.

[0067] Step 21: Soak the silicon substrate in acetone solution. Fig. 9As shown in (d), the remaining photosensitive dry film mask is removed to complete the production of the silicon substrate.

[0068] Step 22: ball planting on silicon substrate, such as Fig.10 As shown above, the printing of solder paste and the placement of solder balls are completed by steel screen printing, and reflow soldering is performed.

[0069] Step 23: Bond the silicon substrate. Fig.10 As shown in the figure, all functional chips are mounted into the chip slots using conductive silver paste; wire bonding is completed and the wire arch height is controlled to be less than 100 μm.

[0070] Step 24: Printing conductive silver paste on the ceramic substrate, such as Fig.10 As shown below, the phased array front end is completed by aligning with the silicon adapter board and reflow soldering.

[0071] like Fig.11 As shown in FIG. 1 , a silicon wafer is prepared according to the above method. A solder ball with a diameter of 300 μm is further implanted on the silicon wafer to produce the following Fig.12 At the same time, on the silicon wafer after ball implantation, according to Figure 2 The chip layout drawing shown in the figure has been processed by chip mounting and wire bonding to produce Figure 13-14 The actual object shown in the figure. The front side of the LTCC antenna substrate is stacked on the surface of the silicon wafer using the reflow soldering technology to obtain the following Figure 15-16 The actual object shown has completed the processing of the main part of the phased array transceiver front end.

[0072] Furthermore, the performance of the phased array transceiver front end manufactured according to the above method was simulated. Fig.17 As shown in FIG, the phased array transceiver front end realizes 50 degrees of beam scanning in the first dimension. Fig.18 As shown in FIG. 1 , the phased array transceiver front end realizes 60 degrees of beam scanning in the second dimension. Fig.19 As shown in the figure, when the phased array transceiver front end works in the receiving mode, the noise figure is 3.6-4.2dB and the conversion gain is 54.4-64.6dB. Fig. 20 As shown, when the phased array transceiver front end works in the transmit mode, the conversion gain is 52.9-58.9dB and the EIRP is 46.6-48.9dB.

[0073] Compared with the prior art, the present invention realizes two-dimensional scanning of the beam without significantly increasing the number of channels, and then adds a Luneburg lens array. By utilizing the characteristics of the Luneburg lens, scanning is performed only in one direction by using amplitude and phase control, and beam scanning is achieved in the other direction by switching channels. In addition, the present invention utilizes the low loss and high precision characteristics of SU8 and applies it to the dielectric layer in the phased array transceiver front-end system. By using the method of solid filling of the dielectric layer through-holes, the overcurrent capacity of the dielectric through-holes is enhanced while also enhancing its heat dissipation capacity. In addition, the present invention etches a chip slot in the multi-layer dielectric and buries the chip in the slot, thereby achieving chip surface mounting on the surface of the silicon wafer, which enables the system to have good heat dissipation capacity. The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principle and purpose of the present invention. The protection scope of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. Each implementation scheme within its scope shall be subject to the constraints of the present invention.

Claims

1. A phased array front-end structure, characterized in that: include: A first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a third metal layer, a third dielectric layer, a fourth metal layer and a solder resist layer are sequentially arranged on a substrate, an SU8 chip slot with a built-in chip is arranged on the substrate, and an antenna substrate located on the top and electrically connected to the third dielectric layer through a ball grid array (BGA), wherein: the chip is electrically connected to the fourth metal layer respectively, through holes are arranged on the first to third dielectric layers, the first metal layer, the first dielectric layer and the second metal layer constitute a first redistribution layer (RDL); the second dielectric layer and the third metal layer constitute a second redistribution layer; the third dielectric layer, the fourth metal layer and the solder resist layer constitute a third redistribution layer; The first metal layer is used for ground plane shielding layer, the second metal layer is used for RF signal, control signal or power network wiring, the third metal layer is used for ground plane shielding layer, control signal or power network wiring, and the fourth metal layer is used for RF signal, control signal or power network wiring.

2. The phased array front end structure according to claim 1, characterized in that: The built-in chips include: a silicon-based beamforming chip, a gallium arsenide-based single-pole double-throw chip, a gallium arsenide-based transceiver chip, a gallium arsenide-based single-pole four-throw chip, an antenna array, and a Luneburg lens array, wherein: the silicon-based beamforming chip at the front end of the channel phased array transceiver is connected to the gallium arsenide-based single-pole double-throw chip, the silicon-based beamforming chip inputs a local oscillator signal and an intermediate frequency signal, outputs a radio frequency signal and realizes the amplitude and phase control of the radio frequency signal, and the gallium arsenide-based single-pole double-throw chip inputs a radio frequency signal and selects the output radio frequency signal; the signal from the silicon-based beamforming chip is input into the gallium arsenide single-pole double-throw chip. The GaAs-based single-pole double-throw chip is used for channel switching; the RF signal after channel switching is input into the GaAs transceiver chip for power amplification; the RF signal after power amplification is input into the GaAs-based single-pole four-throw chip to complete further channel switching; amplitude and phase control of the RF signal can enable the phased array front end to perform beam scanning in a certain direction, and channel switching of the RF signal can enable the phased array front end to perform beam scanning in another direction, thereby realizing two-dimensional beam scanning; power amplification of the RF signal can increase the equivalent omnidirectional radiation power of the phased array front end.

3. A method for preparing the phased array front-end structure according to claim 1 or 2, characterized in that: include: Step 1: first, on a silicon substrate as a substrate, a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a third metal layer, a third dielectric layer, a fourth metal layer and a solder resist layer for subsequent BGA ball planting are sequentially manufactured; Step 2: Use a photosensitive dry film exposure process to imprint the dry film on the surface of the silicon substrate, and expose the area where the chip is mounted after photolithography and development; Step 3: Use dry degumming to process the photosensitive dry film on the wafer surface of the silicon substrate and the exposed SU8 photoresist, so that the first metal layer is exposed, a chip slot is formed in the SU8, the silicon substrate is cleaned, and the residual photosensitive dry film is completely removed; Step 4: Use a steel mesh to plant BGA balls on the surface of the silicon substrate, and perform preliminary reflow soldering to fix the BGA; embed the chip into the SU8 slot and fix it with conductive silver paste; Step 5: Make electrical connection between the chip and the silicon substrate by wire bonding; use a steel mesh to print solder paste on the surface of the LTCC antenna substrate, and align and reflow solder it with the silicon substrate to complete the production of the phased array front end.

4. The preparation method according to claim 3, characterized in that: The first to fourth metal layers are all made by electroplating; the photosensitive dry film is used as a mask for SU-8 dry stripping. The thickness of SU-8 is 120μm, so a dry film with a thickness of more than 240μm is used as a mask to ensure that the SU-8 in the target area is removed cleanly while the surface of the non-target area is still protected by the dry film.

5. The preparation method according to claim 3, characterized in that: The dry stripping process is performed until the metal or silicon at the bottom of the target area can be seen. The groove formed after the SU-8 in the target area is removed is the chip slot.

6. The method according to any one of claims 3 to 5, characterized in that include: Step 1: Select a 4-inch silicon nitride wafer with a thickness of more than 1000 μm, and the thickness of the silicon nitride on the surface of the silicon substrate is more than 1 μm; Step 2, making the first metal layer, specifically including: using magnetron sputtering technology to sequentially sputter 15nm of chromium and 150nm of copper on the surface of the silicon wafer as an electroplating seed layer, defining a grid pattern through a photolithography process, and then using an electroplating process to deposit a 3μm thick copper layer; then using acetone to remove the photoresist, and using isopropanol to clean the silicon wafer, and finally using an ion beam etching method to etch the seed layer. Ion beam etching will cause certain damage to silicon nitride, so the ion beam etching time should not be too long. After the ion beam is completed, a DC needle test is performed to complete the production of the first metal layer; Step 3, making the first dielectric layer, specifically including: taking SU8 out of the refrigerator and fully warming it up, then placing the silicon substrate that has completed step 2 on a 65°C baking plate and baking it for 30 minutes to remove water vapor, before spin coating SU8, using a disposable dropper to remove most of the bubbles after glue dripping and before glue leveling, and using a dispensing needle after glue leveling to further remove residual bubbles, and then performing two-stage pre-baking (65°C for 5 minutes, then 90°C for 10 minutes), and then exposing to define the dielectric layer through-holes, after exposure, performing two-stage post-baking (same as pre-baking conditions), and after development, performing a hard film treatment, including low-temperature baking at 65°C for 1 hour to volatilize the solvent, and then high-temperature baking at 200°C for 1 hour to ensure that SU8 is completely cross-linked and cured; Step 4: sputtering a seed layer, using magnetron sputtering technology to sequentially sputter 30 nm of chromium and 300 nm of copper on the surface of the silicon wafer; Step 5, filling the metal through-holes in the first dielectric layer, specifically comprising: first making a layer of electroplating mask to define the position of the through-hole, using a suitable photolithography process to ensure that the position of the through-hole can be completely developed and cleaned, and then performing electroplating filling. Before electroplating, wetting treatment should be performed in a vacuum environment to ensure that all through-holes are evenly plated. After the electroplating is completed, the mask is removed with acetone, and a measuring microscope can be used to perform Z-axis measurement to observe the filling effect of the metal hole; Step 6: electroplating the second metal layer. In the phased array front end of multi-layer RF interconnection, this metal layer is generally used for RF wiring, and can also be used for power supply or low-frequency wiring. First, make a plating mask to define the pattern of the second metal layer, and use the electroplating process to deposit a 3μm thick copper layer; Step 7, etching the second metal layer, first use acetone solution to remove the electroplating mask, then use ion beam etching to remove the seed layer, and after the ion beam is completed, perform a DC needle test to complete the production of the second metal layer; Step 8: fabricating a second dielectric layer by performing the same operation as step 3 on the second metal layer; Step 9, preparing a seed layer, and preparing a seed layer on the second dielectric layer by the same operation as step 4; Step 10, filling the metal vias in the second dielectric layer on the seed layer using the same operation as step 5; Step 11, electroplating the third metal layer, the third metal layer is manufactured on the silicon wafer with the metal through holes in the second dielectric layer filled by the same operation as step 6, that is, firstly a plating mask corresponding to the pattern of the third metal layer is manufactured, and then a copper layer with a thickness of 3 μm is deposited by the electroplating process; Step 12, etching the third metal layer, and manufacturing a second redistribution layer on the silicon wafer after electroplating the third metal layer by the same operation as step 7; Step 13: fabricating a third dielectric layer by performing the same operation as step 3 on the third metal layer to obtain the third dielectric layer; Step 14: preparing a seed layer, and preparing a seed layer on the third dielectric layer by the same operation as step 4; Step 15, filling the metal vias in the third dielectric layer on the seed layer using the same operation as step 5; Step 16: fabricate a fourth metal layer, fabricate a plating mask on the silicon wafer filled with the third dielectric layer, deposit a 3 μm thick copper layer by electroplating, remove the plating mask by soaking in acetone solution, and then remove the seed layer by ion beam etching; Step 17, making a welding metal layer. The pattern of the welding metal layer is the same as that of the fourth metal layer. It is made by a stripping process. First, a stripping mask is made on the silicon wafer after the fourth metal layer is made. The pattern of the exposed metal part of the mask is the same as that of the fourth metal layer. A 0.2 μm thick nickel layer and a 0.5 μm thick gold layer are deposited on the surface of the silicon wafer by electron beam evaporation. After the deposition is completed, the silicon wafer is immersed in acetone for about one hour, and the photoresist mask is waited to fall off, so that the welding metal layer is formed on the surface of the fourth metal layer. Step 18, making a solder resist layer, spin coating a 6 μm photosensitive initiator on the silicon wafer, exposing and developing, opening windows at all ball implantation positions, wire bonding positions and chip mounting positions to obtain a solder resist layer; Step 19, making an etching mask for the chip slot. The etching mask generally uses two layers of negative photosensitive dry film with a thickness of more than 120 μm (total thickness of 240 μm). The negative photosensitive dry film has a strong bonding force with the silicon wafer substrate. In the subsequent process of removing the dry film with acetone, it is very likely that the dry film on the surface of the metal pad cannot be removed cleanly, affecting the subsequent wire bonding and ball planting process. Therefore, an optimized process is used. Before making the dry film, a layer of easily removable negative photoresist is first made on the surface of the silicon wafer, and then the dry film is made. When making the dry film, lamination, exposure, and development are performed in sequence to complete the making of the etching mask; Step 20, etching the chip groove, using a microwave plasma degumming machine to bombard the silicon substrate to complete the etching of the groove body, etching in SU8 photoresist so that the chip can be directly mounted on the surface of the silicon wafer to improve the heat dissipation effect and prevent the chip from being affected by the upper antenna substrate; Step 21, soaking the silicon substrate in acetone solution to remove the remaining photosensitive dry film mask, thereby completing the production of the silicon substrate; Step 22: ball planting on the silicon substrate, using steel screen printing to complete the printing of solder paste and placement of solder balls, and then performing reflow soldering; Step 23: Wire bonding of silicon substrate, using conductive silver paste to mount all functional chips into chip slots; completing wire bonding, controlling the wire arch height to be less than 100 μm; Step 24: Print conductive silver paste on the ceramic substrate, align it with the silicon adapter board, and perform reflow soldering to complete the production of the phased array front end.

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