Heterojunction solar cell and preparation method thereof

Abstract

The invention provides a heterojunction solar cell and a preparation method thereof. The heterojunction solar cell comprises a crystalline silicon substrate, wherein a front hydrogenated intrinsic amorphous silicon layer, a front doped amorphous silicon layer, a front transparent conductive layer and a front electrode are sequentially arranged on the front surface of the crystalline silicon substrate; a back hydrogenated intrinsic amorphous silicon layer, a back doped amorphous silicon layer, a back transparent conductive layer and a back electrode are sequentially arranged on the back of the crystalline silicon substrate, the front hydrogenated intrinsic amorphous silicon layer comprises a first buffer layer and a first passivation layer which are stacked, and the thickness of the first buffer layer is smaller than or equal to 2 nm; the back hydrogenated intrinsic amorphous silicon layer comprises a second buffer layer and a second passivation layer which are arranged in a stacked mode, and the thickness of the second buffer layer is smaller than or equal to 2 nm. Therefore, the buffer layer which is thinner and is made of the same material as the passivation layer is arranged between the crystalline silicon substrate and the passivation layer, so that the passivation effect of the hydrogenated intrinsic amorphous silicon layer can be effectively improved, and the overall efficiency of the direct solar cell is further improved.

Description

Technical Field

[0001] The present invention relates to the field of battery technology, and in particular to a direct solar cell and a preparation method thereof. Background Art

[0002] Silicon heterojunction solar cells (SHJ) are highly sought after and paid attention to by major photovoltaic companies due to their high efficiency and low cost. The quality of the amorphous silicon / crystalline silicon (a-Si:H / c-Si) interface of SHJ cells has a key impact on the electrical performance parameters of solar cells. It relies on the passivation layer composed of hydrogenated intrinsic amorphous silicon (ia-Si:H). By saturating the dangling bonds on the c-Si surface with H atoms, the recombination and interface state density of photogenerated carriers at the interface are reduced, which can effectively improve the open circuit voltage of the cell and make the theoretical efficiency of SHJ solar cells reach 28.7%. However, the passivation effect of the passivation layer in the current heterojunction solar cells is poor. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, one object of the present invention is to provide a heterojunction solar cell, in which the passivation layer has good passivation performance, which helps to improve the efficiency of the heterojunction solar cell.

[0004] In one aspect of the present invention, the present invention provides a heterojunction solar cell. According to an embodiment of the present invention, the heterojunction solar cell includes a crystalline silicon substrate, the front side of the crystalline silicon substrate is sequentially provided with a front hydrogenated intrinsic amorphous silicon layer, a front doped amorphous silicon layer, a front transparent conductive layer and a front electrode; the back side of the crystalline silicon substrate is sequentially provided with a back hydrogenated intrinsic amorphous silicon layer, a back doped amorphous silicon layer, a back transparent conductive layer and a back electrode, wherein the front hydrogenated intrinsic amorphous silicon layer includes a first buffer layer and a first passivation layer stacked, the first buffer layer is arranged between the first passivation layer and the crystalline silicon substrate, and the thickness of the first buffer layer is less than or equal to 2nm; and / or the back hydrogenated intrinsic amorphous silicon layer includes a second buffer layer and a second passivation layer stacked, the second buffer layer is arranged between the second passivation layer and the crystalline silicon substrate, and the thickness of the second buffer layer is less than or equal to 2nm. Therefore, by setting a thin buffer layer (including the first buffer layer and the second buffer layer) made of the same material as the passivation layer between the crystalline silicon substrate and the passivation layer (including the first passivation layer and the second passivation layer), the passivation effect of the hydrogenated intrinsic amorphous silicon layer can be effectively improved, thereby improving the overall efficiency of the direct solar cell.

[0005] According to an embodiment of the present invention, the thickness of the first passivation layer and the second passivation layer are respectively 3-10 nm.

[0006] According to an embodiment of the present invention, the front doped amorphous silicon layer includes a lightly doped amorphous silicon layer and a heavily doped amorphous silicon layer which are stacked, and the heavily doped amorphous silicon layer is arranged between the lightly doped amorphous silicon layer and the front transparent conductive layer.

[0007] According to an embodiment of the present invention, the heavily doped amorphous silicon layer satisfies at least one of the following conditions: the thickness of the heavily doped amorphous silicon layer is 2nm to 10nm; the conductivity of the heavily doped amorphous silicon layer is 0.2S / cm to 0.7S / cm; the carrier concentration of the heavily doped amorphous silicon layer is 1×10E19 / cm 3 ~2×10E20 / cm 3 The lightly doped amorphous silicon layer satisfies at least one of the following conditions: the thickness of the lightly doped amorphous silicon layer is 5 nm to 20 nm; the conductivity of the lightly doped amorphous silicon layer is 0.05 S / cm to 0.2 S / cm; the carrier concentration of the lightly doped amorphous silicon layer is 5×10E17 / cm 3 ~8×10E18 / cm 3 .

[0008] According to an embodiment of the present invention, the back-doped amorphous silicon layer satisfies at least one of the following conditions: the thickness of the back-doped amorphous silicon layer is 5nm to 25nm; the conductivity of the back-doped amorphous silicon layer is 0.2S / cm to 0.7S / cm; the carrier concentration of the back-doped amorphous silicon layer is 1×10E19 / cm 3 ~2×10E20 / cm 3 .

[0009] According to an embodiment of the present invention, the front transparent conductive layer includes a first transparent conductive layer and a second transparent conductive layer which are stacked, the first transparent conductive layer is arranged between the second transparent conductive layer and the front doped amorphous silicon layer, and the work function of the first transparent conductive layer is smaller than the work function of the second transparent conductive layer, and / or the back transparent conductive layer includes a third transparent conductive layer and a fourth transparent conductive layer which are stacked, the third transparent conductive layer is arranged between the fourth transparent conductive layer and the back doped amorphous silicon layer, and the work function of the third transparent conductive layer is smaller than the work function of the fourth transparent conductive layer.

[0010] According to an embodiment of the present invention, the work functions of the first transparent conductive layer and the third transparent conductive layer are 1.5 to 3.5 eV, respectively, and the work functions of the second transparent conductive layer and the fourth transparent conductive layer are 3.8 to 5.6 eV, respectively.

[0011] According to an embodiment of the present invention, the material of the first transparent conductive layer and the material of the third transparent conductive layer are MgF x O y 、TiN x O y andIn 2 O 3 :Sn, and the material of the second transparent conductive layer and the material of the fourth transparent conductive layer are respectively at least one of indium zinc oxide, indium zirconium oxide and indium tin oxide.

[0012] In another aspect of the present invention, the present invention provides a method for preparing the heterojunction solar cell described above. According to an embodiment of the present invention, the method for preparing a heterojunction solar cell includes: providing a crystalline silicon substrate; sequentially forming a front hydrogenated intrinsic amorphous silicon layer, a front doped amorphous silicon layer, a front transparent conductive layer and a front electrode on the front side of the crystalline silicon substrate; sequentially forming a back hydrogenated intrinsic amorphous silicon layer, a back doped amorphous silicon layer, a back transparent conductive layer and a back electrode on the back side of the crystalline silicon substrate, wherein the step of forming the front hydrogenated intrinsic amorphous silicon layer includes the step of sequentially depositing a first buffer layer and a first passivation layer, the thickness of the first buffer layer is less than or equal to 2nm; and / or, the step of forming the back hydrogenated intrinsic amorphous silicon layer includes the step of sequentially depositing a second buffer layer and a second passivation layer, the thickness of the second buffer layer is less than or equal to 2nm. Therefore, in the above preparation method, by forming a thin buffer layer (including the first buffer layer and the second buffer layer) made of the same material as the passivation layer between the crystalline silicon substrate and the passivation layer (including the first passivation layer and the second passivation layer), the passivation effect of the hydrogenated intrinsic amorphous silicon layer can be effectively improved, thereby improving the overall efficiency of the direct solar cell.

[0013] According to an embodiment of the present invention, the deposition power when depositing the first buffer layer is less than the deposition power when depositing the first passivation layer, wherein the deposition power of the first buffer layer is 5000W~16000W, and the deposition power of the first passivation layer is 8000W~20000W; and / or, the deposition power when depositing the second buffer layer is less than the deposition power when depositing the second passivation layer, wherein the deposition power of the second buffer layer is 5000W~16000W, and the deposition power of the second passivation layer is 8000W~20000W.

[0014] According to an embodiment of the present invention, the hydrogen dilution ratio R when depositing the first buffer layer is H The hydrogen dilution ratio R when depositing the first passivation layer is 5 to 20. H is 3 to 15, and / or, the hydrogen dilution ratio R when depositing the second buffer layer H The hydrogen dilution ratio R when depositing the second passivation layer is 5 to 20.H 3 to 15.

[0015] According to an embodiment of the present invention, the step of forming the front-side doped amorphous silicon layer includes the steps of sequentially depositing a lightly doped amorphous silicon layer and a heavily doped amorphous silicon layer.

[0016] According to an embodiment of the present invention, the step of forming the front transparent conductive layer includes sequentially depositing a first transparent conductive layer and a second transparent conductive layer, the work function of the first transparent conductive layer is smaller than the work function of the second transparent conductive layer, and / or the step of forming the back transparent conductive layer includes sequentially depositing a third transparent conductive layer and a fourth transparent conductive layer, the work function of the third transparent conductive layer is smaller than the work function of the fourth transparent conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 is a schematic structural diagram of a heterojunction solar cell in one embodiment of the present invention;

[0019] Figure 2 is a schematic structural diagram of a heterojunction solar cell in another embodiment of the present invention;

[0020] Figure 3 It is a schematic structural diagram of a heterojunction solar cell in another embodiment of the present invention.

[0021] Figure numerals: crystalline silicon substrate 10; front side 11; back side 12; front side hydrogenated intrinsic amorphous silicon layer 21; first buffer layer 211; first passivation layer 212; back side hydrogenated intrinsic amorphous silicon layer 22; second buffer layer 221; second passivation layer 222; front side doped amorphous silicon layer 31; lightly doped amorphous silicon layer 311; heavily doped amorphous silicon layer 312; back side doped amorphous silicon layer 32; front side transparent conductive layer 41; first transparent conductive layer 411; second transparent conductive layer 412; back side transparent conductive layer 24; third transparent conductive layer 423; fourth transparent conductive layer 424; front side electrode 51; back side electrode 52. DETAILED DESCRIPTION

[0022] The scheme of the present invention will be explained below in conjunction with the embodiments. It will be appreciated by those skilled in the art that the following embodiments are only used to illustrate the present invention and should not be considered as limiting the scope of the present invention. Where specific techniques or conditions are not indicated in the embodiments, the techniques or conditions described in the literature in this area or the product specifications are used. The reagents or instruments used are not indicated by the manufacturer and are all conventional products that can be obtained commercially.

[0023] The present invention is described below with reference to specific embodiments. It should be noted that these embodiments are merely illustrative and do not limit the present invention in any way.

[0024] In one aspect of the present invention, the present invention provides a heterojunction solar cell. Figure 1 The heterojunction solar cell comprises a crystalline silicon substrate 10, wherein a front hydrogenated intrinsic amorphous silicon layer 21, a front doped amorphous silicon layer 31, a front transparent conductive layer 41 and a front electrode 51 are sequentially arranged on a front side 11 of the crystalline silicon substrate 10; a back side hydrogenated intrinsic amorphous silicon layer 22, a back doped amorphous silicon layer 32, a back transparent conductive layer 24 and a back electrode 52 are sequentially arranged on a back side 12 of the crystalline silicon substrate 10, wherein the front hydrogenated intrinsic amorphous silicon layer 21 comprises a first buffer layer 211 and a first passivation layer 212 which are stacked, wherein the first buffer layer 211 is arranged between the first passivation layer 212 and the crystalline silicon substrate 10, and the thickness of the first buffer layer 211 is less than The thickness of the back hydrogenated intrinsic amorphous silicon layer 22 is less than or equal to 2nm (for example, 0.1nm, 0.3nm, 0.5nm, 0.8nm, 1.0nm, 1.2nm, 1.5nm, 1.8nm, 2.0nm, etc.); and / or, the back side hydrogenated intrinsic amorphous silicon layer 22 includes a second buffer layer 221 and a second passivation layer 222 which are stacked, the second buffer layer 221 is arranged between the second passivation layer 222 and the crystalline silicon substrate 10, and the thickness of the second buffer layer 221 is less than or equal to 2nm (for example, 0.1nm, 0.3nm, 0.5nm, 0.8nm, 1.0nm, 1.2nm, 1.5nm, 1.8nm, 2.0nm, etc.). Therefore, by setting a thin buffer layer (including the first buffer layer and the second buffer layer) made of the same material as the passivation layer between the crystalline silicon substrate and the passivation layer (including the first passivation layer and the second passivation layer), the passivation effect of the hydrogenated intrinsic amorphous silicon layer on the crystalline silicon substrate can be effectively improved, thereby improving the overall efficiency of the direct solar cell.

[0025] In heterojunction solar cells, the passivation layer of hydrogenated intrinsic amorphous silicon (ia-Si:H) significantly improves the minority carrier lifetime and open circuit voltage by reducing dangling bonds and surface defects, provides a field passivation effect, and reduces reflectivity, thereby improving the overall efficiency of the cell. Usually, the thickness of the passivation layer of hydrogenated intrinsic amorphous silicon is relatively thin. An excessively thick passivation layer will cause parasitic absorption, thereby reducing the short-circuit current density of the heterojunction solar cell. Therefore, the controllable window of the passivation layer is relatively narrow, which is difficult to control in actual production and preparation. In the present application, before forming the passivation layer, a buffer layer with a relatively thin thickness (less than or equal to 2nm) and the same material as the passivation layer is pre-arranged on the crystalline silicon substrate, which can not only effectively further improve the passivation effect of the hydrogenated intrinsic amorphous silicon layer, but also can widen the process window.

[0026] According to some embodiments of the present invention, when preparing the hydrogenated intrinsic amorphous silicon layer, the deposition power when depositing the first buffer layer is less than the deposition power when depositing the first passivation layer. According to other embodiments of the present invention, the deposition power when depositing the second buffer layer is less than the deposition power when depositing the second passivation layer. Thus, under the condition of low deposition power, the saturated silicon dangling bonds in the buffer layer can be more effectively made, thereby achieving a better passivation effect, and ultimately improving the overall passivation effect of the hydrogenated intrinsic amorphous silicon layer.

[0027] According to some embodiments of the present invention, when preparing the hydrogenated intrinsic amorphous silicon layer, the hydrogen dilution ratio R when depositing the first buffer layer is H The hydrogen dilution ratio R when depositing the first passivation layer is 5 to 20 (e.g., 5, 8, 10, 12, 15, 17, 20, etc.). H is 3 to 15 (for example, 3, 5, 8, 10, 12, 15). According to some other embodiments of the present invention, the hydrogen dilution ratio R when depositing the second buffer layer is H The hydrogen dilution ratio R when depositing the second passivation layer is 5 to 20 (e.g., 5, 8, 10, 12, 15, 17, 20, etc.). H 3 to 15 (for example, 3, 5, 8, 10, 12, 15). H By preparing the buffer layer and the passivation layer under the conditions of , the conductivity of the hydrogenated intrinsic amorphous silicon layer can be improved while ensuring a good surface passivation effect, thereby improving the efficiency of the solar cell.

[0028] In some embodiments of the present invention, the thickness of the first passivation layer and the second passivation layer are 3-10 nm, for example, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc. The passivation layer of the above thickness has a good passivation effect, does not cause parasitic absorption, and ensures a better short-circuit current density of the heterojunction solar cell.

[0029] According to an embodiment of the present invention, the crystalline silicon substrate may be an N-type crystalline silicon substrate.

[0030] According to some embodiments of the present invention, referring to Figure 2 The front doped amorphous silicon layer 31 includes a lightly doped amorphous silicon layer 311 and a heavily doped amorphous silicon layer 312 which are stacked, and the heavily doped amorphous silicon layer 312 is disposed between the lightly doped amorphous silicon layer 311 and the front transparent conductive layer 41. Thus, by disposing the heavily doped amorphous silicon layer 312, the doped amorphous silicon layer can have better conductivity, thereby effectively reducing the contact resistance between the front doped amorphous silicon layer 31 and the front transparent conductive layer (TCO) 41, thereby helping to improve the photoelectric conversion efficiency of the heterojunction solar cell and improve the battery performance.

[0031] According to some embodiments of the present invention, the thickness of the heavily doped amorphous silicon layer is 2 nm to 10 nm (for example, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc.); the conductivity of the heavily doped amorphous silicon layer is 0.2 S / cm to 0.7 S / cm (for example, 0.2 S / cm, 0.3 S / cm, 0.4 S / cm, 0.5 S / cm, 0.6 S / cm, 0.7 S / cm, etc.); the carrier concentration of the heavily doped amorphous silicon layer is 1×10E19 / cm 3 ~2×10E20 / cm 3 (For example, 1×10E19 / cm 3 , 5×10E19 / cm 3 , 8×10E19 / cm 3 , 1×10E20 / cm 3 、1.2×10E20 / cm 3 、1.5×10E20 / cm 3 、1.8×10E20 / cm 3 , 2×10E20 / cm 3 The heavily doped amorphous silicon layer under the above conditions helps to improve the conductivity of the front doped amorphous silicon layer, and effectively reduces the contact resistance between the front doped amorphous silicon layer 31 and the front transparent conductive layer (TCO) 41 .

[0032] According to some embodiments of the present invention, the lightly doped amorphous silicon layer satisfies at least one of the following conditions: the thickness of the lightly doped amorphous silicon layer is 5 nm to 20 nm (for example, 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 17 nm, 18 nm, 19 nm, 20 nm, etc.); the conductivity of the lightly doped amorphous silicon layer is 0.05 S / cm to 0.2 S / cm; the carrier concentration of the lightly doped amorphous silicon layer is 5×10E17 / cm 3 ~8×10E18 / cm 3 .

[0033] In some embodiments of the present invention, the front-doped amorphous silicon layer may be P-type doped, that is, both the lightly doped amorphous silicon layer 311 and the heavily doped amorphous silicon layer 312 are P-type doped, and the doping elements include but are not limited to elements such as boron (B) or aluminum (Al).

[0034] According to some embodiments of the present invention, the thickness of the back-doped amorphous silicon layer is 5 nm to 25 nm (for example, 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 17 nm, 20 nm, 23 nm, 25 nm); the conductivity of the back-doped amorphous silicon layer is 0.2 S / cm to 0.7 S / cm (for example, 0.2 S / cm, 0.3 S / cm, 0.4 S / cm, 0.5 S / cm, 0.6 S / cm, 0.7 S / cm, etc.); the carrier concentration of the back-doped amorphous silicon layer is 1×10E19 / cm 3 ~2×10E20 / cm 3 (For example, 1×10E19 / cm 3 , 5×10E19 / cm 3 , 8×10E19 / cm 3 , 1×10E20 / cm 3 、1.2×10E20 / cm 3 、1.5×10E20 / cm 3 、1.8×10E20 / cm 3 , 2×10E20 / cm 3 ).

[0035] In some embodiments of the present invention, the back-doped amorphous silicon layer may be N-type doped, and the doping elements include but are not limited to phosphorus (P) or arsenic (As).

[0036] According to some embodiments of the present invention, referring to Figure 3 The front transparent conductive layer 41 includes a first transparent conductive layer 411 and a second transparent conductive layer 412 stacked, the first transparent conductive layer 411 is arranged between the second transparent conductive layer and the front doped amorphous silicon layer 31, and the work function of the first transparent conductive layer 411 is less than the work function of the second transparent conductive layer 412. According to some other embodiments of the present invention, referring to Figure 3 The back transparent conductive layer 42 includes a third transparent conductive layer 423 and a fourth transparent conductive layer 424 which are stacked, the third transparent conductive layer 423 is arranged between the fourth transparent conductive layer 424 and the back doped amorphous silicon layer 32, and the work function of the third transparent conductive layer 423 is smaller than the work function of the fourth transparent conductive layer 424. Therefore, the arrangement of the low work function transparent conductive layer (including the first transparent conductive layer and the third transparent conductive layer) can form a good ohmic contact with the doped amorphous silicon layer (including the front doped amorphous silicon layer and the back doped amorphous silicon layer), so as to better reduce the contact resistance between the doped amorphous silicon layer and the transparent conductive layer, and improve the electrical performance of the solar cell.

[0037] According to some embodiments of the present invention, the work function of the first transparent conductive layer and the work function of the third transparent conductive layer are 1.5 to 3.5 eV, such as 1.5 eV, 1.8 eV, 2.0 eV, 2.3 eV, 2.5 eV, 2.8 eV, 3.0 eV, 3.2 eV, 3.5 eV, etc. The first transparent conductive layer and the third transparent conductive layer with low work function can well reduce the contact resistance between the high work function transparent conductive layer (including the second transparent conductive layer and the fourth transparent conductive layer) and the doped amorphous silicon layer. In some specific embodiments, the material of the first transparent conductive layer and the material of the third transparent conductive layer are MgF x O y (F-doped MgO), TiN x O y (Titanium Oxynitride) and In 2 O 3 : Sn (tin-doped indium oxide). The above conductive material not only has a lower work function, effectively realizing the effect of reducing the contact resistance between the transparent conductive layer and the doped amorphous silicon layer, but also has a higher light transmittance, ensuring a good photoelectric conversion efficiency of the solar cell. Among them, the first transparent conductive layer and the third transparent conductive layer can be selected from the same material or different materials, that is, the selection of materials by the two is independent of each other, so the work function of the first transparent conductive layer and the third transparent conductive layer can be the same or different.

[0038] According to some embodiments of the present invention, the work function of the second transparent conductive layer and the work function of the fourth transparent conductive layer are 3.8 to 5.6 eV, such as 3.8 eV, 4.0 eV, 4.2 eV, 4.4 eV, 4.6 eV, 4.8 eV, 5.0 eV, 5.2 eV, 5.4 eV, 5.6 eV, etc. The material of the second transparent conductive layer and the material of the fourth transparent conductive layer are at least one of indium zinc oxide, indium zirconium oxide and indium tin oxide. The second transparent conductive layer and the fourth transparent conductive layer can be selected from the same material or different materials, that is, the selection of materials by the two is independent of each other, so the work function of the second transparent conductive layer and the fourth transparent conductive layer can be the same or different.

[0039] In some embodiments of the present invention, the material of the front electrode and the back electrode may be low-temperature silver paste, so that the conductivity is good.

[0040] In another aspect of the present invention, the present invention provides a method for preparing the heterojunction solar cell described above. According to an embodiment of the present invention, the method for preparing a heterojunction solar cell includes: providing a crystalline silicon substrate 10; sequentially forming a front hydrogenated intrinsic amorphous silicon layer 21, a front doped amorphous silicon layer 31, a front transparent conductive layer 31 and a front electrode 51 on the front side 11 of the crystalline silicon substrate 10; sequentially forming a back hydrogenated intrinsic amorphous silicon layer 22, a back doped amorphous silicon layer 32, a back transparent conductive layer 42 and a back electrode 52 on the back side 12 of the crystalline silicon substrate 10. The structural schematic diagram can be referred to Figure 1 .

[0041] Reference Figure 1 In some embodiments of the present invention, the step of forming the front hydrogenated intrinsic amorphous silicon layer 21 includes the step of sequentially depositing a first buffer layer 211 and a first passivation layer 212, and the thickness of the first buffer layer 211 is less than or equal to 2nm; in other embodiments of the present invention, the step of forming the back hydrogenated intrinsic amorphous silicon layer 22 includes the step of sequentially depositing a second buffer layer 221 and a second passivation layer 222, and the thickness of the second buffer layer 221 is less than or equal to 2nm. Therefore, in the above preparation method, by forming a thin buffer layer (including the first buffer layer and the second buffer layer) made of the same material as the passivation layer between the crystalline silicon substrate and the passivation layer (including the first passivation layer and the second passivation layer), not only can the passivation effect of the hydrogenated intrinsic amorphous silicon layer be further effectively improved, but also the process window can be widened.

[0042] According to some embodiments of the present invention, when preparing the hydrogenated intrinsic amorphous silicon layer, the deposition power when depositing the first buffer layer is less than the deposition power when depositing the first passivation layer. According to other embodiments of the present invention, the deposition power when depositing the second buffer layer is less than the deposition power when depositing the second passivation layer. Thus, under the condition of low deposition power, the saturated silicon dangling bonds in the buffer layer can be more effectively made, thereby achieving a better passivation effect, and ultimately improving the overall passivation effect of the hydrogenated intrinsic amorphous silicon layer.

[0043] In some specific embodiments, the buffer layer and the passivation layer are formed by magnetron sputtering deposition, wherein the deposition power of the first buffer layer and the second buffer layer is 5000W to 16000W, such as 5000W, 6000W, 8000W, 10000W, 12000W, 14000W, 16000W, etc., and the deposition power of the first passivation layer and the second passivation layer is 8000W to 20000W, such as 8000W, 10000W, 12000W, 14000W, 16000W, 18000W, 20000W, etc. In this way, under the above power conditions, the buffer layer and the passivation layer can be well formed, and at the same time, the buffer layer formed by the lower deposition power has more saturated silicon dangling bonds, which helps to achieve a better passivation effect. The deposition powers of the first buffer layer and the second buffer layer are independent of each other, and they can be the same or different; the deposition powers of the first passivation layer and the second passivation layer are independent of each other, and they can be the same or different.

[0044] According to some embodiments of the present invention, when preparing the hydrogenated intrinsic amorphous silicon layer, the hydrogen dilution ratio R when depositing the first buffer layer is H The hydrogen dilution ratio R when depositing the first passivation layer is 5 to 20 (e.g., 5, 8, 10, 12, 15, 17, 20, etc.). H is 3 to 15 (for example, 3, 5, 8, 10, 12, 15). According to some other embodiments of the present invention, the hydrogen dilution ratio R when depositing the second buffer layer is H The hydrogen dilution ratio R when depositing the second passivation layer is 5 to 20 (e.g., 5, 8, 10, 12, 15, 17, 20, etc.). H 3 to 15 (for example, 3, 5, 8, 10, 12, 15). H By preparing the buffer layer and the passivation layer under the conditions of , the conductivity of the hydrogenated intrinsic amorphous silicon layer can be improved while ensuring a good surface passivation effect, thereby improving the efficiency of the solar cell.

[0045] In some embodiments of the present invention, before the hydrogenated intrinsic amorphous silicon layer is deposited on the front and back of the crystalline silicon substrate, a texturing treatment is performed on the front and back of the crystalline silicon substrate to form a textured light trapping structure. There are no special requirements for the specific method of the texturing treatment, and those skilled in the art can flexibly select it according to actual needs and existing technical means.

[0046] According to some embodiments of the present invention, the step of forming the front doped amorphous silicon layer 31 includes the steps of sequentially depositing a lightly doped amorphous silicon layer 311 and a heavily doped amorphous silicon layer 312, that is, the heavily doped amorphous silicon layer 312 is disposed between the lightly doped amorphous silicon layer 311 and the front transparent conductive layer 41. The structural schematic diagram can be seen in Figure 2Thus, by setting the heavily doped amorphous silicon layer 312, the doped amorphous silicon layer can have better conductivity, thereby effectively reducing the contact resistance between the front doped amorphous silicon layer 31 and the front transparent conductive layer (TCO) 41, thereby helping to improve the photoelectric conversion efficiency of the heterojunction solar cell and improve the battery performance.

[0047] In some embodiments of the present invention, the specific method of depositing the lightly doped amorphous silicon layer 311 and the heavily doped amorphous silicon layer 312 includes, but is not limited to, magnetron sputtering. There are no special requirements for the specific process conditions and parameters of the deposition, and those skilled in the art can flexibly select them according to actual needs and existing technical means, and no limitation is imposed here.

[0048] According to some embodiments of the present invention, the step of forming the front transparent conductive layer 41 includes sequentially depositing a first transparent conductive layer 411 and a second transparent conductive layer 412, and the work function of the first transparent conductive layer 411 is less than the work function of the second transparent conductive layer 412; according to some other embodiments of the present invention, the step of forming the back transparent conductive layer 42 includes sequentially depositing a third transparent conductive layer 423 and a fourth transparent conductive layer 424, and the work function of the third transparent conductive layer is less than the work function of the fourth transparent conductive layer. The structural schematic diagram can be referred to Figure 3 Thus, a low work function transparent conductive layer (including the first transparent conductive layer and the third transparent conductive layer) is first formed on the surface of the transparent conductive layer close to the doped amorphous silicon layer, and the low work function transparent conductive layer can form a good ohmic contact with the doped amorphous silicon layer (including the front doped amorphous silicon layer and the back doped amorphous silicon layer), thereby effectively reducing the contact resistance between the doped amorphous silicon layer and the transparent conductive layer, and improving the electrical performance of the solar cell.

[0049] In some embodiments, the method of depositing the first transparent conductive layer 411, the second transparent conductive layer 412, the third transparent conductive layer 423 and the fourth transparent conductive layer 424 includes but is not limited to magnetron sputtering. There are no special requirements for the specific process conditions and parameters of the deposition, and those skilled in the art can flexibly select them according to actual needs and existing technical means, and no limitation is imposed here.

[0050] Those skilled in the art will appreciate that, after forming the front electrode and the back electrode, the method for preparing a heterojunction solar cell further includes sintering, laser-assisted sintering, photoelectric injection and other processing steps to obtain a high-performance heterojunction solar cell.

[0051] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0052] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0053] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A heterojunction solar cell, characterized in that: The invention comprises a crystalline silicon substrate, wherein a front hydrogenated intrinsic amorphous silicon layer, a front doped amorphous silicon layer, a front transparent conductive layer and a front electrode are sequentially arranged on the front side of the crystalline silicon substrate; and a back side hydrogenated intrinsic amorphous silicon layer, a back doped amorphous silicon layer, a back transparent conductive layer and a back electrode are sequentially arranged on the back side of the crystalline silicon substrate. The front hydrogenated intrinsic amorphous silicon layer includes a first buffer layer and a first passivation layer which are stacked, the first buffer layer is arranged between the first passivation layer and the crystalline silicon substrate, and the thickness of the first buffer layer is less than or equal to 2 nm; And / or, the back hydrogenated intrinsic amorphous silicon layer includes a second buffer layer and a second passivation layer which are stacked, the second buffer layer is arranged between the second passivation layer and the crystalline silicon substrate, and the thickness of the second buffer layer is less than or equal to 2 nm.

2. The heterojunction solar cell according to claim 1, characterized in that: The thickness of the first passivation layer and the second passivation layer are respectively 3-10 nm.

3. The heterojunction solar cell according to claim 1 or 2, characterized in that: The front doped amorphous silicon layer comprises a lightly doped amorphous silicon layer and a heavily doped amorphous silicon layer which are stacked, and the heavily doped amorphous silicon layer is arranged between the lightly doped amorphous silicon layer and the front transparent conductive layer.

4. The heterojunction solar cell according to claim 3, characterized in that: The heavily doped amorphous silicon layer satisfies at least one of the following conditions: The heavily doped amorphous silicon layer has a thickness of 2 nm to 10 nm; The conductivity of the heavily doped amorphous silicon layer is 0.2S / cm to 0.7S / cm; The carrier concentration of the heavily doped amorphous silicon layer is 1×10E19 / cm 3 ~2×10E20 / cm 3 , The lightly doped amorphous silicon layer satisfies at least one of the following conditions: The thickness of the lightly doped amorphous silicon layer is 5nm to 20nm; The conductivity of the lightly doped amorphous silicon layer is 0.05S / cm to 0.2S / cm; The carrier concentration of the lightly doped amorphous silicon layer is 5×10E17 / cm 3 ~8×10E18 / cm 3 .

5. The heterojunction solar cell according to claim 3, characterized in that: The back-doped amorphous silicon layer satisfies at least one of the following conditions: The thickness of the back-doped amorphous silicon layer is 5nm to 25nm; The conductivity of the back-doped amorphous silicon layer is 0.2S / cm to 0.7S / cm; The carrier concentration of the back-doped amorphous silicon layer is 1×10E19 / cm 3 ~2×10E20 / cm 3 .

6. The heterojunction solar cell according to claim 1 or 2, characterized in that: The front transparent conductive layer includes a first transparent conductive layer and a second transparent conductive layer stacked in layers, the first transparent conductive layer is arranged between the second transparent conductive layer and the front doped amorphous silicon layer, and the work function of the first transparent conductive layer is smaller than the work function of the second transparent conductive layer, And / or, the back transparent conductive layer includes a third transparent conductive layer and a fourth transparent conductive layer which are stacked, the third transparent conductive layer is arranged between the fourth transparent conductive layer and the back doped amorphous silicon layer, and the work function of the third transparent conductive layer is smaller than the work function of the fourth transparent conductive layer.

7. The heterojunction solar cell according to claim 6, characterized in that: The work functions of the first transparent conductive layer and the third transparent conductive layer are 1.5 to 3.5 eV, respectively. The work functions of the second transparent conductive layer and the fourth transparent conductive layer are 3.8 to 5.6 eV, respectively.

8. The heterojunction solar cell according to claim 7, characterized in that: The materials of the first transparent conductive layer and the third transparent conductive layer are MgF x O y 、TiN x O y and at least one of In2O3:Sn, The material of the second transparent conductive layer and the material of the fourth transparent conductive layer are respectively at least one of indium zinc oxide, indium zirconium oxide and indium tin oxide.

9. A method for preparing a heterojunction solar cell according to any one of claims 1 to 8, characterized in that: include: Providing a crystalline silicon substrate; On the front side of the crystalline silicon substrate, a front hydrogenated intrinsic amorphous silicon layer, a front doped amorphous silicon layer, a front transparent conductive layer and a front electrode are sequentially formed; A back hydrogenated intrinsic amorphous silicon layer, a back doped amorphous silicon layer, a back transparent conductive layer and a back electrode are sequentially formed on the back side of the crystalline silicon substrate. The step of forming the front hydrogenated intrinsic amorphous silicon layer comprises the steps of sequentially depositing a first buffer layer and a first passivation layer, wherein the thickness of the first buffer layer is less than or equal to 2 nm; And / or, the step of forming the back hydrogenated intrinsic amorphous silicon layer includes the steps of sequentially depositing a second buffer layer and a second passivation layer, and the thickness of the second buffer layer is less than or equal to 2 nm.

10. The method according to claim 9, characterized in that The deposition power when depositing the first buffer layer is less than the deposition power when depositing the first passivation layer, wherein the deposition power of the first buffer layer is 5000W to 16000W, and the deposition power of the first passivation layer is 8000W to 20000W; And / or, the deposition power when depositing the second buffer layer is less than the deposition power when depositing the second passivation layer, wherein the deposition power of the second buffer layer is 5000W to 16000W, and the deposition power of the second passivation layer is 8000W to 20000W.

11. The method according to claim 9, characterized in that The hydrogen dilution ratio R when depositing the first buffer layer H The hydrogen dilution ratio R when depositing the first passivation layer is 5 to 20. H is 3 to 15, and / or, the hydrogen dilution ratio R when depositing the second buffer layer H The hydrogen dilution ratio R when depositing the second passivation layer is 5 to 20. H 3 to 15.

12. The method according to any one of claims 9 to 11, characterized in that: The step of forming the front-side doped amorphous silicon layer includes the steps of sequentially depositing a lightly doped amorphous silicon layer and a heavily doped amorphous silicon layer.

13. The method according to any one of claims 9 to 11, characterized in that: The step of forming the front transparent conductive layer comprises depositing a first transparent conductive layer and a second transparent conductive layer in sequence, wherein the work function of the first transparent conductive layer is smaller than the work function of the second transparent conductive layer, And / or, the step of forming the back transparent conductive layer includes sequentially depositing a third transparent conductive layer and a fourth transparent conductive layer, and a work function of the third transparent conductive layer is smaller than a work function of the fourth transparent conductive layer.

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