TBC battery and preparation method thereof

Abstract

The invention discloses a TBC battery and a preparation method thereof. The preparation method of the TBC battery comprises the following steps: preparing a process sheet of the TBC battery; the process wafer comprises an N-type silicon-based substrate, and the N-type silicon-based substrate comprises a first surface and a second surface which are opposite to each other; the second surface side is provided with a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer which are stacked in sequence; the tunneling oxide layer and the phosphorus-doped polycrystalline silicon layer comprise interdigital openings, and P-type doped layers are arranged in the openings; forming an anti-ultraviolet layer on the first surface side; the anti-ultraviolet layer is used for blocking ultraviolet rays; and forming passivation layers on the first surface side and the second surface side, and forming a first metal gate line in contact with the P-type doped layer and a second metal gate line in contact with the phosphorus-doped polycrystalline silicon layer on the surface of one side, deviating from the N-type silicon substrate, of each passivation layer, so as to prepare the TBC battery. According to the technical scheme provided by the invention, external ultraviolet rays can be prevented from entering the TBC battery, the structural stability and the working reliability of the TBC battery are improved, and the service life of the TBC battery is prolonged.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and in particular to a TBC cell and a preparation method thereof. Background Art

[0002] The tunnel oxide passivated contact technology (Tunnel Oxide Passivated Contact, TOPCon) is applied to the back contact solar cell (Interdigitated Back Contact, IBC) to obtain the cross passivated back contact (TOPCon Interdigitated Back Contact, TBC) solar cell. The TBC cell combines the high short-circuit current of the IBC cell and the passivation contact characteristics of the TOPCon technology, so that the TBC has a good passivation structure, which can improve the cell efficiency.

[0003] When ultraviolet rays irradiate the surface of TBC batteries, some bands of ultraviolet rays will enter the battery from the front, thereby destroying the passivation layer structure in the battery, affecting the working stability and service life of the TBC battery. How to improve the anti-ultraviolet ability of TBC batteries to improve the working stability of TBC batteries has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a TBC battery and a preparation method thereof, which can block external ultraviolet rays from entering the interior of the TBC battery, improve the structural stability and working reliability of the TBC battery, and extend the service life of the TBC battery.

[0005] In a first aspect, the present invention provides a method for preparing a TBC battery, characterized by comprising:

[0006] A process wafer for preparing the TBC battery; the process wafer comprises an N-type silicon-based substrate, the N-type silicon-based substrate comprises a first surface and a second surface opposite to each other; a tunneling oxide layer and a phosphorus-doped polysilicon layer stacked in sequence are arranged on the second surface side; the tunneling oxide layer and the phosphorus-doped polysilicon layer comprise openings in a forked shape, and the openings comprise a P-type doped layer;

[0007] An anti-ultraviolet layer is formed on the first surface side; the anti-ultraviolet layer is used to block ultraviolet rays;

[0008] A passivation layer is formed on the first surface side and the second surface side, and a first metal gate line in contact with the P-type doped layer and a second metal gate line in contact with the phosphorus-doped polysilicon layer are formed on a surface of the passivation layer facing away from the N-type silicon substrate to produce the TBC battery.

[0009] Optionally, the anti-ultraviolet layer includes aluminum oxide, and the thickness of the anti-ultraviolet layer is 6 nm to 10 nm.

[0010] Optionally, forming an anti-ultraviolet layer on the first surface side includes:

[0011] Put the process sheet of the TBC battery into a reaction chamber; the temperature of the reaction chamber is 270°C to 290°C;

[0012] Trimethylaluminum with a flow rate of 15 sccm to 20 sccm and oxygen with a flow rate of 10 sccm to 15 sccm are introduced into the reaction chamber; the cycle range is 55s to 65s, and the cycle is performed for 26 to 45 cycles.

[0013] Optionally, the process of preparing the TBC battery comprises:

[0014] Providing the N-type silicon-based substrate;

[0015] Forming the tunnel oxide layer and the polysilicon layer stacked in sequence on the second surface side of the N-type silicon-based substrate;

[0016] Doping the polysilicon layer with phosphorus to form the phosphorus-doped polysilicon layer;

[0017] The tunnel oxide layer and the phosphorus-doped polysilicon layer are etched to form the opening to expose a portion of the N-type silicon-based substrate on the second surface side; the opening is in an interdigitated shape;

[0018] The N-type silicon-based substrate in the opening is doped with boron to form the P-type doped layer.

[0019] Optionally, before boron doping is performed on the N-type silicon-based substrate in the opening, the method further includes:

[0020] performing chain pickling on the first surface side of the process sheet;

[0021] Performing a texturing treatment on the first surface side and the second surface side of the process sheet to form a velvet surface on the first surface side;

[0022] The first surface of the process sheet is subjected to a first oxidation treatment.

[0023] Optionally, after boron doping is performed on the N-type silicon-based substrate in the opening to form the P-type doped layer, the method further includes:

[0024] performing a second oxidation treatment on the second surface side;

[0025] performing chain pickling and alkali polishing on the first surface side and the second surface side;

[0026] The temperature of the second oxidation treatment is 750° C. to 1000° C., the oxygen flow rate is 2000 sccm to 2500 sccm, and the time is 25 minutes to 35 minutes.

[0027] Optionally, before etching the tunnel oxide layer and the phosphorus-doped polysilicon layer to form the opening, the method further includes:

[0028] A protective layer is prepared on the surface of the phosphorus-doped polysilicon layer on one side away from the N-type silicon-based substrate; the protective layer is used to protect the phosphorus-doped polysilicon layer and the tunneling oxide layer.

[0029] Optionally, a protective layer is formed on a surface of the phosphorus-doped polysilicon layer on a side away from the N-type silicon-based substrate, comprising:

[0030] Forming a silicon nitride layer on a surface of the phosphorus-doped polysilicon layer that is away from the N-type silicon-based substrate;

[0031] A silicon oxide layer is prepared on the surface of the silicon nitride layer on the side away from the N-type silicon-based substrate; and the protective layer includes the silicon nitride layer and the silicon oxide layer.

[0032] Optionally, after boron doping is performed on the N-type silicon-based substrate in the opening to form the P-type doped layer, the method further includes:

[0033] Performing acid washing and alkali polishing on the second surface side to remove the silicon oxide layer;

[0034] The first surface side and the second surface side are chain pickled to remove the silicon nitride layer.

[0035] In a second aspect, the present invention provides a TBC battery, which is prepared using the TBC battery preparation method described in the first aspect.

[0036] The technical solution provided by the present invention is to prepare an anti-ultraviolet layer on the first surface side of the process sheet of the TBC battery, that is, to prepare an anti-ultraviolet layer on the surface of the side of the process sheet of the TBC battery that receives light, so as to block the ultraviolet rays irradiated to the surface of the TBC battery, prevent the ultraviolet rays from entering the interior of the TBC battery and damaging the internal film layer of the TBC battery, so as to improve the working reliability and stability of the TBC battery. A passivation layer is provided on the surface of the anti-ultraviolet layer away from the N-type silicon-based substrate to protect the anti-ultraviolet layer, prevent pollutants in the external air from corroding the anti-ultraviolet layer or entering the interior of the TBC battery through the anti-ultraviolet layer, and improve the structural stability of the TBC battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A flow chart of a method for preparing a TBC battery provided by an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of the structure of a process for preparing a TBC battery provided by an embodiment of the present invention;

[0039] Figure 3 A top view of a process sheet of a TBC battery provided by an embodiment of the present invention;

[0040] Figure 4 A flow chart of a method for preparing a process sheet of a TBC battery provided by an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of the process structure of a process sheet for preparing a TBC battery provided by an embodiment of the present invention;

[0042] Figure 6 A flow chart of a method for preparing another process sheet of a TBC battery provided by an embodiment of the present invention;

[0043] Figure 7 A schematic diagram of the process structure of another process sheet for preparing a TBC battery provided by an embodiment of the present invention;

[0044] Figure 8 A schematic diagram of the process structure of another process sheet for preparing a TBC battery provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0046] An embodiment of the present invention provides a method for preparing a TBC battery, and the preparation method is suitable for preparing the TBC battery provided by the embodiment of the present invention. Figure 1 A flowchart of a method for preparing a TBC battery provided by an embodiment of the present invention, Figure 2 A schematic diagram of a process structure of preparing a TBC battery provided in an embodiment of the present invention, wherein the method for preparing the TBC battery comprises:

[0047] S101, preparing a process sheet of a TBC battery.

[0048] Among them, the process wafer includes an N-type silicon-based substrate 10, and the N-type silicon-based substrate 10 includes a first surface 11 and a second surface 12 relative to each other; a tunneling oxide layer 21 and a phosphorus-doped polysilicon layer 22 stacked in sequence are arranged on the second surface side; the tunneling oxide layer 21 and the phosphorus-doped polysilicon layer 22 include a forked-finger-shaped opening OP, and the opening OP includes a P-type doped layer 31.

[0049] Figure 3 A top view of a process sheet of a TBC battery provided by an embodiment of the present invention, such as Figure 3 As shown, the P-type doped layer 31 is located in the opening, and the shape of the opening is a forked finger shape, so the shape of the P-type doped layer 31 is also a forked finger shape. The area where the P-type doped layer 31 is located forms the P-type doped area Q2 of the TBC battery, and the forked finger-shaped area where the phosphorus-doped polysilicon layer 22 is located forms the N-type doped area Q1 of the TBC battery.

[0050] Specifically, the N-type silicon-based substrate 10 can be a wafer or silicon slice doped with pentavalent elements, such as phosphorus (P) or arsenic (As). Semiconductor silicon (Si) is a tetravalent element. After forming electron-hole pairs with the pentavalent elements, a large number of electrons will be generated in the wafer or silicon slice, thereby forming the N-type silicon-based substrate 10.

[0051] refer to Figure 2 The tunnel oxide layer 21 and the phosphorus-doped polysilicon layer 22 on the second surface side can be formed by low-pressure chemical vapor deposition. After the tunnel oxide layer 21 and the phosphorus-doped polysilicon layer 22 are formed, a mask with a forked pattern is placed on the side of the phosphorus-doped polysilicon layer 22 away from the N-type silicon-based substrate 10. The mask is used to protect the phosphorus-doped polysilicon layer 22 and the tunnel oxide layer 21. The tunnel oxide layer 21 and the phosphorus-doped polysilicon layer 22 are etched by laser etching and other processes to form a forked opening OP. After that, the process wafer with the opening OP is placed in a low-pressure diffusion furnace, and a boron source is deposited on the second surface side to form a P-type doped layer 31 in the opening OP. The mask is removed to form a process wafer of a TBC battery.

[0052] It is understandable that the above only illustrates a preparation process of the process sheet of the TBC battery. The preparation process of the process sheet of the TBC battery can also be other, which can be set according to actual needs and is not specifically limited here. The material and thickness of the above-mentioned tunneling oxide layer 21 and the phosphorus-doped polysilicon layer 22 can be set according to actual needs and are not specifically limited here. For example, the material of the tunneling oxide layer 21 may include but is not limited to one or more of silicon oxide, aluminum oxide, titanium oxide, chromium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride and titanium carbonitride; the thickness of the tunneling oxide layer 21 can be 1mm~2mm, the thickness of the phosphorus-doped polysilicon layer 22 can be 100nm-150nm, and the depth of the opening OP can be 1μm~1.5μm.

[0053] It should be noted that the first surface 11 of the N-type silicon-based substrate 10 can be a velvet surface or a plane, and can be set according to actual needs. In the embodiments of the present invention, the first surface 11 of the N-type silicon-based substrate 10 is taken as an example to illustrate that the velvet surface can increase the light receiving area of ​​the TBC battery, thereby improving the photoelectric conversion efficiency of the TBC battery.

[0054] S102, forming an anti-ultraviolet layer on the first surface side.

[0055] Among them, reference Figure 2 The anti-ultraviolet layer 13 is used to block ultraviolet rays. On the premise that the material of the anti-ultraviolet layer 13 includes materials such as zinc oxide or aluminum oxide that can block ultraviolet rays, the material of the anti-ultraviolet layer 13 can be set according to actual needs.

[0056] Specifically, an atomic layer deposition (ALD) process can be used to prepare the anti-ultraviolet layer 13 on the first surface side. Under the premise of ensuring that the anti-ultraviolet layer 13 blocks ultraviolet rays and does not affect visible light and the like from passing through the anti-ultraviolet layer 13 into the N-type silicon-based substrate 10, the thickness of the anti-ultraviolet layer 13 can be set according to actual needs, and no specific limitation is made here.

[0057] S103, forming a passivation layer on the first surface side and the second surface side, and forming a first metal gate line in contact with the P-type doped layer and a second metal gate line in contact with the phosphorus-doped polysilicon layer on the surface of the passivation layer facing away from the N-type silicon substrate to produce a TBC battery.

[0058] Among them, reference Figure 2 The passivation layer 14 includes materials such as silicon nitride, silicon carbide or phosphorus oxide, and can be set according to actual needs.

[0059] Specifically, the passivation layer 14 covers the first surface side and the second surface side respectively, which can prevent pollutants in the air from corroding the inside of the TBC battery, protect the TBC battery, and improve the photoelectric conversion efficiency of the TBC battery. After the passivation layer 14 is prepared, the aluminum-free silver paste is printed in the opening on the second surface side by a screen printing process to form a first metal gate line L1 in contact with the P-type doped layer. The silver paste is printed in the area of ​​the second surface side except the opening by a screen printing process to form a second metal gate line L2 in contact with the phosphorus-doped polysilicon layer 22.

[0060] It should be noted that the first gate line L1 is usually prepared by printing aluminum silver paste, but the aluminum element will form aluminum spikes when the process sheet performs the cooling process, and the aluminum spikes will destroy the internal PN junction and form a metal composite area, resulting in a decrease in the open circuit voltage of the TBC battery and affecting the conversion efficiency of the TBC. By printing aluminum-free silver paste to form the first metal gate line L1, the problem of low conversion efficiency caused by the use of aluminum silver paste can be avoided, and the photoelectric conversion efficiency and working reliability of the TBC battery can be improved.

[0061] In an optional embodiment, the passivation layer 14 includes silicon nitride, and the process conditions for preparing the passivation layer 14 are as follows: the process wafer is placed in a reaction chamber, the temperature in the reaction chamber is 525°C, the pressure is 1700N, the flow rate of nitrogen is 9000sccm, the flow rate of silane is 1300sccm, and the reaction time is 60s.

[0062] The technical solution of the embodiment of the present invention is to prepare an anti-ultraviolet layer on the first surface side of the process sheet of the TBC battery, that is, to prepare an anti-ultraviolet layer on the surface of the side of the process sheet of the TBC battery that receives light, so as to block the ultraviolet rays irradiated to the surface of the TBC battery, prevent the ultraviolet rays from entering the interior of the TBC battery and damaging the internal film layer of the TBC battery, so as to improve the working reliability and stability of the TBC battery. A passivation layer is provided on the surface of the anti-ultraviolet layer away from the N-type silicon-based substrate to protect the anti-ultraviolet layer, prevent pollutants in the external air from corroding the anti-ultraviolet layer or entering the interior of the TBC battery through the anti-ultraviolet layer, and improve the structural stability of the TBC battery.

[0063] In an optional embodiment, the anti-ultraviolet layer 13 includes aluminum oxide, and the thickness of the anti-ultraviolet layer 13 is 6 nm to 10 nm.

[0064] Specifically, when the thickness of the anti-ultraviolet layer 13 is less than 6nm, it means that the thickness of the aluminum oxide is relatively thin. Due to the limitation of the preparation process, there are some areas of the prepared anti-ultraviolet layer 13 where aluminum oxide is not prepared or the density of aluminum oxide is relatively low, so that the efficiency of blocking ultraviolet rays in this area is relatively low, and a good ultraviolet blocking effect cannot be achieved. When the thickness of the anti-ultraviolet layer 13 is greater than 10nm, it means that the thickness of aluminum oxide is relatively thick, and the density of the anti-ultraviolet layer 13 is relatively good, but thicker aluminum oxide can not only block ultraviolet rays, but also reduce the transmittance of visible light and other light, resulting in a decrease in the light absorption rate of the TBC battery, which reduces the power generation of the TBC battery. Therefore, by setting the thickness of the anti-ultraviolet layer 13 to 6nm to 10nm, that is, the thickness range of aluminum oxide is 6nm to 10nm, so as to ensure the density and uniformity of the entire layer of aluminum oxide and the light absorption of the TBC battery, improve the reliability of the aluminum oxide film layer in blocking ultraviolet rays, prevent ultraviolet rays from entering the interior of the TBC battery and affecting part of the film layer, so as to improve the working stability of the TBC battery and extend the service life of the TBC battery.

[0065] In an optional embodiment, forming the anti-ultraviolet layer on the first surface side includes placing a process sheet of a TBC battery into a reaction chamber; the temperature of the reaction chamber is 270° C. to 290° C., introducing trimethylaluminum with a flow rate of 15 sccm to 20 sccm and oxygen with a flow rate of 10 sccm to 15 sccm into the reaction chamber; the cycle range is 55 s to 65 s, and the cycle is performed for 26 to 45 cycles.

[0066] Specifically, under the premise that the reaction chamber temperature is 270° C. to 290° C., trimethylaluminum (TMA) with a flow rate of 15 sccm to 20 sccm and oxygen (O 2 ) reaction, the reaction time can be selected within 55s to 65s, so that trimethylaluminum and oxygen generate a thinner aluminum oxide film under the temperature condition and the reaction time. The above process is repeated 26 to 45 times to form an aluminum oxide film with a thickness of 6nm to 10nm and good compactness. When the temperature of the reaction chamber is 270℃ to 290℃, trimethylaluminum with a flow rate of 15sccm to 20sccm and oxygen with a flow rate of 10sccm to 15sccm are introduced into the reaction chamber; the cycle range is 55s to 65s, and after 26 to 45 cycles, appropriate reaction conditions can be set according to actual needs to form an aluminum oxide film with good compactness and a thickness of 6nm to 10nm. Exemplarily, the reaction chamber temperature is 280° C., the reaction cycle (reaction time) is 58 s, trimethylaluminum with a flow rate of 18 sccm and oxygen with a flow rate of 12 sccm are introduced into the reaction chamber, the cycle is performed for 35 cycles, and the thickness of the formed aluminum oxide film layer is 8 nm.

[0067] In an optional embodiment, Figure 4 A flow chart of a method for preparing a process sheet of a TBC battery provided by an embodiment of the present invention, Figure 5 A schematic diagram of the process structure of a process sheet for preparing a TBC battery provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the process of preparing TBC battery specifically includes:

[0068] S11. Provide an N-type silicon-based substrate.

[0069] Specifically, refer to Figure 5 The N-type silicon-based substrate 10 has a first surface 11 and a second surface 12 opposite to each other, and the first surface 11 and the second surface 12 are flat, so that a whole layer of other structures can be formed on the first surface 11 and the second surface 12. The first surface 11 can be the front side of the N-type TBC battery, that is, the side receiving the light source, and the second surface 12 can be the back side of the N-type TBC battery, that is, the side facing away from the light source.

[0070] S12, forming a tunnel oxide layer and a polysilicon layer stacked in sequence on the second surface side of the N-type silicon-based substrate.

[0071] Specifically, refer to Figure 5The specific preparation process of forming the tunneling oxide layer 21 and the polysilicon layer 220 stacked in sequence on the second surface 12 side of the N-type silicon-based substrate 10 can be: first, a low-pressure chemical vapor deposition (LPCVD) preparation method can be used to form the tunneling oxide layer 21 and the polysilicon layer 220 on the second surface 12 side of the N-type silicon-based substrate 10.

[0072] It should be noted that the preparation method for forming the tunnel oxide layer 21 and the polysilicon layer 220 can be set according to actual needs. In an exemplary embodiment, the process conditions for preparing the tunnel oxide layer 21 are: temperature of 592° C., reaction time of 12 min, and oxygen flow rate of 36000 sccm. The process conditions for preparing the polysilicon layer 220 are: temperature of 585° C., reaction time of 42 min, and silane flow rate of 230 sccm.

[0073] S13, doping the polysilicon layer with phosphorus to form a phosphorus-doped polysilicon layer.

[0074] Specifically, refer to Figure 5 , the process wafer with the tunneling oxide layer 21 and the polysilicon layer 220 formed on the second surface 12 side is placed in a low-pressure diffusion furnace, and phosphorus diffusion is completed in the low-pressure diffusion furnace. The phosphorus in the low-pressure diffusion furnace can be diffused and doped into the polysilicon layer 220 to form a phosphorus-doped polysilicon layer 22, thereby forming a passivation contact structure composed of the tunneling oxide layer 21 and the phosphorus-doped polysilicon layer 22, which is beneficial to reducing surface recombination and metal contact recombination.

[0075] It should be noted that the phosphorus doping depth in the phosphorus-doped polysilicon layer 22 is related to the reaction conditions. For example, the thickness of the undoped polysilicon layer 220 is 110 nm. After the polysilicon layer 220 is doped with phosphorus, the phosphorus-doped polysilicon layer 22 formed includes a phosphorus-doped polysilicon layer with a thickness of 60 nm and a non-doped polysilicon layer with a thickness of 50 nm. At this time, the phosphorus doping depth is 60 nm. The process conditions of phosphorus diffusion can be adjusted according to actual needs to form a phosphorus-doped polysilicon layer 22 with a desired phosphorus doping depth.

[0076] It can be understood that the preparation process of phosphorus doping includes: reaction temperature of 850℃~950℃, reaction pressure of 175mbar~190mbar, introduction of phosphorus oxychloride (POCl3) with a flow rate of 125-150sccm / min, oxygen with a flow rate of 700~800sccm / min, nitrogen with a flow rate of 1250~2400sccm / min, and deposition time of 10min~14min; when the temperature of the N-type silicon-based substrate rises to 970℃-1050℃, the reaction pressure is controlled to be 950mbar, the oxygen flow rate is 9500~14000sccm / min, and the deposition time is 40min~55min to form phosphorus-doped polysilicon and reduce the metal contact resistivity. The square resistance of the process wafer after phosphorus expansion is 30~40Ω / sq, and the junction depth of ECV is 0.5~1.5μm. For example, the sheet resistance after phosphorus diffusion is 35Ω / sq, and the junction depth of ECV is 1.08μm.

[0077] S14, etching the tunnel oxide layer and the phosphorus-doped polysilicon layer to form an opening to expose a portion of the N-type silicon-based substrate on the second surface side.

[0078] The opening is in the shape of a fork finger.

[0079] Specifically, refer to Figure 5 The tunnel oxide layer 21 and the phosphorus-doped polysilicon layer 22 on the second surface 20 side of the N-type silicon-based substrate 10 include an opening OP, and the opening OP can expose the N-type silicon-based substrate 10 on the second surface 20 side. The opening OP can be obtained by physical grinding, ion beam etching or laser, etc., and this embodiment of the present invention does not specifically limit this.

[0080] In an optional embodiment, laser etching can be used to tunnel the oxide layer and the phosphorus-doped polysilicon layer to form an opening OP. A laser is used to use picosecond green light to perform grooving by laser marking. The laser marking speed is 38000-42000 mm / min, the laser power is 20W-25w, and the frequency is 1200-1600Hz to form an opening with a width of 250μm-350μm and a depth of 1μm-2μm. Exemplarily, the laser marking speed is 40000 mm / min, the laser power is 22w, and the frequency is 1400Hz. The width of the opening after the laser is 300 microns and the depth is 1.35 microns.

[0081] S15, boron-doping the N-type silicon-based substrate in the opening to form a P-type doped layer.

[0082] Specifically, refer to Figure 5The process wafer including the opening OP on the second surface 12 side can be placed in a low-pressure diffusion furnace, and the boron diffusion can be completed in the low-pressure diffusion furnace. The boron in the low-pressure diffusion furnace can be diffused and doped into the N-type silicon-based substrate 10 to form a P-type doped layer 31, and the P-type doped layer forms a PN junction with the N-type silicon-based substrate.

[0083] In an optional embodiment, the boron doping preparation process includes: a reaction temperature of 850°C to 900°C, a flow rate of 250-310 sccm of boron chloride (BCl3), and a reaction time of 400s to 450s. Exemplarily, the reaction temperature is 870°C, a flow rate of 280 sccm of boron chloride (BCl3) is introduced, and the reaction time is 420s.

[0084] It can be understood that the above-mentioned process of preparing the process sheet of the TBC battery is only an exemplary method of the present invention, and the method of preparing the process sheet of the TBC battery in the embodiment of the present invention is not limited to this. For example, after or before the step of etching the opening, a velvet surface can be formed on the side of the first surface 11 to improve the light absorption rate of the TBC battery.

[0085] Optional, Figure 6 A flow chart of another method for preparing a TBC battery process sheet provided by an embodiment of the present invention, Figure 7 A schematic diagram of the process structure of another process sheet for preparing a TBC battery provided by an embodiment of the present invention is shown in FIG. Figure 6 As shown, the process of preparing TBC battery specifically includes:

[0086] S11', providing an N-type silicon-based substrate.

[0087] S12', forming a tunnel oxide layer and a polysilicon layer stacked in sequence on the second surface side of the N-type silicon-based substrate.

[0088] S13', doping the polysilicon layer with phosphorus to form a phosphorus-doped polysilicon layer.

[0089] S14', etching the tunnel oxide layer and the phosphorus-doped polysilicon layer to form an opening to expose a portion of the N-type silicon-based substrate on the second surface side.

[0090] The opening is in the shape of a fork finger.

[0091] S15', chain pickling is performed on the first surface side of the process sheet.

[0092] Specifically, refer to Figure 7 By chain pickling the first surface 11 side, metal impurities or metal hydroxides such as Al, Fe, Zn, Ni, etc. on the first surface 11 side of the N-type silicon-based substrate 10 are removed, so that the first surface 11 side has a clean surface, which is convenient for subsequent surface texturing.

[0093] It should be noted that the chain pickling process can be set according to actual needs. In an optional embodiment, hydrochloric acid with a mass percentage of 1% to 5% is used to clean the first surface 11. Exemplarily, the mass percentage of hydrochloric acid in the chain pickling is 1.5%.

[0094] S16', performing a texturing treatment on the first surface side and the second surface side of the process sheet to form a textured surface on the first surface side.

[0095] Specifically, a protective film layer can be provided on the surface of the phosphorus-doped polysilicon layer 22 facing away from the N-type silicon-based substrate 10 to prevent the texturing process from affecting the phosphorus-doped polysilicon layer 22. Then, the process wafer is placed in a texturing tank for texturing to form a velvet surface on the first surface 11 side, and there is a certain height difference between the second surface 12 side in the opening OP and the phosphorus-doped polysilicon layer, so that a slight velvet surface is formed on the second surface 12 side in the opening OP. This step mainly forms a pyramid-shaped velvet surface on the first surface 11 side to reduce the reflectivity of the TBC cell surface.

[0096] It should be noted that the process conditions of the texturing treatment can be set according to actual needs. In an exemplary embodiment, the process conditions of the texturing treatment include: 36L of concentrated KOH alkali solution, 8L of texturing additive, 450L of water, a reaction temperature of 65°C, and a reaction time of 320s. Other conditions may also be used, which are not specifically limited here.

[0097] S17', performing a first oxidation treatment on the first surface of the process wafer.

[0098] Specifically, after the texturing treatment, a first silicon oxide protective layer 251 is formed on the first surface 11 side through a first oxidation process, which can prevent the subsequent preparation process from affecting the texture on the first surface 11 side and protect the texture on the first surface 11 side.

[0099] Optionally, in one embodiment, the first silicon oxide protective layer 251 is formed by a thermal oxidation process, the temperature of the thermal oxidation process is 400-500° C., the oxygen flow rate is 2500-3000 sccm, and the reaction time is 8 min to 12 min. For example, the first surface 11 is subjected to thermal oxidation at a temperature of 450° C., an oxygen flow rate of 2700 sccm, and a reaction time of 10 min to form the first silicon oxide protective layer 251.

[0100] S18', boron-doping the N-type silicon-based substrate in the opening to form a P-type doped layer.

[0101] S19', performing a second oxidation treatment on the second surface side.

[0102] The temperature of the second oxidation treatment is 750°C to 1000°C, the oxygen flow rate is 2000sccm to 2500sccm, and the time is 25 minutes to 35 minutes. On this basis, the process conditions of the second oxidation treatment can be set according to actual needs. In an exemplary embodiment, the reaction temperature of the second oxidation treatment is 780°C, the oxygen flow rate is 2200sccm, and the reaction time is 30 minutes.

[0103] Specifically, after forming the P-type doping layer, the boron in the P-type doping layer 31 is evenly distributed through the second thermal oxidation process, thereby improving the preparation reliability of the P-type doping layer 31. During the second oxidation process, a second silicon oxide protective layer 252 is formed on the second surface 12 side.

[0104] S20', performing chain pickling and alkali polishing on the first surface side and the second surface side.

[0105] Specifically, by performing chain pickling and alkali polishing on the first surface 11 side and the second surface 12 side, the borosilicate glass (not shown in the figure) produced when preparing the P-type doping layer 31, as well as the first silicon oxide protective layer 251 produced during the first oxidation treatment and the second silicon oxide protective layer 252 produced during the second oxidation treatment are removed, thereby exposing the P-type doping regions and N-type doping regions arranged in a forked-finger-like manner.

[0106] It should be noted that the specific process parameters of chain pickling and alkali polishing can be set according to actual needs. For example, 1.2% by mass hydrochloric acid and 1.5% by mass hydrofluoric acid are used to chain pickle the process sheet. A mixed solution including 26L of concentrated KOH alkali solution, 4L of alkali polishing additive and 440L is used to react for 2800s at a temperature of 65°C to achieve alkali polishing of the process sheet.

[0107] It can be understood that the process of preparing the process sheet of the TBC battery shown above is only an exemplary method of the present invention, and the method of preparing the process sheet of the TBC battery in the embodiment of the present invention is not limited to this. For example, after forming the tunneling oxide layer and the phosphorus-doped polysilicon layer, a protective layer can be first prepared on the surface of the phosphorus-doped polysilicon layer on the side away from the N-type silicon-based substrate, and then an opening is etched to form a P-type doped layer in the opening.

[0108] Figure 8 A schematic diagram of the process structure of another process sheet for preparing a TBC battery provided by an embodiment of the present invention, referring to Figure 8The process of preparing a TBC cell includes: providing an N-type silicon-based substrate; forming a tunneling oxide layer and a polysilicon layer stacked in sequence on the second surface side of the N-type silicon-based substrate; and phosphorus-doping the polysilicon layer to form a phosphorus-doped polysilicon layer. A protective layer is prepared on the surface of the phosphorus-doped polysilicon layer facing away from the N-type silicon-based substrate. The tunneling oxide layer and the phosphorus-doped polysilicon layer are etched to form an opening to expose a portion of the N-type silicon-based substrate on the second surface side; the shape of the opening is a fork finger shape. The N-type silicon-based substrate in the opening is boron-doped to form a P-type doped layer. The second surface side is pickled and alkaline polished to remove the silicon oxide layer; the first surface side and the second surface side are chain pickled to remove the silicon nitride layer.

[0109] The protective layer is used to protect the phosphorus-doped polysilicon layer and the tunneling oxide layer.

[0110] Specifically, by preparing a protective layer (23 and 24) on the surface of the phosphorus-doped polysilicon layer 22 facing away from the N-type silicon-based substrate 10, the phosphorus-doped polysilicon layer 22 is prevented from being affected by the preparation process or preparation environment used in the subsequent preparation of the P-type doped layer 31, and the N-type doped region formed by the phosphorus-doped polysilicon layer 22 and the tunneling oxide layer 21 is protected. Since the protective layer is provided, when the tunneling oxide layer and the phosphorus-doped polysilicon layer are etched to form an opening to expose a portion of the N-type silicon-based substrate on the second surface side, the protective layer, the phosphorus-doped polysilicon layer and the tunneling oxide layer need to be etched successively to form an opening OP that can expose the N-type silicon-based substrate 10 on the second surface 12 side. Since a protective layer is provided, after forming the P-type doped layer, the second surface side needs to be pickled and alkaline polished to remove the borosilicate glass formed during boron diffusion and the silicon oxide layer 23 in the protective layer. The first surface 11 side and the second surface 12 side are chain pickled to remove the silicon nitride layer 24 and impurities located on the first surface 11 side, so that the surface of the process sheet for forming the TBC battery has better cleanliness.

[0111] Optionally, a protective layer is formed on the surface of the phosphorus-doped polysilicon layer facing away from the N-type silicon-based substrate, including forming a silicon nitride layer 23 on the surface of the phosphorus-doped polysilicon layer facing away from the N-type silicon-based substrate; and forming a silicon oxide layer 24 on the surface of the silicon nitride layer 23 facing away from the N-type silicon-based substrate 10.

[0112] The protective layer includes a silicon nitride layer 23 and a silicon oxide layer 24 .

[0113] Specifically, the silicon nitride layer 23 mainly prevents the alkaline solution or the like used in the subsequent preparation of the P-type doped layer 31 from corroding the area where the phosphorus-doped polysilicon layer 22 is located, and the silicon oxide layer 24 mainly prevents the acidic solution or the like used in the preparation of the P-type doped layer 31 from corroding the area where the phosphorus-doped polysilicon layer 22 is located, so as to protect the phosphorus-doped polysilicon layer 22.

[0114] Based on the same inventive concept, an embodiment of the present invention provides a TBC battery, which is manufactured using the TBC battery manufacturing method of any embodiment of the present invention and has the same beneficial effects as the above method. Please refer to the above description and no further details will be given here.

[0115] It can be understood that the TBC battery provided in the embodiment of the present invention can be manufactured using the manufacturing method of the TBC battery provided in any embodiment of the present invention. In the actual production and application process, the specific preparation parameters can be adaptively selected according to the parameters mentioned in the embodiment of the present invention to form a corresponding TBC battery.

[0116] In an optional embodiment, the preparation process of a TBC battery provided by the present invention is as follows:

[0117] (1) Take an N-type silicon-based substrate of 182 mm*191 mm and perform alkali polishing on it to polish the surfaces of both sides of the N-type silicon-based substrate.

[0118] The alkali polishing solution in the alkali polishing treatment includes 6% by mass of concentrated KOH solution, 1.3% by mass of alkali polishing additive and 92.7% by mass of aqueous solution. The treatment time is 260s and the treatment temperature is 75°C.

[0119] (2) A tunnel oxide layer and a polysilicon layer are sequentially formed on the second surface side (back surface) of the N-type silicon-based substrate.

[0120] Wherein, the tunneling oxide layer comprises silicon oxide.

[0121] The process conditions for forming the tunnel oxide layer are: oxygen flow rate of 36000sccm, reaction temperature of 582°C, and reaction time of 12min. The process conditions for forming the polysilicon layer are: silane flow rate of 230sccm, reaction temperature of 585°C, and reaction time of 42min. The thickness of the tunnel oxide layer is 1.5nm, and the thickness of the polysilicon layer is 110nm.

[0122] (3) Phosphorus is doped into the polysilicon layer.

[0123] In the phosphorus diffusion process, the temperature is 880℃, POCl 3 The deposition was carried out for 12 minutes under the conditions of 130 sccm / min of oxygen flow, 750 sccm / min of nitrogen flow, and 1800 sccm / min of pressure at 182 mbar, and then the silicon wafer was heated to 1010°C and treated for 47 minutes under the conditions of 950 mbar of pressure and 12000 sccm / min of oxygen flow to obtain a phosphorus-doped polysilicon layer. The square resistance after phosphorus diffusion is 35Ω / sq, and the ECV junction depth is 1.08μm.

[0124] (4) Take the N-type silicon-based substrate after phosphorus diffusion and perform tubular backside thermal oxidation treatment on the second surface side.

[0125] Among them, the backside thermal oxidation treatment can improve the diffusion uniformity of phosphorus in the polysilicon layer.

[0126] The back thermal oxygen treatment process is: oxygen flow rate is 2500sccm, reaction time is 12min, and reaction temperature is 470°C.

[0127] (5) A silicon nitride protective layer is formed on the surface of the phosphorus-doped polysilicon layer facing away from the N-type silicon-based substrate.

[0128] The process conditions for forming the silicon nitride protective layer are: reaction for 520 seconds at a temperature of 460° C., an ammonia flow rate of 11500 sccm, a silane flow rate of 1800 sccm, a nitrogen dioxide flow rate of 1200 sccm, and a pressure of 1700 N.

[0129] (6) A silicon oxide protective layer is formed on the surface of the silicon nitride protective layer facing away from the N-type silicon-based substrate.

[0130] The process conditions for forming the silicon oxide protective layer are: temperature of 400° C., oxygen flow rate of 8000 sccm, and reaction time of 240 s.

[0131] (7) A P-type doped region and an N-type silicon-based substrate arranged in an interdigitated manner are formed on the second surface side.

[0132] The silicon oxide protective layer, silicon nitride protective layer, phosphorus-doped polysilicon layer and tunneling oxide on the second surface side are laser grooved by laser marking. A laser with a rated power of 22W is used, and the laser marking speed is 40000mm / min and the frequency is 1400Hz, forming an opening with a width of 300μm and a depth of 1.35μm to expose the N-type silicon substrate.

[0133] (8) After the laser grooved N-type silicon-based substrate has been subjected to chain pickling, the first surface side and the second surface side are subjected to texturing treatment.

[0134] Among them, chain pickling can remove impurities generated by laser grooving.

[0135] Chain pickling process conditions: hydrochloric acid concentration is 1.5% and the reaction time is 30s.

[0136] The process conditions of the texturing treatment are as follows: the alkali polishing solution includes 7% by mass of concentrated KOH solution, 1.6% by mass of alkali polishing additive and 91.4% by mass of aqueous solution, the treatment time is 320s, and the treatment temperature is 65°C to form a velvet surface on the first surface side.

[0137] (9) The first surface side of the N-type silicon-based substrate after the texturing treatment is subjected to a front-side thermal oxidation treatment.

[0138] The process conditions of the front thermal oxygen treatment are as follows: temperature of 450°C, oxygen flow rate of 2700sccm, and reaction time of 10min.

[0139] (10) Boron is diffused into the N-type silicon-based substrate exposed on the second surface side by boron diffusion to form a P-type doped layer.

[0140] The process conditions for boron diffusion are: a boron chloride flow rate of 280 sccm, a reaction temperature of 870°C, and a reaction time of 420 s.

[0141] (11) The second surface side of the N-type silicon-based substrate after the boron diffusion treatment is subjected to a backside thermal oxidation treatment.

[0142] Among them, back-side thermal oxidation treatment can improve the diffusion uniformity of boron in the N-type silicon-based substrate.

[0143] The process conditions of the backside thermal oxidation treatment are as follows: temperature of 780°C, oxygen flow rate of 2200 sccm, and reaction time of 30 min. The sheet resistance after thermal oxidation treatment is 55Ω / sq.

[0144] (12) After the first surface side is subjected to back chain pickling, the first surface side and the second surface side are subjected to alkali polishing.

[0145] The back chain pickling can remove the borosilicate glass generated in the boron diffusion process. The alkali polishing can remove the silicon oxide formed on the first surface side and the second surface side due to the thermal oxidation treatment and the silicon oxide protective layer on the second surface side.

[0146] Chain pickling process conditions: hydrochloric acid concentration is 1.2%, hydrofluoric acid concentration is 1.5%, and reaction time is 30s.

[0147] The process conditions of the texturing treatment are as follows: the alkali polishing solution includes 5.5% by mass of concentrated KOH solution, 0.9% by mass of alkali polishing additive and 93.6% by mass of aqueous solution, the treatment time is 2800s, and the treatment temperature is 65°C.

[0148] (13) The first surface side and the second surface are chain pickled on both sides.

[0149] Among them, the front and back chain pickling can remove the silicon nitride protective layer on the second surface side and remove impurities and the like located on the first surface side.

[0150] Front and back chain pickling process conditions: hydrochloric acid concentration is 1.5%, hydrofluoric acid concentration is 1%, and reaction time is 30s.

[0151] (14) An anti-ultraviolet layer is deposited on the first surface side.

[0152] Wherein, the anti-ultraviolet layer comprises aluminum oxide.

[0153] The process conditions for depositing aluminum oxide are: reaction temperature of 280° C., reaction time of 60 s, flow rate of trimethylaluminum (TMA) of 18 sccm, oxygen flow rate of 12 sccm, and 35 cycles to form aluminum oxide with a thickness of 8 nm.

[0154] (15) Passivation layers are formed on the first surface side and the second surface side.

[0155] Wherein, the passivation layer includes silicon nitride.

[0156] The process conditions for preparing silicon nitride are as follows: silane flow rate is 1300 sccm, oxygen flow rate is 9000 sccm, reaction pressure is 1700N, reaction temperature is 525°C, and reaction time is 60s.

[0157] (16) Printing silver paste in the area where the phosphorus-doped polysilicon layer is located on the second surface side, and printing silver paste in the area where the P-type doped layer is located.

[0158] (17) The silicon wafer is subjected to high temperature sintering, light injection and laser sintering to produce a TBC battery.

[0159] The peak temperature of high temperature sintering is 748°C.

[0160] The light injection temperature is 528°C and the light intensity is 6800W / m 2 .

[0161] The laser power for laser sintering was 16 W and the applied reverse voltage was 32 V.

[0162] The opening voltage of the laser sintered TBC battery is 741.5mv, the short-circuit current is 13.984A, the fill factor is 85.72%, and the photoelectric conversion efficiency is 26.573%. The laser sintered TBC battery is placed in an ultraviolet irradiation device for aging experiments. The ultraviolet irradiation device provides an ultraviolet illuminance of 180W / m 2 The cumulative radiation intensity is UV30KWh / m 2 , the opening voltage before and after the aging test is obtained, and the opening voltage decay rate of the TBC battery is determined to be 0.75%. This is much lower than the decay rate of 2% of ordinary TBC batteries. In this way, by setting an anti-ultraviolet layer in the TBC battery, the working stability of the TBC battery is improved, the effect of ultraviolet rays on the working performance of the TBC battery is reduced, and the service life of the TBC battery is extended.

[0163] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for preparing a TBC battery, characterized in that: include: A process wafer for preparing the TBC battery; the process wafer comprises an N-type silicon-based substrate, the N-type silicon-based substrate comprises a first surface and a second surface opposite to each other; a tunneling oxide layer and a phosphorus-doped polysilicon layer stacked in sequence are arranged on the second surface side; the tunneling oxide layer and the phosphorus-doped polysilicon layer comprise openings in a forked shape, and the openings comprise a P-type doped layer; An anti-ultraviolet layer is formed on the first surface side; the anti-ultraviolet layer is used to block ultraviolet rays; A passivation layer is formed on the first surface side and the second surface side, and a first metal gate line in contact with the P-type doped layer and a second metal gate line in contact with the phosphorus-doped polysilicon layer are formed on a surface of the passivation layer facing away from the N-type silicon substrate to produce the TBC battery.

2. The method for preparing a TBC battery according to claim 1, characterized in that: The anti-ultraviolet layer comprises aluminum oxide, and the thickness of the anti-ultraviolet layer is 6nm-10nm.

3. The method for preparing a TBC battery according to claim 2, characterized in that: An anti-ultraviolet layer is formed on the first surface side, comprising: Put the process sheet of the TBC battery into a reaction chamber; the temperature of the reaction chamber is 270°C to 290°C; Trimethylaluminum with a flow rate of 15 sccm to 20 sccm and oxygen with a flow rate of 10 sccm to 15 sccm are introduced into the reaction chamber; the cycle range is 55s to 65s, and the cycle is performed for 26 to 45 cycles.

4. The method for preparing a TBC battery according to claim 1, characterized in that: The process of preparing the TBC battery sheet includes: Providing the N-type silicon-based substrate; Forming the tunnel oxide layer and the polysilicon layer stacked in sequence on the second surface side of the N-type silicon-based substrate; Doping the polysilicon layer with phosphorus to form the phosphorus-doped polysilicon layer; The tunnel oxide layer and the phosphorus-doped polysilicon layer are etched to form the opening to expose a portion of the N-type silicon-based substrate on the second surface side; the opening is in an interdigitated shape; The N-type silicon-based substrate in the opening is doped with boron to form the P-type doped layer.

5. The method for preparing a TBC battery according to claim 4, characterized in that: Before boron doping is performed on the N-type silicon-based substrate in the opening, the method further comprises: performing chain pickling on the first surface side of the process sheet; Performing a texturing treatment on the first surface side and the second surface side of the process sheet to form a velvet surface on the first surface side; The first surface of the process sheet is subjected to a first oxidation treatment.

6. The method for preparing a TBC battery according to claim 5, characterized in that: After boron doping is performed on the N-type silicon-based substrate in the opening to form the P-type doped layer, the method further includes: performing a second oxidation treatment on the second surface side; performing chain pickling and alkali polishing on the first surface side and the second surface side; The temperature of the second oxidation treatment is 750° C. to 1000° C., the oxygen flow rate is 2000 sccm to 2500 sccm, and the time is 25 minutes to 35 minutes.

7. The method for preparing a TBC battery according to claim 4, characterized in that: Before etching the tunnel oxide layer and the phosphorus-doped polysilicon layer to form the opening, the method further includes: A protective layer is prepared on the surface of the phosphorus-doped polysilicon layer on one side away from the N-type silicon-based substrate; the protective layer is used to protect the phosphorus-doped polysilicon layer and the tunneling oxide layer.

8. The method for preparing a TBC battery according to claim 7, characterized in that: A protective layer is prepared on a surface of the phosphorus-doped polysilicon layer on a side away from the N-type silicon-based substrate, comprising: Forming a silicon nitride layer on a surface of the phosphorus-doped polysilicon layer that is away from the N-type silicon-based substrate; A silicon oxide layer is prepared on the surface of the silicon nitride layer on the side away from the N-type silicon-based substrate; and the protective layer includes the silicon nitride layer and the silicon oxide layer.

9. The method for preparing a TBC battery according to claim 8, characterized in that: After boron doping is performed on the N-type silicon-based substrate in the opening to form the P-type doped layer, the method further includes: Performing acid washing and alkali polishing on the second surface side to remove the silicon oxide layer; The first surface side and the second surface side are chain pickled to remove the silicon nitride layer.

10. A TBC battery, characterized in that: The TBC battery is prepared by the preparation method of any one of claims 1 to 9.

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