Ceramic substrate, ceramic circuit substrate, and semiconductor device

Abstract

A ceramic substrate according to an embodiment is characterized in that an AC voltage of 50 Hz or 60 Hz is applied between a front surface and a back surface at a boost speed of 200 V / s, an arc discharge voltage A (kV) when arc discharge is detected is measured, and an insulation breakdown voltage B (kV) between the front surface and the back surface is measured in accordance with IEC672-2. The ratio A / B of the arc discharge voltage A to the insulation breakdown voltage B is 0.3 or more. It is preferable for the ceramic substrate to have, in an arbitrary cross-section, a 90 [mu] m * 120 [mu] m region in which the number of first voids having an area of 1 [mu] m2 is in the range of 30-500 inclusive and the number of second voids having an area of 1 [mu] m2 or more is in the range of 0-30 inclusive.

Description

Technical Field

[0001] The embodiments described below generally relate to a ceramic substrate, a ceramic circuit substrate, and a semiconductor device. Background Art

[0002] In recent years, with the improvement of the performance of industrial equipment, the power modules installed therein have been developing at a higher output. Along with this, the semiconductor elements have been developing at a higher output. The guaranteed operating temperature of semiconductor elements is 125°C to 150°C, but it may rise to 175°C or above in the future. Ceramic circuit substrates are used as circuit substrates for mounting semiconductor elements. Examples of ceramic substrates include silicon nitride substrates, aluminum nitride substrates, and aluminum oxide substrates.

[0003] For example, Japanese Patent No. 6293772 (Patent Document 1) discloses a silicon nitride substrate having a thermal conductivity of 50 W / m·K or more and a three-point bending strength of 600 MPa or more. In Patent Document 1, the distribution of the grain boundary phase in the thickness direction of the substrate is controlled. In Japanese Patent No. 5928896 (Patent Document 2), the area ratio of voids having an equivalent circle diameter of 0.5 μm or more is controlled.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent No. 6293772

[0007] Patent Document 2: Japanese Patent No. 5928896 Summary of the invention

[0008] Technical problem to be solved by the invention

[0009] The silicon nitride substrates described in Patent Document 1 and Patent Document 2 both have excellent insulation properties. On the other hand, from the perspective of long-term reliability, there is still room for improvement. In previous insulation tests, insulation resistance was measured as a destructive test. In the insulation resistance test, electrodes are arranged on the front and back of the ceramic substrate, respectively, and the voltage at which insulation breakdown occurs is measured. Despite the high insulation resistance, ceramic substrates with insufficient long-term reliability may sometimes be produced. The reasons for this have been studied, and it is known that the conditions used in the insulation resistance test deviate greatly from the practical electric field, and there may also be cases where the measured insulation resistance is inappropriate as an indicator of long-term reliability. For example, relative to the practical voltage of the semiconductor device of about 1 kV, a large voltage of about 9 kV is applied in the insulation resistance test. An embodiment is an embodiment for addressing such a technical problem, and is used to provide a ceramic substrate that can obtain long-term reliability of insulation.

[0010] Means for solving technical problems

[0011] The ceramic substrate of the embodiment is characterized in that an AC voltage of 50 Hz or 60 Hz is applied between the front and back surfaces at a voltage boost rate of 200 V / s, an arc discharge voltage A (kV) is measured when arc discharge is detected, and when the insulation breakdown voltage B (kV) between the front and back surfaces is measured in accordance with IEC672-2, a ratio A / B of the arc discharge voltage A to the insulation breakdown voltage B is greater than 0.3. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram showing an example of a ceramic substrate according to an embodiment.

[0013] Figure 2 It is a schematic diagram showing an example of a cross-sectional structure of a ceramic substrate.

[0014] Figure 3 It is a schematic diagram showing an example of a ceramic circuit board according to an embodiment.

[0015] Figure 4 It is a schematic diagram showing an example of a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0016] The ceramic substrate of the embodiment is characterized in that an AC voltage of 50 Hz or 60 Hz is applied between the front and back surfaces at a voltage boost rate of 200 V / s, an arc discharge voltage A (kV) is measured when arc discharge is detected, and when the insulation breakdown voltage B (kV) between the front and back surfaces is measured in accordance with IEC672-2, a ratio A / B of the arc discharge voltage A to the insulation breakdown voltage B is greater than 0.3.

[0017] Figure 1 Schematic diagram showing an example of a ceramic substrate according to an embodiment. Figure 1 In the figure, reference numeral 1 denotes a ceramic substrate. Figure 1 In the figure, a rectangular substrate is exemplified. The ceramic substrate 1 can be in various shapes such as a circle, an ellipse, a triangle, a square, a pentagon, etc. If necessary, holes for screw fixing can be provided in the ceramic substrate 1.

[0018] First, the method for measuring the arc discharge voltage is described. Electrodes are arranged on the front and back sides of the ceramic substrate 1, respectively, and the ceramic substrate 1 is clamped by a pair of electrodes. In this state, an AC voltage of 50 Hz or 60 Hz is applied between the electrodes. The voltage increase rate is set to 200 V / s. The voltage when the arc discharge is detected between the electrodes is measured as the arc discharge voltage (kV). When measuring the arc discharge voltage, the voltage application is stopped without further increasing the voltage.

[0019] For example, the electrode uses a spherical electrode with a tip diameter of 10 mm as specified in JIS-C-2110-1 (2013). JIS-C-2110-1 corresponds to IEC60243-1. Regarding the measurement environment, the temperature is managed at 10°C to 25°C, the humidity is managed at 30% to 60%, and the measurement is performed in the atmosphere. Alternatively, the arc discharge voltage can be measured in insulating oil such as silicone oil that is stable to the electric field.

[0020] For a ceramic substrate, the arc discharge voltage is measured at any three locations, and the average value is recorded as the arc discharge voltage A (kV). In addition, the three locations are selected so as not to overlap each other. In addition, the maximum voltage is set to 20 kV. The ceramic substrate 1 to be measured is contained in a container so that the measurement is not affected by the airflow. The measuring device preferably uses the AC withstand voltage tester-7473 manufactured by the Measurement Technology Research Institute. Alternatively, a device having an arc discharge detection function equal to or higher than that thereof may be used. The unit of the arc discharge voltage A can be "kV / mm" obtained by dividing the voltage by the thickness of the ceramic substrate.

[0021] The insulation breakdown voltage is measured according to the insulation breakdown strength test of JIS-C-2141 (1992). JIS-C-2141 corresponds to IEC672-2. The test is performed by a two-terminal method. Electrodes are arranged on the front and back sides of the ceramic substrate 1, and the ceramic substrate 1 is clamped by a pair of electrodes. In this state, an AC voltage of 50 Hz or 60 Hz is applied between the electrodes to increase the voltage. The voltage increase rate is set to 200 V / s. The voltage when the insulation breakdown occurs in the ceramic substrate 1 is measured as the insulation breakdown voltage B (kV).

[0022] For example, the electrode uses a spherical electrode with a tip diameter of 10 mm as specified in JIS-C-2110-1 (2013). The electrode conditions when measuring the insulation breakdown voltage B are the same as the electrode conditions when measuring the arc discharge voltage A. The maximum voltage is set to 20 kV. The unit of the insulation breakdown voltage B can be "kV / mm" obtained by dividing the voltage by the thickness of the ceramic substrate 1. The unit of the arc discharge voltage and the unit of the insulation breakdown voltage are unified into one of "kV" or "kV / mm".

[0023] The electrodes, voltage rise rate and measuring environment when measuring the insulation breakdown voltage are the same as those when measuring the arc discharge voltage. In addition, when the size of the ceramic substrate is small, the catalog value can also be used as the insulation breakdown voltage of the ceramic substrate 1. As a reference for the size, when one side is less than 5 mm, it is preferred to use the catalog value.

[0024] Regarding the ceramic substrate 1 of the embodiment, when the arc discharge voltage A (kV) and the dielectric breakdown voltage B (kV) are measured by the above-mentioned method, the ratio A / B is 0.3 or more.

[0025] When an alternating electric field of a certain frequency is applied to the ceramic substrate 1, arc discharge is detected as a pulse current generated periodically. For example, arc discharge is easily generated in a structure where the electric field is concentrated. Arc discharge is generated inside the ceramic substrate 1 due to gaps, etc. When a voltage is applied to the ceramic substrate 1, a shared voltage is applied to the gaps, etc. This is caused by a voltage gradient generated due to a difference in resistance value from the ceramic. In the case of a gap, the size of the shared voltage changes depending on its size and shape. When the shared voltage reaches the discharge voltage in the gap, etc., a local discharge that becomes the basis of the arc discharge is generated. The state in which the pulse current generated by the local discharge appears periodically is judged as the occurrence of arc discharge. The voltage at which the arc discharge starts is detected as the arc discharge voltage A for measurement.

[0026] As the dielectric breakdown voltage, the voltage at which current is conducted between the front and back surfaces of the ceramic substrate is measured. That is, the structural breakdown voltage at which the ceramic substrate 1 is short-circuited is measured as the dielectric breakdown voltage B.

[0027] In recent years, with the improvement of the performance of semiconductor elements, the switching frequency has become higher. Power semiconductor elements include Si elements, SiC elements, GaN elements and other elements. These switching frequencies are various between tens of Hz and hundreds of kHz. In addition, in recent years, there are also semiconductor elements with a switching frequency of about 1G. According to the switching frequency, the current is repeatedly connected and disconnected. If the current is repeatedly connected and disconnected, arc discharge may occur. The lower the arc discharge voltage of the ceramic substrate, the easier it is to cause arc discharge when the current is repeatedly connected and disconnected. If arc discharge occurs repeatedly, the insulation of the ceramic substrate will deteriorate. Therefore, the insulation of the ceramic substrate cannot be maintained for a long time. That is, although the insulation breakdown voltage is not reached, the insulation of the ceramic substrate is reduced.

[0028] Generally, the switching frequency of Si-IGBT, a type of Si element, is about 100 Hz to 50 kHz. The switching frequency of SiC-MOS elements is about 8 kHz to 1 MHz. As the switching frequency increases, the output power and power density increase. For example, for a Si-IGBT element with a switching frequency of 25 kHz, there is an output power of 3.3 kW and a power density of 0.3 W / cm 3 For SiC-MOS devices with a switching frequency of 160kHz, there are devices with an output power of 5kW and a power density of 1.8W / cm 3There are also GaAs-MESFET (Metal semiconductor) and HEMT (High Electron Mobility Transistor) devices with switching operation frequencies of 1G to 10G. An increase in switching frequency leads to an increase in output voltage or power density.

[0029] The ceramic substrate of the embodiment shows excellent insulation even when the switching frequency is as high as 8kHz or more. In addition, even when the output power is 1W or more or the power density is 1W / cm 3 The above semiconductor elements also exhibit excellent insulation properties. In other words, the insulation properties of ceramic substrates used in semiconductor devices including high-performance semiconductor elements cannot be properly evaluated only by the dielectric breakdown voltage.

[0030] In the ceramic substrate 1 of the embodiment, when measuring the arc discharge voltage A (kV) and the insulation breakdown voltage B (kV), the ratio A / B is greater than 0.3. This means that the arc discharge voltage A is greater than 0.3 times the insulation breakdown voltage B. On the other hand, a ratio A / B less than 0.3 means that the arc discharge voltage A is less than 0.3 times the insulation breakdown voltage B. In the case of using a ceramic substrate with a ratio A / B less than 0.3, although the insulation breakdown voltage is high, poor insulation of the ceramic substrate sometimes occurs when a semiconductor element with a high switching frequency is installed and used. That is, a ceramic substrate with a ratio A / B less than 0.3 sometimes lacks long-term reliability.

[0031] When an alternating electric field of a certain frequency is applied between electrodes, arc discharge is detected as a pulse current generated periodically. The initial arc discharge phenomenon occurs due to gaps in the ceramic substrate, etc. If arc discharge is repeated, arc degradation occurs. If arc degradation occurs, insulation breakdown occurs. In other words, arc discharge is a sign of insulation breakdown. Therefore, by measuring the voltage generated by arc discharge, the long-term reliability of the ceramic substrate can be confirmed.

[0032] In particular, when the switching frequency of the semiconductor element becomes higher, the number of pulse currents generated periodically increases. If the output voltage and power density increase, arc discharge is likely to occur inside the ceramic substrate. Therefore, the greater the switching frequency, output voltage, and power density, the greater the insulation of the ceramic substrate is likely to deteriorate due to arc discharge even when the ceramic substrate is not dielectrically broken down. As a result, long-term reliability issues may arise.

[0033] A ratio A / B of 0.3 or more indicates that the arc discharge voltage A is higher than that of the conventional ceramic substrate. Therefore, even when the output voltage and power density of the semiconductor element are large, arc discharge is not easy to occur. By suppressing the occurrence of arc discharge, the number of occurrences of arc discharge can be suppressed even when the switching frequency of the mounted semiconductor element is high. In other words, suppressing the occurrence of arc discharge helps to improve the reliability of semiconductor devices equipped with semiconductor elements with high switching frequencies.

[0034] The upper limit of the ratio A / B is 1.0. The ratio A / B = 1.0 indicates a state in which the arc discharge voltage is substantially the same as the insulation breakdown voltage, or a state in which arc discharge is substantially not observed. The ratio A / B = 1.0 indicates that the ceramic substrate does not have a structure that generates a periodic pulse current even when an alternating electric field of a certain frequency is applied between the electrodes. Sometimes there are substantially no gaps on the ceramic substrate, and sometimes there are gaps but arc discharges (including those below the detection limit) cannot be detected. In these cases, long-term reliability predictions cannot be made. Therefore, the ratio A / B is preferably greater than 0.3 and less than 1.0, and more preferably within the range of greater than 0.5 and less than 0.9.

[0035] In the ceramic substrate of the embodiment, it is preferable that a portion of the ceramic substrate having an area of ​​less than 1 μm exists in any cross section. 2 The number of voids is within a range of 30 to 500, and the area is 1 μm 2 The number of the above voids is within the range of 0 to 30 in an area of ​​90 μm×120 μm. Here, for the sake of convenience, the area less than 1 μm 2 The gap with an area of ​​1 μm is called a "small gap" (first gap). 2 The above gap is called "large gap" (second gap).

[0036] Figure 2 Schematic diagram showing an example of a cross-sectional structure of a ceramic substrate. Figure 2 In the figure, reference numeral 2 indicates a cross section of a ceramic substrate, and reference numeral 3 indicates an area of ​​1 μm 2 The above large gaps, reference numeral 4 indicates an area less than 1 μm 2 In the small gap. Figure 2 In the figure, the large gap 3 is represented by black, and the small gap 4 is represented by hollow.

[0037] The method of observing the cross section is described below. First, prepare an arbitrary cross section of the ceramic substrate. Use a polished surface with a surface roughness Ra of 1 μm or less as the cross section. Observe the cross section with a scanning electron microscope (SEM) and take a 1000-fold magnified photograph. Use JOEL JCM-7000, JSM-7200F or a device with equivalent or higher performance. Based on the magnified photograph taken, observe an area of ​​1 μm 2 Large gaps above 3, area less than 1μm 2 Small gap 4.

[0038] In the observation of voids, the SEM photos are analyzed using image analysis software. ImageJ or equivalent software is used as the image analysis software. In the SEM photos of the cross section, a contrast is generated between the voids and other parts. For example, the color of the voids appears darker and thicker than the color of the parts outside the voids. By using this contrast to binarize the SEM photos, it is possible to distinguish between the voids and other parts. In addition, as small voids, 0.01 μm 2 This is because the area is less than 0.01 μm. 2 The gaps are difficult to discern in the 1000x magnified photo.

[0039] The threshold used for binarization uses the value obtained by the "pattern method" or the "discriminant analysis binarization method". When the image analysis software has the function of the discriminant analysis binarization method, the discriminant analysis binarization method of the image analysis software is used. In the discriminant analysis binarization method, the threshold is uniquely determined by the analysis software. Therefore, it is easy to discriminate the void. For example, in the SEM photo, the area that looks white around the void is the boundary between the void and the silicon nitride sintered body. Therefore, the area that looks white around the void should not be counted as a void. In addition, in the SEM photo, the silicon nitride sintered body is gray. By using the threshold obtained by the "pattern method" or the "discriminant analysis binarization method", the void can be represented by black, and the white area around the void and the silicon nitride sintered body can be represented by white. By using the binarized image, the voids and other areas reflected in the SEM photo can be discriminated.

[0040] The observation area of ​​the SEM is set to a size of 180μm×430μm. Observe three areas and select the 90μm×120μm area where the most voids are observed. In addition, when the 180μm×430μm area cannot be observed in one field of view, the 180μm×430μm area can be observed multiple times. In this case, the minimum size of the observed area is 90μm×120μm. In addition, the orientation of the sample relative to the 180μm×430μm observation area and the 90μm×120μm area is arbitrary. In any cross-section, the orientation of the 180μm×430μm observation area and the orientation of the 90μm×120μm area can be adjusted so that the most voids are observed.

[0041] It is preferred that the number of large voids 3 in any cross section is in the range of 0 to 30, and the area of ​​90 μm×120 μm is present. The large voids 3 affect both the arc discharge voltage and the insulation breakdown voltage. In particular, the large voids 3 are the cause of the reduction of the arc discharge voltage. Therefore, the number of large voids 3 is preferably in the range of 0 to 30, and more preferably in the range of 0 to 20.

[0042] It is preferred that there is a 90 μm×120 μm area in any cross section in which the number of small voids 4 is within a range of more than 30 and less than 500. The small voids 4 have little effect on the arc discharge voltage and the insulation breakdown voltage. However, if the number of small voids 4 exceeds 500, the arc discharge characteristics will be affected. If the number of small voids is less than 30, the insulation is improved. On the other hand, in order to manufacture a ceramic substrate with less than 30 small voids 4, hot isostatic pressing (HIP) treatment is required, which is the main reason for the cost increase.

[0043] In addition, if there are small gaps 4, the deflection of the ceramic substrate 1 can be increased. The deflection amount indicates the amount of "deformation" from the horizontal state when stress is applied to a horizontally placed ceramic substrate. For example, the length of deflection caused by fixing both ends of the ceramic substrate and pressing the middle is called the "deflection amount". The ceramic circuit substrate is fixed by screw fixing, etc. If the deflection amount is large, the ceramic substrate can be prevented from being damaged even if the stress of the screw fixing is added. Therefore, the number of small gaps 4 present in a unit area of ​​90μm×120μm is preferably in the range of 30 or more and 500 or less, and more preferably in the range of 40 or more and 400 or less.

[0044] The number of large voids 3 and the number of small voids 4 mentioned above are the numbers counted when observing the 90μm×120μm area with the most voids in any cross section. Therefore, when observing the cross section, there may be areas where the number of large voids 3, the number of small voids 4, the area ratio described later, etc. are less than the specified range. In other words, for the ceramic substrate 1 of the embodiment, when three 180μm×430μm areas are observed, there is at least one area where the number of large voids 3 and the number of small voids 4 are within the specified range. Preferably, even when an arbitrary 90μm×120μm area is observed, there is no part where the number of large voids 3 and the number of small voids 4 are more than the specified range. For example, it is also possible to observe any three 180μm×430μm areas and determine that there is no place where the number of large voids 3 and the number of small voids 4 are more than the specified range.

[0045] By controlling the number of large voids 3 and the number of small voids 4, the ratio of arc discharge voltage A / insulation breakdown voltage B can be controlled. Furthermore, on the basis of controlling the number of large voids 3 and the number of small voids 4, the total area ratio of small voids 4 present in the area of ​​90μm×120μm is preferably in the range of 0.01% to 0.8%. By controlling the area ratio of small voids 4, insulation and deflection can be achieved at the same time. In addition, on the basis of controlling the number of large voids 3 and the number of small voids 4, the total area ratio of large voids 3 present in the area of ​​90μm×120μm is preferably in the range of 0% to 0.6%. Even if the number of macropores 3 is within the specified range, if the total area ratio is greater than 0.6%, it may become a cause of reduced insulation.

[0046] The area ratio of the large voids 3 and the area ratio of the small voids 4 are calculated in a 90 μm×120 μm region where a predetermined number of large voids 3 and small voids 4 exist. That is, in the ceramic substrate 1 of the embodiment, the area ratio is controlled while the number of large voids 3 and small voids 4 is controlled.

[0047] The maximum diameter of the voids in the area of ​​90 μm×120 μm is preferably 15 μm or less. First, when observing the cross section, measure the major axis of each void shown in the photograph. The "major axis" is the distance between the two points farthest from each other on the outer edge of the void. The largest value among the major axes of the plurality of voids is taken as the "maximum diameter". By setting the maximum diameter of the voids to 15 μm or less, the reduction in the insulation of the ceramic substrate 1 can be suppressed.

[0048] The maximum diameter of the voids is measured in the 90 μm×120 μm region where the most voids are observed. More preferably, the maximum diameter of the voids in the three regions of 180 μm×430 μm is 15 μm or less. The three regions used to measure the maximum diameter may be the same as the three regions of 180 μm×430 μm observed when counting the number of voids.

[0049] In addition, in the area of ​​90μm×120μm, the number of groups in which the distance between large voids 3 is less than 5μm is preferably greater than 0 and less than 3. The number of groups of large voids 3 is counted in the area of ​​90μm×120μm where the most voids are observed. If the distance between one large void 3 and another large void 3 is less than 5μm, these large voids 3 are counted as a group. In the case where there are two large voids 3 within a range of 5μm from one large void 3 that serves as a reference, the large void 3 that serves as a reference and the two large voids 3 are each counted as two groups. In the case where there are more than three large voids 3 within a range of 5μm from one large void 3, these large voids 3 are counted as more than three groups. For example, when the distance between each other is less than 5μm and there are three large voids 3 distributed in a triangular shape, these large voids 3 are counted as three groups.

[0050] The distance is measured using the magnified photograph of the observed cross section. A range of 5 μm is set with the observed large voids 3 as the center, and if there are other large voids 3 within the range, the number of the group is counted. Then, when a range of 5 μm is set with other large voids 3 as the center, the group counted once is not counted again.

[0051] If the distance between the large voids 3 is close to each other, these large voids 3 may have the same function as larger voids. For example, if the number of groups of large voids 3 with a distance of less than 5 μm from each other exceeds 3, the arc discharge voltage and the insulation breakdown voltage may be reduced, and the insulation of the ceramic substrate 1 will be reduced. Therefore, the number of groups of large voids 3 with a distance of less than 5 μm from each other is preferably within the range of more than 0 and less than 3, and more preferably within the range of more than 0 and less than 1. In addition, even if there are small voids 4 near the large voids 3, the group of large voids 3 and small voids 4 is not counted. This is because, even if the large voids 3 and small voids 4 are close to each other, the adverse effect on the insulation is small. Here, only the groups of large voids 3 with a distance of less than 5 μm from each other are counted.

[0052] Two or more conditions selected from the number of voids, the total area ratio, the maximum diameter of the voids, and the number of groups of large voids 3 can be combined. Most preferably, in any cross section, there is a region where the number of voids, the total area ratio, the maximum diameter, and the number of groups of large voids 3 are all within the above ranges.

[0053] The ceramic substrate 1 is one selected from a silicon nitride substrate, an aluminum nitride substrate, an aluminum oxide substrate, and an aluminum silicon substrate. The aluminum silicon substrate is a substrate containing both aluminum oxide and zirconium oxide. Among the ceramic substrates, a silicon nitride substrate is preferred. The thermal conductivity of the silicon nitride substrate is 40 W / m·K or more, and further 80 W / m·K or more. In addition, the three-point bending strength of the silicon nitride substrate is 600 MPa or more, and further 700 MPa or more.

[0054] The thermal conductivity of the aluminum nitride substrate is 160W / m·K or more, and further 200W / m·K or more. The three-point bending strength of the aluminum nitride substrate is about 300MPa to 450MPa. The three-point bending strength of the alumina substrate is about 300MPa to 450MPa, but the alumina substrate is cheaper than other substrates. In addition, the thermal conductivity of the alumina substrate is about 20W / m·K to 30W / m·K. The three-point bending strength of the aluminum-based alloy substrate is as high as about 550MPa, but the thermal conductivity is about 30W / m·K to 50W / m·K.

[0055] The thickness of the ceramic substrate 1 is preferably in the range of 0.2 mm to 3 mm. When the thickness is less than 0.2 mm, the insulation of the ceramic substrate 1 may be insufficient. When the thickness exceeds 3 mm, although the insulation of the ceramic substrate 1 is good, the heat dissipation is reduced.

[0056] Since the silicon nitride substrate has high strength, the thickness of the substrate can be within the range of 0.2 mm to 0.8 mm, and further within the range of 0.2 mm to 0.4 mm. In addition, by controlling the gap, insulation and deflection can be achieved at the same time. When the thickness of two ceramic substrates is the same, the one with a larger deflection is more difficult to break.

[0057] The arc discharge voltage A of the ceramic substrate 1 which ensures a dielectric breakdown voltage B of 10 kV / mm or more is preferably 5 kV / mm or more. By making the arc discharge pressure 5 kV / mm or more, A / B can be made 0.3 or more, and further 0.5 or more. Therefore, the ceramic substrate 1 is preferably a silicon nitride substrate with an arc discharge voltage of 5 kV / mm or more.

[0058] The ceramic substrate described above can be applied to a ceramic circuit substrate. Figure 3 Schematic diagram showing an example of a ceramic circuit substrate according to an embodiment. Figure 3 In the figure, reference numeral 1 denotes a ceramic substrate, reference numeral 5 denotes a metal portion, reference numeral 6 denotes a bonding layer, and reference numeral 10 denotes a ceramic circuit substrate.

[0059] exist Figure 3In the example shown, two metal parts 5 are bonded to the surface side of the ceramic substrate 1, and one metal part 5 is bonded to the back side of the ceramic substrate 1. The ceramic circuit substrate 10 of the embodiment is not limited to such a shape. A necessary number of metal parts 5 can be provided on the ceramic substrate 1. In addition, in the example shown in FIG. 5, a metal part 5 used as a circuit is bonded to the surface side, and a metal part 5 used as a heat sink is bonded to the back side. Without being limited to this example, a metal part 5 used as a circuit may be bonded to both sides of the ceramic substrate 1. The bonding layer 6 is preferably formed using an active metal brazing filler metal.

[0060] Figure 4 Schematic diagram showing an example of a semiconductor device according to an embodiment. Figure 4 In the drawings, reference numeral 8 denotes a semiconductor element, reference numeral 10 denotes a ceramic circuit substrate, and reference numeral 20 denotes a semiconductor device.

[0061] like Figure 4 As shown in FIG. 1 , by mounting a semiconductor element 8 on a metal portion 5 of a ceramic circuit substrate 10, a semiconductor device 20 can be manufactured. Figure 4 In the example shown, one semiconductor element 8 is mounted on one metal portion 5. A plurality of semiconductor elements 8 may be mounted on each of a plurality of metal portions 5. A plurality of semiconductor elements 8 may be mounted on one metal portion 5. In addition to the semiconductor element 8, a lead frame, wire bonding, etc. may be bonded to the metal portion 5. By improving the arc discharge voltage of the ceramic substrate 1, long-term reliability of the insulation of the semiconductor device 20 can be ensured even when a semiconductor element 8 with a high switching frequency is mounted.

[0062] Next, a method for manufacturing the ceramic substrate 1 of the embodiment is described. As long as the ceramic substrate 1 of the embodiment has the above-mentioned structure, its manufacturing method is not particularly limited. Here, an example of a method for obtaining the ceramic substrate 1 with a good yield is described. In the following example, a method for manufacturing a silicon nitride substrate is described.

[0063] First, prepare silicon nitride powder and sintering aid powder as raw materials. Use silicon nitride powder manufactured by imide decomposition method or direct nitridation method. The average particle size of silicon nitride powder is preferably in the range of 0.1 μm or more and 4 μm or less. As a sintering aid, one or more selected from rare earth elements, titanium (Ti), hafnium (Hf), magnesium (Mg) and calcium (Ca) can be used. Compounds of these elements can also be used. As compounds, oxides, nitrides, nitrogen oxides, etc. can be mentioned. As rare earth elements, yttrium (Y) and lanthanides can be mentioned. As lanthanides, ytterbium (Yb), erbium (Er), europium (Eu), lutetium (Lu), lanthanum (La), cerium (Ce), dysprosium (Dy), etc. can be listed. The average particle size of the sintering aid powder is preferably in the range of 0.1 μm or more and 4 μm or less.

[0064] It is preferred to control the amount of impurities contained in the silicon nitride powder and the sintering aid powder. As the impurities to be controlled, Fe and carbon can be listed. The powder obtained by mixing the silicon nitride powder and the sintering aid powder is called a raw mixed powder. The Fe content of the raw mixed powder is preferably 0.05% by mass or less. In addition, the carbon content of the raw mixed powder is preferably 0.5% by mass or less.

[0065] Fe and carbon present as impurities in the raw material mixed powder lead to the formation of structural defects in the sintered body. For example, Fe dissolves into a liquid phase during sintering, which significantly reduces the viscosity of the liquid phase of the dissolved portion. In liquid phase sintering, densification occurs due to grain boundary diffusion. In the portion where the liquid phase viscosity is reduced, the speed of grain boundary diffusion changes, so defects such as voids are easily generated. In particular, iron contained as an impurity is likely to cause voids. In addition, carbon has a strong reducing effect and is likely to generate defects such as voids.

[0066] In order to control the Fe content and carbon content of the raw material mixed powder, it is effective to use silicon nitride powder and sintering aid powder with low Fe content and carbon content. It is also effective to prevent the mixing of impurities in the manufacturing process. In the case where the Fe content contained in the raw material mixed powder is large, it is also effective to remove Fe using a magnet. By controlling the Fe content and carbon content, a void distribution that has no effect on the arc discharge characteristics can be obtained.

[0067] It is also effective to control the fluorine (F) or chlorine (Cl) present as impurities in the raw material mixed powder. The total content of fluorine or chlorine in the raw material mixed powder is preferably 0 wtppm or more and 1000 wtppm or less. The total content of fluorine or chlorine in the sintered body is preferably 0 wtppm or more and 1000 wtppm or less.

[0068] Fluorine and chlorine are elements that are easily contained in silicon nitride powder. The manufacturing method of silicon nitride powder is mainly made by an imide decomposition method or a direct nitridation method. In the imide decomposition method, a silicon halide is used as a raw material. In the direct nitridation method, a fluorine compound is used as a catalyst for nitriding metal silicon. Therefore, fluorine or chlorine is easily left in the silicon nitride powder.

[0069] In addition, fluorine or chlorine has a large electronegativity, so anion defects are easily generated in the sintered body. Therefore, it is possible to become the main cause of arc discharge. Therefore, the total content of fluorine or chlorine in the raw material mixed powder is preferably more than 0wtppm and less than 1000wtppm, more preferably more than 0wtppm and less than 400wtppm. Thus, the content of fluorine or chlorine contained in the silicon nitride sintered body can be less than 1000wtppm, further more than 0wtppm and less than 400wtppm.

[0070] A mixing process is performed in which silicon nitride powder and sintering aid powder are mixed and further mixed using a pulverizer. As the pulverizer, a ball mill or a bead mill can be cited. In the mixing process, a binder, a solvent, etc. are added to the silicon nitride powder and the sintering aid powder to prepare a raw powder slurry. In addition, it is preferred that the raw powder slurry has hysteresis. In order to make the slurry have hysteresis, it is effective to control thixotropy. Thixotropy is a property in which the apparent viscosity decreases over time if a certain shear stress is continuously applied, and the apparent viscosity gradually recovers if the force is removed. It is believed that the apparent viscosity reflects the internal structure of the slurry, such as the coagulation state. In JIS-R-1665 (2005), the evaluation of thixotropy based on the hysteresis measurement of the flow curve is determined.

[0071] In order to make the slurry have hysteresis, it is effective to increase the thixotropic index (TI value) which is an index of thixotropy. In order to increase the thixotropic index, for example, it is preferred to increase the particle concentration in the slurry and use a poor solvent for the dispersibility of the particles. If the particle concentration of the slurry is high, the interaction between the particles becomes larger, and the dispersion state of the particles can be made uneven. As a result, the distribution of the particles in the molded body can be made uneven and dense to a certain extent. It is easy to produce the densification voids during sintering, and the distribution of the voids can be controlled. The thixotropic index (TI value) is preferably above 1.5 and below 5.

[0072] The TI value is measured using a rotational viscometer according to JIS-R-1665 (2005). If the shear rate is continuously increased using a rotational viscometer, the viscosity usually decreases in a fluid having cohesion. At this time, the ratio of the viscosity η at the shear rate a to the viscosity η at the shear rate b becomes the TI value. That is, the TI value is represented by the following formula.

[0073] TI value = ηa / ηb

[0074] The viscosity η is measured when the shear rate a is set to 4 (1 / s), and the viscosity η is measured when the shear rate b is set to 40 (1 / s). The TI value is calculated based on ηa / ηb. The closer the TI value is to 1, the closer it is to the behavior of a Newtonian fluid, and the more highly dispersed the slurry is with no coagulation or very weak coagulation.

[0075] A TI value of 1.5 or more indicates that the slurry has some cohesion. By having cohesion, the distribution of voids in the molded body can be controlled. In addition, if the TI value exceeds 5, there is a possibility that the cohesion is too strong and the voids become too many. Therefore, the TI value of the slurry is preferably in the range of 1.5 or more and 5 or less, and more preferably in the range of 2.1 or more and 3.7 or less. The molded body is made using the slurry with controlled TI value. As a molding process, known molding methods such as scraper and mold molding can be applied. The production of a sheet-like molded body is referred to as sheet molding.

[0076] Next, a drying step of drying the molded body is performed. It is preferred that a constant drying period and a reduced-rate drying period are introduced according to the weight reduction of the solvent, and the temperature and time of the drying step are set based on the constant drying period and the reduced-rate drying period.

[0077] At the beginning of drying, there is a sufficient amount of solvent in the ceramic molded body, and the solvent forms a continuous layer at the interface of the ceramic particles. The constant rate drying period is a period during which the solvent of the ceramic molded body evaporates at a roughly constant ratio through the continuous layer. On the other hand, the deceleration drying period is a period during which the solvent inside the ceramic molded body evaporates in a state where the continuous layer of the solvent is interrupted. During the transition from the constant rate drying period to the deceleration drying period, the shrinkage stress applied to the molded body becomes maximum. Therefore, the control of the constant rate drying period, the deceleration drying period, and the transition period is related to the control of the gap.

[0078] The weight reduction rate of the solvent during the constant drying rate is preferably 1 mass% / min or more. The upper limit of the weight reduction rate of the solvent during the constant drying rate is not particularly limited, but is preferably 10 mass% / min or less. If the weight reduction rate exceeds 10 mass% / min, the voids may become larger. Therefore, the weight reduction rate of the solvent during the constant drying rate is preferably within the range of 1 mass% / min or more and 10 mass% / min or less.

[0079] The weight reduction rate of the solvent during the deceleration drying period is preferably slower than the weight reduction rate of the solvent during the constant rate drying period. In addition, the ratio of the weight reduction rates (weight reduction rate of the solvent during the constant rate drying period / weight reduction rate of the solvent during the deceleration drying period) is preferably greater than 1 and less than 20. Thus, the evaporation route of the solvent formed during the constant rate drying period can be used to evaporate the solvent inside the ceramic molded body during the deceleration drying period. If the weight reduction rate ratio (weight reduction rate of the solvent during the constant rate drying period / weight reduction rate of the solvent during the deceleration drying period) exceeds 20, the drying speed is too fast, which may be the cause of large voids. If the weight reduction rate during the deceleration drying period is slow, the manufacturing efficiency deteriorates.

[0080] The molded body subjected to the drying step is subjected to a degreasing step. The degreasing step is preferably performed at a temperature in the range of 400° C. to 800° C. The degreasing step can remove organic matter such as a binder and also removes residual solvent.

[0081] Next, a sintering process is performed. The sintering process is carried out by heating the molded body in a non-oxidizing atmosphere within a temperature range of 1650°C to 1950°C for 4 hours to 24 hours. As a non-oxidizing atmosphere, a nitrogen atmosphere or a reducing atmosphere containing nitrogen is preferred. The pressure in the sintering furnace is preferably a pressurized atmosphere. If the molded body is sintered at a sintering temperature lower than 1650°C, it is difficult to obtain a dense sintered body. On the other hand, if the molded body is sintered at a sintering temperature higher than 1950°C, self-decomposition of Si3N4 is easily caused, and it is difficult to obtain a dense sintered body. Therefore, the sintering temperature is preferably controlled within the above range.

[0082] In the temperature rise process from the degreasing process to the sintering process, a heat treatment process is preferably performed. In the heat treatment process, the molded body is kept in a range of 1400° C. to 1650° C. for 1 hour to 8 hours. Through this treatment, the diffusion of the liquid phase composed of the sintering aid is promoted and controlled, resulting in the control of the voids in the sintered body.

[0083] (Example)

[0084] (Examples 1 to 9, Comparative Examples 1 to 3)

[0085] As a ceramic substrate, a silicon nitride substrate or an aluminum nitride substrate is prepared. The mixing ratio of silicon nitride powder and sintering aid powder as raw material powder is shown in Table 1. The mixing ratio is the value when the total of any one of silicon nitride powder or aluminum nitride powder and sintering aid powder is set to 100 mass%. In the embodiments and comparative examples, the Fe amount in the raw material mixed powder is less than 0.05 mass%, and the carbon amount is less than 0.5 mass%. In addition, the total amount of fluorine and chlorine in the raw material mixed powder is less than 1000wtppm.

[0086] [Table 1]

[0087] Mixing ratio (mass %) Example 1 <![CDATA[Si3N4(89),Y2O3(4),Er2O3(4),MgO(1),TiO2(1),HfO2(1)]]> Example 2 <![CDATA[Si3N4(92),Y2O3(6),MgO(0.7),HfO2(1.3)]]> Example 3 <![CDATA[Si3N4(93),Y2O3(5),MgO(2)]]> Example 4 <![CDATA[Si3N4(93),Er2O3(6),MgO(1)]]> Example 5 <![CDATA[Si3N4(88),Y2O3(5),Er2O3(4),MgO(1.5),TiO2(1),HfO2(0.5)]]> Example 6 <![CDATA[AlN(95),Y2O3(5)]]> Example 7 <![CDATA[AlN(97),Y2O3(3)]]> Example 8 <![CDATA[Si3N4(92.8),Y2O3(5),MgO(1.2),HfO2(1.0)]]> Example 9 <![CDATA[Si3N4(93.2),Y2O3(4),MgO(2.2),HfO2(0.6) <!-- 9 -->]]> Comparative Example 1 <![CDATA[Si3N4(95),Y2O3(4),MgO(1)]]> Comparative Example 2 <![CDATA[Si3N4(92),Y2O3(6),MgO(0.7),HfO2(1.3)]]> Comparative Example 3 <![CDATA[AlN(97),Y2O3(3)]]>

[0088] A binder and a solvent are added to the raw powder to prepare a raw powder slurry. The raw powder slurry is mixed using a ball mill. The TI values ​​of the raw powder slurries are adjusted respectively. In the embodiment, the TI value is set to be within the range of not less than 2.1 and not more than 3.7. In Comparative Examples 1 to 3, the TI value is set to be within the range of not less than 5.5 and not more than 6.5. The TI value is measured in accordance with JIS-R-1665 (2005). The details of the measurement conditions are as described above. Using the obtained raw powder slurry, a sheet molding is prepared. The sheet molding is prepared using a scraper method.

[0089] The obtained sheet molding is subjected to a drying process. In the embodiment, the weight reduction rate of the solvent during the constant rate drying is within the range of 1 mass% / min or more and 10 mass% / min or less. In addition, in the embodiment, the weight reduction rate ratio (weight reduction rate of the solvent during the constant rate drying / weight reduction rate of the solvent during the deceleration drying) is set to a range of more than 1 and less than 20. In the comparative example, the weight reduction rate of the solvent during the constant rate drying is set to a range of more than 0.3 mass% / min and less than 0.8 mass% / min. In addition, the weight reduction rate ratio of the comparative example (weight reduction rate of the solvent during the constant rate drying / weight reduction rate of the solvent during the deceleration drying) is within the range of more than 1 and less than 5. The sheet molding after the drying process is subjected to a degreasing process. The degreasing process is performed in the air at a temperature of more than 400°C and less than 800°C.

[0090] The degreased body is subjected to a sintering step. During the heating process, the degreased body is kept in a non-oxidizing atmosphere at a temperature in the range of 1400° C. to 1650° C. for 1 to 8 hours. Then, the molded body is kept at a temperature in the range of 1650° C. to 1950° C. for 4 to 24 hours, thereby sintering the molded body.

[0091] Through the above process, the silicon nitride substrates of the embodiments and comparative examples are prepared. The size of the obtained silicon nitride substrate is 100 mm long side × 80 mm short side. In addition, the thermal conductivity of the silicon nitride substrate is 40 W / m·K or more and 95 W / m·K or less, and the three-point bending strength is 500 MPa or more. In addition, the size of the aluminum nitride substrate is 100 mm long side × 80 mm short side. The thermal conductivity of the aluminum nitride substrate is 150 W / m·K or more and 250 W / m·K or less, and the three-point bending strength is 300 MPa or more and 450 MPa or less.

[0092] For each silicon nitride substrate or aluminum nitride substrate, observe any cross section with SEM. In the observation using SEM, a 1000-fold magnified photograph was taken. Observe any three areas. The size of the area is 180μm×430μm. Extract the 90μm×120μm area containing the most voids from the observed area. Use image analysis software to calculate the number and area ratio of voids in the 90μm×120μm area. In the 90μm×120μm area with the largest number of voids, count the number of groups of large voids 3 with a distance of less than 5μm. Measure the long diameter of each void from three 180μm×430μm areas and extract the maximum diameter from them. Image analysis software uses ImageJ. In addition, the total amount of fluorine and chlorine in the silicon nitride substrate or aluminum nitride substrate was measured. The results are shown in Table 2.

[0093] [Table 2]

[0094]

[0095] As shown in Table 2, in the silicon nitride substrate and the aluminum nitride substrate of the embodiment, the area is less than 1 μm 2 The number of small voids is 30 or more and 500 or less. Area 1 μm 2 The number of the above macrovoids is within the range of 0 or more and 30 or less.

[0096] Next, the arc discharge voltage, insulation breakdown voltage and deflection are measured. The arc discharge voltage and insulation breakdown voltage are measured as described above. Deflection A cylindrical support member with a span width of 30 mm is arranged at both ends of the short side direction of the silicon nitride substrate. Stress is applied to the center of the substrate. The length until breakage is obtained. The results are shown in Table 3.

[0097] [Table 3]

[0098]

[0099] As can be seen from Table 3, for the silicon nitride substrate and the aluminum nitride substrate of the embodiment, the ratio of the arc discharge voltage A / insulation breakdown voltage B is greater than 0.3. The arc discharge voltage of each silicon nitride substrate and each aluminum nitride substrate of the embodiment is greater than 5 kV, and the insulation breakdown voltage is greater than 8.5 kV. In addition, if the insulation breakdown voltage is divided by the thickness of the ceramic substrate, the unit can be kV / mm. For example, in Example 1, the thickness of the silicon nitride substrate is 0.32 mm, so the insulation breakdown voltage of the silicon nitride substrate is 30.3 kV / mm. In addition, the insulation breakdown voltage of the aluminum nitride substrate of the embodiment is greater than 9.3 kV. In the embodiment, good results were also obtained regarding the amount of deflection. In addition, as in Example 9, if the void content and fluorine content are high, A / B is slightly reduced to 0.51.

[0100] In the examples, it is found that the arc discharge voltage can be improved while maintaining the dielectric breakdown voltage of the ceramic substrate, and thus the long-term reliability of the insulation of the silicon nitride substrate and the aluminum nitride substrate is improved.

[0101] In contrast, in Comparative Examples 1, 2, and 3, although the insulation breakdown voltage is the same as that of the embodiment, the arc discharge voltage is reduced. This is because the number of voids, the area ratio, etc. are outside the preferred range. From this point of view, the silicon nitride substrate and the aluminum nitride substrate of the embodiment can take into account both the long-term reliability of insulation and cost reduction.

[0102] Implementations of the invention may include the following features.

[0103] (Feature 1)

[0104] A ceramic substrate, wherein an AC voltage of 50 Hz or 60 Hz is applied between the front and back surfaces at a voltage increasing rate of 200 V / s, and an arc discharge voltage A (kV) is measured when arc discharge is detected. When the insulation breakdown voltage B (kV) between the front and back surfaces is measured in accordance with IEC672-2, a ratio A / B of the arc discharge voltage A to the insulation breakdown voltage B is greater than 0.3.

[0105] (Feature 2)

[0106] The ceramic substrate according to claim 1 has a thickness in the range of 0.2 mm to 3 mm.

[0107] (Feature 3)

[0108] The ceramic substrate according to claim 1 or 2, wherein in any cross section, there is an area of ​​less than 1 μm 2 The number of the first voids is within a range of 30 to 500 and the area is 1 μm 2 The number of the above second voids is within a range of 0 to 30 inclusive, and is within a region of 90 μm×120 μm.

[0109] (Feature 4)

[0110] A ceramic substrate having a thickness in the range of 0.2 mm to 3 mm, wherein in any cross section, there is a 1 μm 2 The number of the first voids is within a range of 30 to 500 and the area is 1 μm 2 The number of the above second voids is within a range of 0 to 30 inclusive, and is within a region of 90 μm×120 μm.

[0111] (Feature 5)

[0112] In the ceramic substrate according to claim 3 or 4, in the region of 90 μm×120 μm, the total area ratio of the first voids is within a range of 0.01% to 0.8%.

[0113] (Feature 6)

[0114] According to any one of claims 3 to 5, in the region of 90 μm×120 μm, the total area ratio of the second voids is within a range of 0% to 0.6%.

[0115] (Feature 7)

[0116] According to any one of claims 3 to 6, in the region of 90 μm×120 μm, the maximum diameter of the voids is 15 μm or less.

[0117] (Feature 8)

[0118] According to any one of claims 3 to 7, in the region of 90 μm×120 μm, the number of groups of the first gaps having a distance of 5 μm or less is 3 or less.

[0119] (Feature 9)

[0120] The ceramic substrate according to any one of claims 1 to 8, wherein the ceramic substrate is a silicon nitride substrate having an arc discharge voltage A of 5 kV or more.

[0121] (Feature 10)

[0122] The ceramic substrate according to any one of claims 1 to 9, wherein the ceramic substrate is a silicon nitride substrate having a thickness of 0.2 mm or more and 3 mm or less.

[0123] (Feature 11)

[0124] A ceramic circuit substrate, comprising:

[0125] The ceramic substrate according to any one of claims 1 to 10; and

[0126] The metal part is arranged on the surface of the ceramic substrate.

[0127] (Feature 12)

[0128] A semiconductor device comprising:

[0129] The ceramic circuit substrate according to claim 1; and

[0130] A semiconductor element is mounted on the metal portion.

[0131] Several embodiments of the present invention are illustrated above, but these embodiments are proposed as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the scope of the main purpose of the invention. These embodiments and their modifications are included in the scope and main purpose of the invention, and are included in the invention described in the claims and the scope of their equivalents. In addition, the above-mentioned embodiments can be implemented in combination with each other.

[0132] Description of Reference Numerals

[0133] 1…Ceramic substrate

[0134] 2… Section

[0135] 3…Area 1μm 2 The gap above

[0136] 4…area less than 1μm 2The gap

[0137] 5…Metal Department

[0138] 6…Joint layer

[0139] 10…Ceramic circuit substrate

Claims

1. A ceramic substrate, An AC voltage of 50 Hz or 60 Hz is applied between the front and back surfaces at a voltage boost rate of 200 V / s, and the arc discharge voltage A (kV) is measured when arc discharge is detected. When the insulation breakdown voltage B (kV) between the front and back surfaces is measured in accordance with IEC672-2, the ratio A / B of the arc discharge voltage A to the insulation breakdown voltage B is greater than 0.

3.

2. The ceramic substrate according to claim 1, The ceramic substrate has a thickness in a range of 0.2 mm to 3 mm.

3. The ceramic substrate according to claim 1, In any cross section, there are areas less than 1 μm 2 The number of the first voids is within a range of 30 to 500 and the area is 1 μm 2 The number of the above second voids is within a range of 0 to 30 inclusive, and is within a region of 90 μm×120 μm.

4. A ceramic substrate, The thickness is within the range of 0.2 mm to 3 mm. In any cross section, there are areas less than 1 μm 2 The number of the first voids is within a range of 30 to 500 and the area is 1 μm 2 The number of the above second voids is within a range of 0 to 30 inclusive, and is within a region of 90 μm×120 μm.

5. The ceramic substrate according to claim 3 or 4, In the region of 90 μm×120 μm, the total area ratio of the first voids is within a range of 0.01% to 0.8%.

6. The ceramic substrate according to claim 5, In the region of 90 μm×120 μm, the total area ratio of the second voids is within a range of 0% to 0.6%.

7. The ceramic substrate according to claim 6, In the region of 90 μm×120 μm, the maximum diameter of the voids was 15 μm or less.

8. The ceramic substrate according to claim 7, In the region of 90 μm×120 μm, the number of groups of the first gaps having a distance of 5 μm or less is 3 or less.

9. The ceramic substrate according to claim 1 or 4, The ceramic substrate is a silicon nitride substrate having an arc discharge voltage A of 5 kV or more.

10. The ceramic substrate according to claim 3 or 4, The ceramic substrate is a silicon nitride substrate having a thickness of 0.2 mm to 3 mm.

11. The ceramic substrate according to claim 8, The ceramic substrate is a silicon nitride substrate having a thickness of 0.2 mm to 3 mm.

12. A ceramic circuit substrate comprising: The ceramic substrate according to claim 1 or 4; and The metal part is arranged on the surface of the ceramic substrate.

13. A ceramic circuit substrate comprising: The ceramic substrate according to claim 10; and The metal part is arranged on the surface of the ceramic substrate.

14. A ceramic circuit substrate comprising: The ceramic substrate according to claim 11; and The metal part is arranged on the surface of the ceramic substrate.

15. A semiconductor device comprising: The ceramic circuit substrate according to claim 12; and The semiconductor element is mounted on the metal portion.

16. A semiconductor device comprising: The ceramic circuit substrate according to claim 13; and The semiconductor element is mounted on the metal portion.

17. A semiconductor device comprising: The ceramic circuit substrate according to claim 14; and The semiconductor element is mounted on the metal portion.

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