Multi-core heterogeneous arc monitoring chip and method based on frequency-band AD sampling

Abstract

The invention discloses a multi-core heterogeneous arc monitoring chip and method based on frequency-band AD sampling. The monitoring chip comprises a conditioning circuit, an analog front-end circuit, a processor unit, an AI intelligent diagnosis unit, a storage unit and a communication interface. The fault arc signal is amplified and filtered through the conditioning circuit; the processed fault arc signal is input to an analog front-end circuit; the analog front-end circuit is used for collecting fault arc signals of different frequency bands; the processor unit is connected with the analog front-end circuit and is used for identifying arc characteristic values of fault arc signals of different frequency bands; the AI intelligent diagnosis unit is connected with the processor unit and the analog front-end circuit, and is used for carrying out intelligent diagnosis and identification on the arc characteristic value to obtain a diagnosis result; the storage unit is connected with the analog front-end circuit, the processor unit and the AI intelligent diagnosis unit and is used for storing data in operation; and the communication interface is used for transmitting the diagnosis result to a terminal.

Description

Technical Field

[0001] The present invention relates to the technical field of power systems, and more specifically, to a multi-core heterogeneous arc monitoring chip and method based on frequency-band AD sampling. Background Art

[0002] According to statistics from the Fire and Rescue Bureau, electrical fires have been the leading cause of fire accidents for 10 consecutive years, and fault arcs account for more than 70% of the causes of electrical fires, which is one of the main culprits of electrical fires and seriously threatens the safety of people's lives and property. However, at present, my country's advanced early warning technology reserves for electrical fires are relatively weak, and fault arc monitoring has problems such as difficulty in multi-dimensional feature characterization, poor anti-interference, and inability to select and locate lines. It is urgent to strengthen independent innovation in low-voltage weak arc fault diagnosis technology. The IEC standard stipulates arc monitoring requirements for output voltage 220V and output current 3A~63A, but because the applicable system only considers a single load branch, and does not consider the collection branch and combined interference load, the equivalent GB / T31143 is only used as a transition for domestic related product testing and has not been maturely applied. The collection branch fault arc monitoring will become the mainstream of research.

[0003] my country's arc fault measurement and diagnosis technology started late, and there is an urgent need to promote the development of fault arc fire monitoring technology towards digitalization, Internet of Things, and intelligence.

[0004] At present, domestic and foreign manufacturers of arc fault monitoring devices have successively launched arc diagnostic devices and arc monitoring diagnostic chips. However, the arc diagnostic device is suitable for the diagnosis of main line fault arcs and complex environments with multiple scenarios and multiple loads, with a false alarm rate of more than 80% and a false alarm rate of more than 70%. When the load types are more than 5, the accuracy rate continues to decline. There are many problems with arc monitoring diagnostic chips, such as no intelligent recognition database, no dedicated intelligent recognition algorithm, slow recognition speed, high false alarm rate, and inability to restore high-frequency components in weak arc signals.

[0005] Therefore, how to achieve full-band arc feature extraction while ensuring fast recognition speed and low false alarm rate is a problem that needs to be solved urgently. Summary of the invention

[0006] The technical solution of the present invention provides a multi-core heterogeneous arc monitoring chip and method based on frequency-band AD sampling to solve the problem of how to monitor fault arcs under the premise of achieving full-band arc feature extraction.

[0007] In order to solve the above problems, the present invention provides a multi-core heterogeneous arc monitoring chip based on frequency-band AD sampling, characterized in that the monitoring chip comprises: a conditioning circuit, an analog front-end circuit, a processor unit, an AI intelligent diagnosis unit, a storage unit and a communication interface;

[0008] The fault arc signal is passed through the conditioning circuit to undergo signal amplification and filtering processing; the processed fault arc signal is input into the analog front-end circuit;

[0009] The analog front-end circuit is used to collect the fault arc signals in different frequency bands;

[0010] The processor unit is connected to the analog front-end circuit and is used to identify arc characteristic values ​​of the fault arc signals in different frequency bands;

[0011] The AI ​​intelligent diagnosis unit is connected to the processor unit and the analog front-end circuit, and is used to perform intelligent diagnosis and identification on the arc characteristic value to obtain a diagnosis result;

[0012] The storage unit is connected to the analog front-end circuit, the processor unit and the AI ​​intelligent diagnosis unit, and is used to store running data;

[0013] The communication interface is used to transmit the diagnosis result to the terminal.

[0014] Preferably, the monitoring chip includes: a power module, and the power module is used to supply power to the conditioning circuit, the analog front-end circuit, the processor unit, the AI ​​intelligent diagnosis unit, the storage unit and the communication interface.

[0015] Preferably, the monitoring chip includes: a clock module, the clock module includes an oscillator and a phase-locked loop circuit, and is used to provide a clock signal for the processor unit, the AI ​​intelligent diagnosis unit, and the analog front-end circuit.

[0016] Preferably, the analog front-end circuit includes: 2 500Msps 12-bit ADCs, 4 2Msps 24-bit ADCs, an anti-aliasing filter, and a variable gain amplifier.

[0017] Preferably, the conditioning circuit comprises: an anti-aliasing filter and a variable gain amplifier.

[0018] Preferably, the AI ​​intelligent diagnosis unit includes: a sparse pulse neuron core, a pulse arithmetic unit and a data cache module.

[0019] Preferably, the processor unit integrates CPU, DSP, AI, high-performance and high-precision ADC, low-jitter high-speed clock, high-precision filter, and high-reliability power supply.

[0020] Preferably, the storage unit includes FLASH and SRAM.

[0021] Preferably, the communication interface supports I2C protocol, SPI protocol, and UART universal serial port.

[0022] Based on another aspect of the present invention, the present invention provides a method for performing fault arc monitoring using a multi-core heterogeneous arc monitoring chip based on frequency band AD sampling, characterized in that the method comprises:

[0023] Inputting the fault arc signal into the conditioning circuit, and performing signal amplification and filtering processing through the conditioning circuit; inputting the processed fault arc signal into the analog front-end circuit;

[0024] The analog front-end circuit is used to collect the fault arc signals in different frequency bands;

[0025] Connecting a processor unit to the analog front-end circuit to identify arc characteristic values ​​of the fault arc signals in different frequency bands;

[0026] Connecting an AI intelligent diagnosis unit to the processor unit and the analog front-end circuit to perform intelligent diagnosis and identification on the arc characteristic value and obtain a diagnosis result;

[0027] Connecting a storage unit to the analog front-end circuit, the processor unit and the AI ​​intelligent diagnosis unit to store running data;

[0028] The diagnosis result is transmitted to the terminal through the communication interface.

[0029] The technical solution of the present invention provides a multi-core heterogeneous arc monitoring chip based on frequency-band AD sampling, and the monitoring chip includes: a conditioning circuit, an analog front-end circuit, a processor unit, an AI intelligent diagnosis unit, a storage unit and a communication interface; the fault arc signal is amplified and filtered after the conditioning circuit; the processed fault arc signal is input into the analog front-end circuit; the analog front-end circuit is used to collect fault arc signals of different frequency bands; the processor unit is connected to the analog front-end circuit, and is used to identify the arc characteristic values ​​of fault arc signals of different frequency bands; the AI ​​intelligent diagnosis unit is connected to the processor unit and the analog front-end circuit, and is used to perform intelligent diagnosis and identification of the arc characteristic values ​​and obtain the diagnosis results; the storage unit is connected to the analog front-end circuit, the processor unit and the AI ​​intelligent diagnosis unit, and is used to store the running data; the communication interface is used to transmit the diagnosis results to the terminal. The technical solution of the present invention improves the reliable early warning capability of low-voltage faults under the development trend of the new power distribution system, and ensures the safe, reliable and economical operation of the power grid and the safe use of electricity by users. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] A more complete understanding of exemplary embodiments of the present invention may be obtained by referring to the following drawings:

[0031] Figure 1 A structural diagram of a multi-core heterogeneous arc monitoring chip system based on frequency-band AD sampling according to a preferred embodiment of the present invention;

[0032] Figure 2 Schematic diagram of the overall architecture of a multi-core heterogeneous arc monitoring chip according to a preferred embodiment of the present invention;

[0033] Figure 3 A schematic diagram of a low-voltage broadband fault arc signal conditioning circuit according to a preferred embodiment of the present invention;

[0034] Figure 4 A schematic diagram of the structure of a successive approximation-pipeline hybrid ADC according to a preferred embodiment of the present invention;

[0035] Figure 5 A schematic diagram of the structure of a noise shaping oversampling ADC according to a preferred embodiment of the present invention;

[0036] Figure 6 A schematic diagram of the architecture of a low-jitter charge pump phase-locked loop according to a preferred embodiment of the present invention; and

[0037] Figure 7 The present invention is a flow chart of a monitoring method for a multi-core heterogeneous arc monitoring chip based on frequency-band AD sampling according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0038] Now, exemplary embodiments of the present invention are described with reference to the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to disclose the present invention in detail and completely and to fully convey the scope of the present invention to those skilled in the art. The terms used in the exemplary embodiments shown in the accompanying drawings are not intended to limit the present invention. In the accompanying drawings, the same units / elements are marked with the same reference numerals.

[0039] Unless otherwise specified, the terms (including technical terms) used herein have the commonly understood meanings to those skilled in the art. In addition, it is understood that the terms defined in commonly used dictionaries should be understood to have the same meanings as those in the context of the relevant fields, and should not be understood as idealized or overly formal meanings.

[0040] Figure 1 A structural diagram of a multi-core heterogeneous arc monitoring chip system based on frequency-band AD sampling according to a preferred embodiment of the present invention;

[0041] The present invention provides a multi-core heterogeneous arc monitoring chip based on frequency-band AD sampling, which aims to solve the problems of large background noise, wide fault arc frequency range, difficult arc feature extraction, and excessive noise reducing the minimum signal that can be resolved by ADC in low-voltage source-load systems, improve the reliable early warning capability of low-voltage faults under the development trend of new power distribution and utilization systems, and ensure safe, reliable and economical operation of power grids and safe use of electricity by users.

[0042] like Figure 1 As shown, the present invention provides a multi-core heterogeneous arc monitoring chip based on frequency-band AD sampling, the monitoring chip comprising: a conditioning circuit, an analog front-end circuit, a processor unit, an AI intelligent diagnosis unit, a storage unit and a communication interface;

[0043] The present invention provides a multi-core heterogeneous arc monitoring chip based on frequency band AD sampling, such as Figure 2 As shown in the figure, the arc monitoring chip completes the fault arc signal acquisition through high-performance and high-precision ADC. The converted data is processed in the time-frequency domain by DSP to obtain the full-band arc characteristics. The AI ​​intelligent diagnosis unit performs intelligent identification on it, and finally transmits the decision information to single-phase and three-phase electricity meters and other terminals through communication interfaces such as SPI, UART, and I2C.

[0044] The multi-core heterogeneous arc monitoring chip of the present invention mainly includes the following parts: a clock module, a power module, a high-performance and high-precision analog front-end circuit, a CPU+DSP heterogeneous processor unit, an AI intelligent diagnosis unit, a storage unit and a communication interface.

[0045] The fault arc signal is amplified and filtered by the conditioning circuit; the processed fault arc signal is input to the analog front-end circuit;

[0046] The analog front-end circuit is used to collect fault arc signals in different frequency bands;

[0047] The processor unit is connected to the analog front-end circuit and is used to identify arc characteristic values ​​of fault arc signals in different frequency bands;

[0048] The AI ​​intelligent diagnosis unit is connected to the processor unit and the analog front-end circuit to perform intelligent diagnosis and identification of arc characteristic values ​​and obtain diagnosis results;

[0049] The storage unit is connected to the analog front-end circuit, the processor unit and the AI ​​intelligent diagnosis unit, and is used to store the running data;

[0050] The communication interface is used to transmit the diagnosis result to the terminal.

[0051] Preferably, the monitoring chip includes: a power module, which is used to supply power to a conditioning circuit, an analog front-end circuit, a processor unit, an AI intelligent diagnosis unit, a storage unit and a communication interface.

[0052] The power supply module of the monitoring chip of the present invention comprises LDO, POR, LVD and other circuits, which are respectively connected to the processor unit, digital signal processor unit, intelligent diagnosis unit and analog front end, and are used for powering the inside of the chip, and can power the analog circuit, digital circuit and memory inside the chip.

[0053] Preferably, the monitoring chip includes: a clock module, the clock module includes an oscillator and a phase-locked loop circuit, and is used to provide a clock signal for the processor unit, the AI ​​intelligent diagnosis unit, and the analog front-end circuit.

[0054] The clock module of the monitoring chip of the present invention comprises an oscillator, a phase-locked loop and other circuits, is connected with a processor unit, a digital signal processor unit, an intelligent diagnosis unit and an analog front end, and is used to generate a clock signal inside the chip.

[0055] Preferably, the analog front-end circuit includes: 2 500Msps 12-bit ADCs, 4 2Msps 24-bit ADCs, an anti-aliasing filter, and a variable gain amplifier.

[0056] The high-performance and high-precision analog front-end circuit of the monitoring chip of the present invention includes two 500Msps12-bit ADCs, four 2Msps 24-bit ADCs, anti-aliasing filters, variable gain amplifiers and other circuits, which are connected to the CPU, DSP, and AI to collect fault arc signals in different frequency bands.

[0057] In the present invention, the fault arc signal first passes through a low-voltage broadband fault arc signal conditioning circuit, amplifies and filters the signal, and then outputs it to the ADC. Figure 3 As shown. The conditioning circuit mainly includes anti-aliasing filter and variable gain amplifier to solve the problem of high background noise in low-voltage source-load system. Based on the low-noise technology of variable gain amplifier and low input offset circuit technology, a low-noise signal amplification module is designed; based on the high linearity design technology of filters with different structures, combined with the characteristics of main interference signals and out-of-band noise, an anti-aliasing filter module is designed to filter out out-of-band interference and high-frequency noise, and improve the sampling accuracy of the subsequent ADC.

[0058] Aiming at the problem that the fault arc frequency range is wide and the arc characteristics are difficult to extract, the present invention designs a multi-ADC frequency division dedicated signal acquisition unit to realize the accurate acquisition and conversion of arc fault signals. The ADC design for sampling the high frequency band components of the arc signal is realized by adopting high-performance and high-precision ADC architecture technology, successive approximation-pipeline hybrid ADC quantization principle and high-speed and high-precision inter-stage amplifier technology. Figure 4 As shown; the single-loop high-order multi-bit modulator architecture technology, the digital weighted averaging technology of the multi-bit DAC and the low-noise circuit technology are used to realize the noise shaping oversampling ADC circuit design for sampling the low-frequency components of the arc signal, as shown Figure 5 As shown. Finally, the accurate collection of fault arc signals in different frequency bands is achieved.

[0059] Preferably, the conditioning circuit includes: an anti-aliasing filter and a variable gain amplifier.

[0060] Preferably, the AI ​​intelligent diagnosis unit includes: a sparse pulse neuron core, a pulse arithmetic unit and a data cache module.

[0061] The AI ​​intelligent diagnosis unit of the monitoring chip of the present invention mainly includes a sparse pulse neuron core, a pulse arithmetic unit, and a data cache module, which are linked to the CPU, DSP, and analog front-end circuit to intelligently identify the characteristic values ​​of arcs in the entire frequency band.

[0062] Preferably, the processor unit integrates CPU, DSP, AI, high-performance and high-precision ADC, low-jitter high-speed clock, high-precision filter, and high-reliability power supply.

[0063] The CPU+DSP heterogeneous processor unit of the monitoring chip of the present invention is connected to the analog front-end circuit and the AI ​​circuit, and is used to transform the collected fault arc signal in the time-frequency domain and extract the full-band arc characteristics; the design supports on-chip storage resources, AI units and high-computing power CPU-DSP heterogeneous computing chip platforms, realizes hardware resource virtualization and dynamic balancing, improves data training throughput, and realizes hardware acceleration through data flow planning and scheduling strategies and accelerator parallel computing array architecture; based on the architecture technology of low-jitter charge pump phase-locked loop (such as Figure 6 As shown in the figure, a linear loop model including noise factors is established, and a charge pump circuit based on the combination of unity gain feedback and common mode feedback technology is designed to cause reference spurious of the system clock with a small charge pump; finally, a multi-core heterogeneous arc detection intelligent identification dedicated chip design is realized which integrates CPU, DSP, AI, high-performance and high-precision ADC, low-jitter high-speed clock, high-precision filter, high-reliability power supply and other functions.

[0064] Preferably, the storage unit includes FLASH and SRAM.

[0065] The storage unit of the monitoring chip of the present invention comprises FLASH, SRAM and other units, which are connected with CPU, DSP, AI and analog front-end circuit and are used for storing various data.

[0066] Preferably, the communication interface supports I2C protocol, SPI protocol, and UART universal serial port.

[0067] The communication interface of the monitoring chip of the present invention is used for external data communication, and the interface circuit supports protocols including I2C protocol, SPI protocol, UART universal serial port, etc.

[0068] The present invention provides a multi-core heterogeneous arc monitoring chip based on frequency-band AD sampling. It completes the acquisition of fault arc signals through high-performance and high-precision ADC. The converted data is processed in the time-frequency domain by DSP and the full-band arc characteristics are extracted. The AI ​​unit performs intelligent identification on it and finally transmits the decision information to single-phase and three-phase electric energy meters and other terminals through SPI, UART, I2C and other communication interfaces. It improves the reliable early warning capability of low-voltage faults under the development trend of new power distribution and utilization systems, and ensures the safe, reliable and economical operation of the power grid and the safe use of electricity by users.

[0069] like Figure 2 As shown in the figure, the multi-core heterogeneous arc monitoring chip mainly includes the following parts: clock module, power module, high-performance and high-precision analog front-end circuit, CPU+DSP heterogeneous processor unit, AI intelligent diagnosis unit, storage unit and communication interface.

[0070] The clock module of the present invention includes an oscillator, a phase-locked loop and other circuits, which are connected to a processor unit, a digital signal processor unit, an intelligent diagnosis unit and an analog front end, and are used to generate a clock signal inside the chip;

[0071] The power module of the present invention comprises LDO, POR, LVD and other circuits, which are respectively connected to the processor unit, the digital signal processor unit, the intelligent diagnosis unit and the analog front end, and are used to supply power to the inside of the chip, and can supply power to the analog circuit, digital circuit and memory inside the chip;

[0072] The high-performance and high-precision analog front-end circuit of the present invention includes two 500Msps 12-bit ADCs, four 2Msps 24-bit ADCs, anti-aliasing filters, variable gain amplifiers and other circuits, which are connected to the CPU, DSP and AI to collect fault arc signals in different frequency bands.

[0073] In the present invention, the fault arc signal first passes through a low-voltage broadband fault arc signal conditioning circuit, amplifies and filters the signal, and then outputs it to the ADC. Figure 3As shown. The conditioning circuit mainly includes anti-aliasing filter and variable gain amplifier to solve the problem of high background noise in low-voltage source-load system. Based on the low-noise technology of variable gain amplifier and low input offset circuit technology, a low-noise signal amplification module is designed; based on the high linearity design technology of filters with different structures, combined with the characteristics of main interference signals and out-of-band noise, an anti-aliasing filter module is designed to filter out out-of-band interference and high-frequency noise, and improve the sampling accuracy of the subsequent ADC.

[0074] Aiming at the problem that the fault arc frequency range is wide and the arc characteristics are difficult to extract, the present invention designs a multi-ADC frequency division dedicated signal acquisition unit to realize the accurate acquisition and conversion of arc fault signals. The ADC design for sampling the high frequency band components of the arc signal is realized by adopting high-performance and high-precision ADC architecture technology, successive approximation-pipeline hybrid ADC quantization principle and high-speed and high-precision inter-stage amplifier technology. Figure 4 As shown; the single-loop high-order multi-bit modulator architecture technology, the digital weighted averaging technology of the multi-bit DAC and the low-noise circuit technology are used to realize the noise shaping oversampling ADC circuit design for sampling the low-frequency components of the arc signal, as shown Figure 5 As shown. Finally, the accurate collection of fault arc signals in different frequency bands is achieved.

[0075] The AI ​​intelligent diagnosis unit in the present invention includes a sparse pulse neuron core, a pulse arithmetic unit, and a data cache module, which are linked to a CPU, a DSP, and an analog front-end circuit for intelligently identifying arc characteristic values ​​across the entire frequency band.

[0076] The CPU+DSP heterogeneous processor unit in the present invention is connected to the analog front-end circuit and the AI ​​circuit, and is used to transform the collected fault arc signal in the time-frequency domain and extract the full-band arc characteristics; the design supports on-chip storage resources, AI units and high-computing power CPU-DSP heterogeneous computing chip platforms, realizes hardware resource virtualization and dynamic balancing, improves data training throughput, and realizes hardware acceleration through data flow planning and scheduling strategies and accelerator parallel computing array architecture; based on the architecture technology of low-jitter charge pump phase-locked loop (such as Figure 6 As shown in the figure, a linear loop model including noise factors is established, and a charge pump circuit based on the combination of unity gain feedback and common mode feedback technology is designed to reduce the reference spurious of the system clock caused by a small charge pump; a multi-core heterogeneous arc detection intelligent identification dedicated chip design is realized that integrates CPU, DSP, AI, high-performance and high-precision ADC, low-jitter high-speed clock, high-precision filter, high-reliability power supply and other functions.

[0077] The storage unit in the present invention includes FLASH, SRAM and other units, which are connected with CPU, DSP, AI and analog front-end circuits to store various data.

[0078] The communication interface in the present invention is used for external data communication, and the interface circuit supports protocols including I2C protocol, SPI protocol, UART universal serial port, etc.

[0079] Figure 7 The present invention is a flow chart of a monitoring method for a multi-core heterogeneous arc monitoring chip based on frequency-band AD sampling according to a preferred embodiment of the present invention.

[0080] like Figure 7 As shown, the present invention provides a method for fault arc monitoring using a multi-core heterogeneous arc monitoring chip based on frequency band AD sampling, characterized in that the method comprises:

[0081] Step 701: inputting the fault arc signal into a conditioning circuit, performing signal amplification and filtering processing through the conditioning circuit; inputting the processed fault arc signal into an analog front-end circuit;

[0082] Step 702: collecting arc fault signals of different frequency bands through an analog front-end circuit;

[0083] Step 703: connecting the processor unit to the analog front-end circuit to identify arc characteristic values ​​of fault arc signals in different frequency bands;

[0084] Step 704: connecting the AI ​​intelligent diagnosis unit to the processor unit and the analog front-end circuit to perform intelligent diagnosis and identification on the arc characteristic value and obtain the diagnosis result;

[0085] Step 705: Connecting a storage unit to the analog front-end circuit, the processor unit, and the AI ​​intelligent diagnosis unit to store running data;

[0086] Step 706: Transmit the diagnosis result to the terminal via the communication interface.

[0087] Preferably, the monitoring chip includes: a power module, which is used to supply power to a conditioning circuit, an analog front-end circuit, a processor unit, an AI intelligent diagnosis unit, a storage unit and a communication interface.

[0088] Preferably, the monitoring chip includes: a clock module, the clock module includes an oscillator and a phase-locked loop circuit, and is used to provide a clock signal for the processor unit, the AI ​​intelligent diagnosis unit, and the analog front-end circuit.

[0089] Preferably, the analog front-end circuit includes: 2 500Msps 12-bit ADCs, 4 2Msps 24-bit ADCs, an anti-aliasing filter, and a variable gain amplifier.

[0090] Preferably, the conditioning circuit includes: an anti-aliasing filter and a variable gain amplifier.

[0091] Preferably, the AI ​​intelligent diagnosis unit includes: a sparse pulse neuron core, a pulse arithmetic unit and a data cache module.

[0092] Preferably, the processor unit integrates CPU, DSP, AI, high-performance and high-precision ADC, low-jitter high-speed clock, high-precision filter, and high-reliability power supply.

[0093] Preferably, the storage unit includes FLASH and SRAM.

[0094] Preferably, the communication interface supports I2C protocol, SPI protocol, and UART universal serial port.

[0095] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The schemes in the embodiments of the present invention may be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0096] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0097] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0098] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0099] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0100] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

[0101] The invention has been described above with reference to a few embodiments. However, it is readily apparent to a person skilled in the art that other embodiments than the ones disclosed above are equally within the scope of the invention, as defined by the appended patent claims.

[0102] Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a / said / the [means, components, etc.]" are to be openly interpreted as at least one instance of said means, components, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not necessarily have to be performed in the exact order disclosed, unless explicitly stated otherwise.

Claims

1. A multi-core heterogeneous arc monitoring chip based on frequency-band AD sampling, characterized in that: The monitoring chip includes: a conditioning circuit, an analog front-end circuit, a processor unit, an AI intelligent diagnosis unit, a storage unit and a communication interface; The fault arc signal is passed through the conditioning circuit to undergo signal amplification and filtering processing; the processed fault arc signal is input into the analog front-end circuit; The analog front-end circuit is used to collect the fault arc signals in different frequency bands; The processor unit is connected to the analog front-end circuit and is used to identify arc characteristic values ​​of the fault arc signals in different frequency bands; The AI ​​intelligent diagnosis unit is connected to the processor unit and the analog front-end circuit, and is used to perform intelligent diagnosis and identification on the arc characteristic value to obtain a diagnosis result; The storage unit is connected to the analog front-end circuit, the processor unit and the AI ​​intelligent diagnosis unit, and is used to store running data; The communication interface is used to transmit the diagnosis result to the terminal.

2. The monitoring chip according to claim 1, characterized in that: The monitoring chip includes: a power module, which is used to supply power to the conditioning circuit, the analog front-end circuit, the processor unit, the AI ​​intelligent diagnosis unit, the storage unit and the communication interface.

3. The monitoring chip according to claim 1, characterized in that: The monitoring chip includes: a clock module, which includes an oscillator and a phase-locked loop circuit, and is used to provide a clock signal for the processor unit, the AI ​​intelligent diagnosis unit, and the analog front-end circuit.

4. The monitoring chip according to claim 1, characterized in that: The analog front-end circuit includes: 2 500Msps12bit ADCs, 4 2Msps 24bit ADCs, an anti-aliasing filter, and a variable gain amplifier.

5. The monitoring chip according to claim 1, characterized in that: The conditioning circuit includes: an anti-aliasing filter and a variable gain amplifier.

6. The monitoring chip according to claim 1, characterized in that: The AI ​​intelligent diagnosis unit includes: a sparse pulse neuron core, a pulse arithmetic unit and a data cache module.

7. The monitoring chip according to claim 1, characterized in that: The processor unit integrates CPU, DSP, AI, high-performance and high-precision ADC, low-jitter high-speed clock, high-precision filter, and high-reliability power supply.

8. The monitoring chip according to claim 1, characterized in that: The storage unit includes FLASH and SRAM.

9. The monitoring chip according to claim 1, characterized in that: The communication interface supports I2C protocol, SPI protocol, and UART universal serial port.

10. A method for fault arc monitoring based on a multi-core heterogeneous arc monitoring chip with frequency-band AD sampling, characterized in that: The method comprises: Inputting the fault arc signal into the conditioning circuit, performing signal amplification and filtering processing through the conditioning circuit; inputting the processed fault arc signal into the analog front-end circuit; The analog front-end circuit is used to collect the fault arc signals of different frequency bands; Connecting a processor unit to the analog front-end circuit to identify arc characteristic values ​​of the fault arc signals in different frequency bands; Connecting an AI intelligent diagnosis unit to the processor unit and the analog front-end circuit to perform intelligent diagnosis and identification on the arc characteristic value and obtain a diagnosis result; Connecting a storage unit to the analog front-end circuit, the processor unit and the AI ​​intelligent diagnosis unit to store running data; The diagnosis result is transmitted to the terminal through the communication interface.

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