Memory voltage processing method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a memory voltage processing method and device, a storage medium and electronic equipment, and relates to the field of computers.The memory voltage processing method comprises the steps that based on a substrate management controller integrated on a server mainboard, first standard voltage output by a target power supply chip is obtained, the first standard voltage provides memory voltage for a group of memory modules of the server; transmitting the first standard voltage to a target operating system in response to a first triggering operation on the voltage adjusting instruction; determining N preset voltages based on the first standard voltage; based on the N preset voltages, memory performance testing is executed, a target testing result is obtained, and the target testing result comprises N performance indexes corresponding to the N preset voltages; determining a target preset voltage from the N preset voltages based on the N performance indexes; and modifying the power supply voltage output by the target power supply chip from the first standard voltage to the target preset voltage.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and more specifically, to a method and device for processing memory voltage, a storage medium, and an electronic device. Background Art

[0002] With the rapid development of cloud computing and big data technology, the information and intelligentization trend of the current society is accelerating. As the core equipment of the information system, the server has higher and higher performance requirements. Memory is one of the core components of the server system. It plays a vital role in ensuring the efficient operation, data integrity and performance of the server.

[0003] The key to memory interface design is the bus signal and power supply. In related technologies, the memory voltage of the server is usually designed to be a fixed value, for example, usually a standard value (1.2v). However, due to differences in materials from different manufacturers and deviations in manufacturing processes during memory manufacturing, there are differences between memories produced in different batches. Therefore, it is impossible to ensure that the above standard voltage value is the optimal value for adapting the memory voltage of different servers, which affects the tuning of server memory performance parameters and leads to technical problems of poor flexibility in the server memory performance tuning process.

[0004] With regard to the problem of poor flexibility in the process of server memory performance tuning in related technologies, no effective solution has been proposed so far. Summary of the invention

[0005] The embodiments of the present application provide a method and device for processing memory voltage, a storage medium, and an electronic device to at least solve the problem of poor flexibility that occurs during server memory performance tuning.

[0006] According to an embodiment of the present application, a method for processing memory voltage is provided, comprising: based on a baseboard management controller integrated on a server motherboard, obtaining a first standard voltage output by a target power chip, wherein the first standard voltage provides memory voltage for a group of memory modules of the server; in response to a first trigger operation on a voltage adjustment instruction, transmitting the first standard voltage to the target operating system; based on the first standard voltage, determining N preset voltages, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1; based on the N preset voltages, performing a memory performance test to obtain a target test result, wherein the target test result includes N performance indicators corresponding to the N preset voltages; based on the N performance indicators, determining a target preset voltage from the N preset voltages; and modifying the power voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0007] In an exemplary embodiment, the above-mentioned determination of N preset voltages based on the first standard voltage includes: based on the voltage difference, sequentially determining n preset voltages smaller than the first standard voltage, wherein n is a positive integer greater than or equal to 1 and less than or equal to N; based on the voltage difference, sequentially determining m preset voltages greater than the first standard power supply, wherein m is a positive integer greater than or equal to 1 and less than or equal to N, and the sum of n and m is equal to N; and determining the n preset voltages and the m preset voltages as the N preset voltages.

[0008] In an exemplary embodiment, the above-mentioned memory performance test is performed based on the N preset voltages to obtain the target test result, including: performing the following processing on the i-th preset voltage among the N preset voltages to obtain the i-th performance indicator, where i is a positive integer greater than or equal to 1 and less than or equal to N: based on the i-th preset voltage, performing M memory performance tests to obtain M test data, where M is a positive integer greater than or equal to 1; performing an averaging operation on the M test data to obtain the i-th performance indicator, wherein the target test result includes the i-th performance indicator.

[0009] In an exemplary embodiment, the target preset voltage is determined from the N preset voltages based on the N performance indicators, including: arranging the N performance indicators in ascending order according to the values ​​of the performance indicators to obtain a target sorting result; based on the target sorting result, determining the target performance indicator with the highest ranking from the N performance indicators; and determining a preset voltage corresponding to the target performance indicator as the target preset voltage.

[0010] In an exemplary embodiment, the above-mentioned modification of the power voltage output by the target power chip from the first standard voltage to the target preset voltage includes: sending the target preset voltage to the target power chip through the baseboard management controller; generating a target control signal in response to the received target preset voltage, wherein the target control signal represents a control logic for modifying a register of the target power chip based on the target preset voltage; based on the control logic, modifying specific bits of the register to obtain modified register status information; based on the modified register status information, adjusting the first standard voltage output by the target power chip to the target preset voltage.

[0011] In an exemplary embodiment, the baseboard management controller integrated on the server motherboard obtains the first standard voltage output by the target power chip, including: starting the target power chip in response to configuring the general input and output signal pins to a high level; reading the current register status information of the target power chip based on the target serial interface of the baseboard management controller, wherein the current register status information represents the encoding information of the power voltage output by the target power chip; and converting the encoding information of the power voltage into the first standard voltage.

[0012] In an exemplary embodiment, the transmitting the first standard voltage to the target operating system in response to the first trigger operation of the voltage adjustment instruction includes: generating the voltage adjustment instruction when the target memory module is connected to the server motherboard for the first time; transmitting the first standard voltage to the target operating system in response to the first trigger operation of the voltage adjustment instruction; or obtaining the first memory model of the first memory module inserted in the target memory slot connected to the memory controller on the server motherboard; generating the voltage adjustment instruction when it is detected that the memory model of the memory module inserted in the target memory slot is changed from the first memory model to the second memory model, wherein the second memory model is the memory model of the second memory module; transmitting the first standard voltage to the target operating system in response to the first trigger operation of the voltage adjustment instruction; or generating the voltage adjustment instruction in response to the second trigger operation of the memory performance tuning control when a memory performance tuning control is configured on the management interface of the baseboard manager; obtaining the first standard voltage of a group of memory modules inserted in a pre-selected group of memory slots in response to the first trigger operation of the voltage adjustment instruction, and transmitting the first standard voltage to the target operating system.

[0013] According to another embodiment of the embodiment of the present application, a memory voltage processing device is also provided, including: a first acquisition unit, used to acquire a first standard voltage output by a target power chip based on a baseboard management controller integrated on a server motherboard, wherein the first standard voltage provides a memory voltage for a group of memory modules of the server; a transmission unit, used to transmit the first standard voltage to the target operating system in response to a first trigger operation on a voltage adjustment instruction; a first processing unit, used to determine N preset voltages based on the first standard voltage, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1; a second processing unit, used to perform a memory performance test based on the N preset voltages to obtain a target test result, wherein the target test result includes N performance indicators corresponding to the N preset voltages; a third processing unit, used to determine a target preset voltage from the N preset voltages based on the N performance indicators; and a fourth processing unit, used to modify the power voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0014] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0015] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0016] According to another embodiment of the present application, a computer program product is provided. The computer program product includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0017] By adopting the above embodiment provided by the present application, the first standard power output by the target power chip on the server motherboard is obtained through the baseboard management controller, and the memory performance under N preset voltages is tested based on the first standard power in the target operating system, and the optimal voltage value (target preset voltage) corresponding to the current motherboard is determined by comparing the memory performance indicators under different preset power supplies, so as to modify the power voltage output by the target power chip to the target preset voltage. In other words, the embodiment of the present application intelligently performs memory performance tests of N preset voltages based on the first standard voltage obtained, and then dynamically determines the optimal voltage value for each server memory based on the test results, thereby achieving the technical effect of improving the flexibility of memory tuning. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 It is a hardware structure block diagram of a server device according to a memory voltage processing method of an embodiment of the present application;

[0020] Figure 2 is a flow chart of an optional memory voltage processing method according to an embodiment of the present application;

[0021] Figure 3 is a schematic diagram of an optional process of obtaining a standard voltage according to an embodiment of the present application;

[0022] Figure 4 is a flowchart of an optional memory performance tuning according to an embodiment of the present application;

[0023] Figure 5 is a structural block diagram of a verification device for a soft decoding function according to an embodiment of the present application;

[0024] Figure 6 It is a schematic diagram of the structure of an optional electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0027] The memory voltage processing method provided in the embodiment of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 1 is a hardware structure block diagram of a server device of a memory voltage processing method according to an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1 The server device includes a processor 102 (only one is shown) (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the server device may also include a transmission device 106 and an input / output device 108 for communication functions. A person skilled in the art can understand that Figure 1The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0028] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for processing memory voltage in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0029] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0030] In order to better understand the above-mentioned memory voltage processing method, the following first briefly introduces the baseboard management controller (BMC), power chip (also understood as VR chip), memory (also understood as memory stick) and other components integrated on the server motherboard in the embodiment of the present application, and explains the interaction process between the various components.

[0031] like Figure 3 As shown, each server motherboard integrates CPLD (Complex Programmable Logic Device), BMC (Baseboard Management Controller), memory VR and multiple memory sticks.

[0032] Among them, the output voltage of the VR chip (which can also be understood as a power chip) can be but is not limited to providing power supply voltage for a group of memories, that is, memory voltage; complex programmable logic devices are used to implement specific digital logic functions, such as timing control, logic function control, performance optimization, hardware monitoring and management, etc. CPLD is mainly responsible for the power timing control of the motherboard, and controls the on or off state of the memory VR chip by controlling the GPIO (general input and output) pin to output high and low levels; the baseboard management controller is one of the key components in server hardware. It is an embedded controller whose function is to monitor and manage the hardware status of the server to ensure the normal operation of the hardware.

[0033] In order to solve the above problems existing in the related art, a method for processing memory voltage is provided in this embodiment, and its execution subjects include but are not limited to the client and the server motherboard, such as Figure 2 As shown, the process includes the following steps S202-S212:

[0034] Step S202: Based on a baseboard management controller integrated on a server mainboard, a first standard voltage output by a target power chip is obtained, wherein the first standard voltage provides a memory voltage for a group of memory modules of the server;

[0035] Step S204: in response to a first trigger operation on the voltage adjustment instruction, transmitting the first standard voltage to the target operating system;

[0036] Step S206: determining N preset voltages based on the first standard voltage, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1;

[0037] Step S208: performing a memory performance test based on the N preset voltages to obtain a target test result, wherein the target test result includes N performance indicators corresponding to the N preset voltages;

[0038] Step S210, determining a target preset voltage from the N preset voltages based on the N performance indicators;

[0039] Step S212, modifying the power voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0040] like Figure 3 As shown, by connecting the I2C communication protocol of the baseboard management controller to the memory VR chip, the power supply voltage output by the target power chip can be read through the baseboard management controller after the server is turned on, wherein the power supply voltage output by the target power chip is the currently set standard voltage (or standard voltage value), for example 1.2v.

[0041] I2C (Inter-Integrated Circuit) is a serial communication protocol used for inter-device communication on the server motherboard. I2C allows multiple devices to communicate with one or more hosts through a bunch of shared serial lines. This communication method can be used to monitor and control hardware status, such as temperature, voltage, fan speed, etc.

[0042] It should be noted that, in this embodiment, the baseboard management controller communicates with other chips or devices on the server motherboard through I2C to monitor and manage the hardware. This communication method is crucial to ensure the stable operation of the server and respond to hardware problems in a timely manner.

[0043] For ease of understanding, in the embodiment of the present application, the power supply of the server memory is based on the current mainstream DDR4 memory as an example. There are three power supply voltages (VDDQ, VPP, VTT: 1 / 2VDDQ), among which the voltage range of VDDQ is generally 1.16V-1.26V, and the standard voltage is 1.2V. The voltage range of VPP is generally 2.14V-2.75V, and the standard voltage is 2.5V. The materials of different memory manufacturers will be slightly different.

[0044] like Figure 3 As shown, taking a single-channel motherboard as an example, one CPU can support the installation of 16 memory sticks, among which every 8 memory sticks share a set of power supply. The VR commonly used in the current DDR4 platform is the 2Loop (4+1) solution. The voltage values ​​of VPP and VDDQ can be adjusted separately through the I2C bus. The VTT voltage is 1 / 2 of VDDQ and does not need to be adjusted separately.

[0045] That is to say, in the embodiment of the present application, the power supply voltage output by a VR chip is used as the adjustment object to adjust the memory voltage of a group (8*DDR4) of memory or a group of memory modules. For example, the power supply voltage output by the memory VR1 provides memory voltage for 8 memory sticks.

[0046] When it is determined that the first standard voltage output by the target power chip needs to be adjusted or optimized, the first standard voltage output by the target power chip is transmitted to the target operating system through the baseboard management controller, and the memory performance test is performed in the operating system. The target operating system may be, but is not limited to, an operating system installed on the target client. Whether the first standard voltage output by the target power chip needs to be adjusted will be explained below in conjunction with a specific embodiment.

[0047] The basic process of memory performance test is: according to the first standard voltage obtained, N preset voltages are set manually, for example, according to the preset voltage difference of 5mv or 10mv, N preset voltages are set, and memory performance test is performed for each of the N preset voltages to obtain corresponding test data. Finally, according to the test data, the target preset voltage that can make the performance of the current group of memory or a group of memory modules reach the best is determined from the N preset voltages.

[0048] The target preset voltage determined by the memory performance test is sent to the target power chip through the baseboard management controller, and the voltage output by the target power chip is modified from the current first standard voltage to the target preset voltage.

[0049] For example, assuming that the first standard voltage output by the target power chip read by the baseboard management controller is 1.2v, the four preset voltages are manually set to 1.18v, 1.19v, 1.21v and 1.22v, and then the performance indicators corresponding to the 44 preset voltages are determined to be C1, C2, C3 and C4 through memory performance testing. Based on C1, C2, C3 and C4, 1.21v is determined as the target preset voltage.

[0050] The target preset voltage is sent to the target power chip through the baseboard management controller, and the first standard voltage output by the target power chip is modified so that the voltage output by the target power chip is the target preset voltage, thereby making the power voltage provided for a group of memories the target preset voltage.

[0051] In actual application scenarios, servers allow voltage fluctuations within a certain range to adapt to different working conditions or perform performance tuning. For example, some servers may allow memory voltage to be adjusted within a certain range to optimize performance or reduce power consumption. The embodiment of the present application is based on this point. The first standard voltage output by the target power chip is read by the baseboard management controller and transmitted to the target operating system, and the performance indicators under different preset voltages are obtained through a pre-configured memory performance test system, thereby determining the optimal memory voltage.

[0052] In the above manner, the first standard power output by the target power chip on the server motherboard is obtained through the baseboard management controller, and the memory performance under N preset voltages is tested based on the first standard power in the target operating system, and the optimal voltage value (target preset voltage) corresponding to the current motherboard is determined by comparing the memory performance indicators under different preset power supplies, so as to modify the power voltage output by the target power chip to the target preset voltage. In other words, the embodiment of the present application intelligently performs memory performance tests of N preset voltages based on the obtained first standard voltage, and then dynamically determines the optimal voltage value for each server memory based on the test results, thereby achieving the technical effect of improving the flexibility of memory tuning.

[0053] In an exemplary embodiment, determining N preset voltages based on the first standard voltage includes:

[0054] Based on the voltage difference, sequentially determining n preset voltages that are smaller than the first standard voltage, wherein n is a positive integer greater than or equal to 1 and less than or equal to N;

[0055] Based on the voltage difference, sequentially determine m preset voltages greater than the first standard power supply, wherein m is a positive integer greater than or equal to 1 and less than or equal to N, and the sum of n and m is equal to N;

[0056] The n preset voltages and the m preset voltages are determined as the N preset voltages.

[0057] Assuming that the first standard voltage is 1.2v, the voltage difference needs to be determined according to the parameters of the power chip itself, for example, 5mv or 10mv. According to the determined voltage difference, N preset voltages are manually set, for example, n preset voltages larger than the first standard voltage, for example, 1.21v and 1.22v, and m preset voltages smaller than the first standard voltage, for example, 1.18v, 1.19v, etc.

[0058] A memory performance test is performed in the target operating system for each preset voltage in turn to obtain a performance indicator corresponding to each preset voltage, thereby determining a target preset voltage.

[0059] In other words, through the command interaction between the baseboard management controller and the target power chip, real-time monitoring of the memory voltage can be achieved, ensuring the optimization of memory performance and ensuring the stable operation of the server.

[0060] In an exemplary embodiment, the memory performance test is performed based on the N preset voltages to obtain a target test result, including:

[0061] The following processing is performed on the i-th preset voltage among the N preset voltages to obtain the i-th performance indicator, where i is a positive integer greater than or equal to 1 and less than or equal to N:

[0062] Based on the i-th preset voltage, perform M memory performance tests to obtain M test data, where M is a positive integer greater than or equal to 1;

[0063] An averaging operation is performed on the M test data to obtain the i-th performance indicator, wherein the target test result includes the i-th performance indicator.

[0064] That is, for each preset voltage, M memory performance tests are performed respectively, and the M performance test data are averaged. The server memory performance test includes but is not limited to the following aspects:

[0065] (1) Memory bandwidth test: Tests the data transfer rate of the memory, that is, how much data the memory can process per second;

[0066] (2) Read and write response test: Use attacks such as stream to test the read and write speed and response time of the memory;

[0067] (3) Memory latency test: tests the latency of memory access, that is, the time from issuing a memory access request to receiving a response;

[0068] (4) Memory capacity test: evaluate the maximum memory capacity that the server can support;

[0069] (5) Memory stability test: Run memory-intensive tasks for a long time to ensure that the memory remains stable under high load;

[0070] (6) Error rate test: Test the probability of memory errors during long-term operation;

[0071] (7) Concurrent user testing: Simulate multiple users accessing the server at the same time to test the performance under high memory concurrency conditions.

[0072] That is, for each preset voltage, the memory performance test is performed M times to obtain the test data of the above multiple aspects, and then the test data of the multiple aspects are weighted averaged to obtain a performance indicator X1 corresponding to the current preset voltage.

[0073] Through multiple performance tests, the impact of memory voltage on performance can be more comprehensively evaluated, and the accuracy and reliability of memory tuning results can be improved. Especially in the deep tuning stage of the server, the optimal value of memory voltage can be determined through the analysis of the above M test data to meet the needs of high-performance computing or big data processing.

[0074] In an exemplary embodiment, the method of determining the target preset voltage from the N preset voltages based on the N performance indicators includes:

[0075] According to the values ​​of the performance indicators, the N performance indicators are arranged in ascending order to obtain the target sorting result;

[0076] Based on the target ranking result, determining the target performance indicator with the highest ranking from the N performance indicators;

[0077] A preset voltage corresponding to the target performance indicator is determined as the target preset voltage.

[0078] In this embodiment, the N performance indicators may be sorted, but not limited to, and the performance indicator X having the largest value may be determined according to the sorting result. max , and will be with X max The corresponding preset voltage is determined as the target preset voltage.

[0079] Among them, the adjustment range of the memory voltage needs to be determined according to actual needs and material support conditions, and the accuracy of the voltage adjustment depends on the parameters of the power chip (VR chip) itself.

[0080] The specific values ​​of N and M can be selected according to the accuracy and efficiency requirements of the tuning, ensuring the efficiency and accuracy of the memory tuning process and being suitable for server environments of different scales and performance requirements.

[0081] Through the above performance tests, the impact of different preset voltages on memory performance can be quantified, making it easier to find the optimal balance between performance and energy consumption, further improving the overall performance of the server or reducing energy consumption.

[0082] In an exemplary embodiment, the above-mentioned modifying the power voltage output by the target power chip from the first standard voltage to the target preset voltage includes:

[0083] Sending the target preset voltage to the target power chip via the baseboard management controller;

[0084] generating a target control signal in response to the received target preset voltage, wherein the target control signal represents a control logic for modifying a register of the target power chip based on the target preset voltage;

[0085] Based on the control logic, modify a specific bit of the register to obtain modified register state information;

[0086] Based on the modified register state information, the first standard voltage output by the target power chip is adjusted to the target preset voltage.

[0087] Specifically, after the target preset voltage determined after the target operating system test is sent to the target power chip on the server mainboard through the baseboard management controller, the first standard voltage output by the target power chip is modified to the target preset voltage by modifying the value of the status bit of the register of the target power chip as follows:

[0088] S11, determine the target register;

[0089] First, identify the specific registers that control the voltage outputs, usually by consulting the VR chip's data sheet or technical documentation.

[0090] S12, read the current configuration;

[0091] Through interfaces such as I2C or PMBus, read the current register value to obtain the current voltage setting;

[0092] Among them, the registers of the memory VR chip usually refer to the storage components inside the memory VR chip, which are used to store various parameters and status information for controlling memory operations.

[0093] S13, determining how to achieve the control logic of the voltage change through register setting according to the target preset voltage to be adjusted;

[0094] The register stores an 8-bit binary value, and generates a control signal through the control logic. The control signal is used to indicate the type of modification operation, including but not limited to setting, clearing or flipping a specific bit, etc. According to the control signal, the specific bit in the register is modified while the values ​​of other bits are not changed.

[0095] S14, write configuration pins or programs;

[0096] Write a script or program to modify the value of the register (at least some of the 8 bits) to modify the value of specific bits in the register.

[0097] S15, sending a command through the programming interface to update the value of the register;

[0098] It mainly involves the communication protocol with the VR chip, such as I2C or PMBus.

[0099] S16, verifying and changing the changed register value;

[0100] After changing the register value, it is necessary to verify that the voltage output is as expected, which can be done, but is not limited to, by reading the value of the register or using an external voltage measurement device.

[0101] S17, monitor and adjust.

[0102] After changing voltage, monitor system stability and performance and make further adjustments if necessary.

[0103] Finally, according to the modified register value, the current first standard voltage is adaptively modified to the target preset voltage, for example, from 1.2v to 1.21v.

[0104] Through the collaborative work between the above-mentioned baseboard management controller, target power chip and other components, the automation procedure of memory performance tuning is improved, and the flexibility and efficiency of memory tuning are enhanced.

[0105] In an exemplary embodiment, the baseboard management controller integrated on the server mainboard is used to obtain the first standard voltage output by the target power chip, including:

[0106] In response to configuring the general input / output signal pin to a high level, starting the target power chip;

[0107] Based on the target serial interface of the baseboard management controller, read the current register state information of the target power chip, wherein the current register state information represents the encoding information of the power voltage output by the target power chip;

[0108] The encoded information of the power supply voltage is converted into the first standard voltage.

[0109] After the server motherboard is turned on, the CPLD is responsible for the power timing control of the motherboard. By controlling the GPIO output high level, the memory VR chip (target power chip) is turned on. After the server is turned on, the register status of the memory VR chip is read through the I2C interface of the baseboard management controller, and the current set voltage value is obtained based on the read register status.

[0110] The specific steps are as follows:

[0111] (1) Reading register values: First, the register values ​​related to voltage output in the VR chip need to be read through an appropriate interface (such as I2C, SPI, PMBus, etc.);

[0112] (2) Decoding register values: The values ​​in the registers usually contain encoded information about the voltage settings. This requires referring to the VR chip's data sheet to understand how to convert the encoded values ​​into actual voltage values. For example, some registers may directly contain a digital representation of the voltage value, while other registers may contain control bits for the voltage settings.

[0113] (3) Calculate voltage: Calculate the corresponding voltage value based on the register value and the information in the data sheet.

[0114] By connecting the baseboard management controller and the target power chip through I2C, and through the communication between the baseboard management controller and the target power chip, the memory voltage can be monitored in real time. In addition, by outputting the voltage set in the FW file, the accuracy and consistency of the memory voltage are ensured. Especially when the server hardware is upgraded or the memory is replaced, it can quickly adapt to the voltage requirements of the new memory to ensure the stable operation of the server.

[0115] In an exemplary embodiment, in response to the first trigger operation of the voltage adjustment instruction, transmitting the first standard voltage to the target operating system includes:

[0116] When the target memory module is connected to the server mainboard for the first time, generating the voltage adjustment instruction;

[0117] In response to the first triggering operation on the voltage adjustment instruction, transmitting the first standard voltage to the target operating system; or

[0118] Obtain a first memory model of a first memory module inserted into a target memory slot connected to a memory controller on a mainboard of the server;

[0119] generating the voltage adjustment instruction when it is detected that the memory model of the memory module inserted into the target memory slot is changed from the first memory model to a second memory model, wherein the second memory model is the memory model of the second memory module;

[0120] In response to the first triggering operation on the voltage adjustment instruction, transmitting the first standard voltage to the target operating system; or

[0121] In a case where a memory performance tuning control is configured on the management interface of the baseboard manager, generating the voltage adjustment instruction in response to a second trigger operation on the memory performance tuning control;

[0122] In response to the first triggering operation of the voltage adjustment instruction, the first standard voltage of a group of memory modules inserted into a pre-selected group of memory slots is obtained, and the first standard voltage is transmitted to the target operating system.

[0123] It is easy to understand that the above memory performance tuning method is not necessary during normal operation of the server. Usually, the execution process of the above memory performance tuning is started in the following three situations.

[0124] The first method: when the memory is used for the first time in the corresponding server motherboard interface, the fixed voltage of the memory currently connected for the first time (i.e., the default standard voltage) is obtained, the above-mentioned memory performance test method is adopted, N preset voltages are set from a preset voltage range, and a performance test is performed on each preset voltage to obtain N performance indicators, and a target preset voltage that matches the memory currently used for the first time is determined based on the N performance indicators.

[0125] It should be noted that before starting the above memory performance test method, it is necessary to manually determine whether voltage adjustment is required. If it is manually determined that voltage adjustment is required, the above voltage adjustment instruction is generated, and the obtained first standard voltage is transmitted to the target operating system through the BMC.

[0126] The second type: when the memory model corresponding to the motherboard interface is changed, the above voltage adjustment instruction is generated.

[0127] After manually determining that the memory model of the motherboard interface has changed, by generating the above-mentioned voltage adjustment instruction and transmitting the instruction to the target power chip, the target power chip can transmit the real-time monitored power supply voltage to the target operating system to execute the above-mentioned memory performance test in the target operating system.

[0128] The third method: by setting a memory performance tuning button on the BMC interface and performing a trigger operation on the memory performance tuning button, the above voltage adjustment instruction is generated.

[0129] For example, you can manually select a memory operation and then perform a voltage matching action. The specific memory performance tuning process is as follows: Figure 4 As shown, including:

[0130] S402, performing parameter tuning on a group of memory in the entire machine;

[0131] S404, obtaining, through the BMC, a current set voltage output by a group of VR chips connected to the memory;

[0132] For example, Figure 3 As shown, the power supply voltage output by VR1 provides memory voltage for a group (8 memories) of memories. Through I2C, BMC reads the register of the memory VR chip and obtains the status value of the register. According to the status value of the register, the current set voltage value is determined and used as the current set voltage output by the VR chip.

[0133] S406, performing a memory performance test using the current voltage value and recording the test result;

[0134] For details, please refer to the description in the above embodiment, which will not be repeated here.

[0135] S408, taking N values ​​above and below the current voltage value, and performing M memory performance tests for each value, while recording an average value of the M memory performance tests corresponding to each value;

[0136] A value (a preset voltage) performs M memory performance tests, and the M test data are averaged to obtain a performance index. Then N values ​​correspond to N performance indexes.

[0137] S410, sorting the N performance indicators, and taking the preset voltage value corresponding to the performance indicator with the largest value as the target voltage value finally set for the memory VR chip.

[0138] Combined with the description in the above embodiment, it can be seen that the memory voltage size is adjusted in real time by BMC and combined with the memory performance test function under the system, so as to achieve the effect of tuning the memory performance of each server. The software and hardware architecture is simple and easy, highly feasible and low-cost.

[0139] Combined with the description of the above embodiments, it can be seen that compared with the prior art, the technical solution in the embodiments of the present application has at least the following beneficial effects:

[0140] (1) Through the I2C bus of the baseboard management controller, the command interaction between the baseboard management controller and the memory VR chip is realized to achieve real-time adjustment of the memory voltage;

[0141] (2) Using the memory performance test function under the target operating system, the voltage of the memory VR chip is flexibly configured through I2C to adapt to the optimal value and improve memory performance;

[0142] (3) While retaining the monitoring function of the baseboard management controller in the existing solution, a new memory performance tuning function is added. This can trigger the memory performance tuning process under necessary conditions based on actual needs and application scenarios, thereby improving product competitiveness.

[0143] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0144] In this embodiment, a memory voltage processing device is also provided to implement the above-mentioned embodiments and preferred implementation modes, which have been described and will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the modules described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0145] Figure 5 is a structural block diagram of a memory voltage processing device according to an embodiment of the present application, the device comprising:

[0146] A first acquisition unit 502 is used to acquire a first standard voltage output by a target power chip based on a baseboard management controller integrated on a server motherboard, wherein the first standard voltage provides a memory voltage for a group of memory modules of the server;

[0147] A transmission unit 504, configured to transmit the first standard voltage to the target operating system in response to a first trigger operation on the voltage adjustment instruction;

[0148] A first processing unit 506 is configured to determine N preset voltages based on the first standard voltage, wherein a voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1;

[0149] A second processing unit 508, configured to perform a memory performance test based on the N preset voltages to obtain a target test result, wherein the target test result includes N performance indicators corresponding to the N preset voltages;

[0150] A third processing unit 510 is configured to determine a target preset voltage from the N preset voltages based on the N performance indicators;

[0151] The fourth processing unit 512 is configured to modify the power voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0152] In an exemplary embodiment, the first processing unit 506 includes:

[0153] A first processing module, configured to sequentially determine n preset voltages less than the first standard voltage based on the voltage difference, wherein n is a positive integer greater than or equal to 1 and less than or equal to N;

[0154] A second processing module, configured to sequentially determine m preset voltages greater than the first standard power source based on the voltage difference, wherein m is a positive integer greater than or equal to 1 and less than or equal to N, and a sum of n and m is equal to N;

[0155] The third processing module is used to determine the n preset voltages and the m preset voltages as the N preset voltages.

[0156] In an exemplary embodiment, the second processing unit 508 includes:

[0157] The fourth processing module is used to perform the following processing on the i-th preset voltage among the N preset voltages to obtain the i-th performance indicator, where i is a positive integer greater than or equal to 1 and less than or equal to N:

[0158] Based on the i-th preset voltage, perform M memory performance tests to obtain M test data, where M is a positive integer greater than or equal to 1;

[0159] An averaging operation is performed on the M test data to obtain the i-th performance indicator, wherein the target test result includes the i-th performance indicator.

[0160] In an exemplary embodiment, the third processing unit 510 includes:

[0161] A fifth processing module is used to arrange the N performance indicators in ascending order according to the values ​​of the performance indicators to obtain a target sorting result;

[0162] A sixth processing module, configured to determine the target performance indicator with the highest ranking from the N performance indicators based on the target ranking result;

[0163] The seventh processing module is used to determine a preset voltage corresponding to the target performance indicator as the target preset voltage.

[0164] In an exemplary embodiment, the fourth processing unit 512 includes:

[0165] A sending module, used for sending the target preset voltage to the target power chip through the baseboard management controller;

[0166] an eighth processing module, configured to generate a target control signal in response to the received target preset voltage, wherein the target control signal represents a control logic for modifying a register of the target power chip based on the target preset voltage;

[0167] A modification module, used to modify a specific bit of the register based on the control logic to obtain modified register state information;

[0168] An adjustment module is used to adjust the first standard voltage output by the target power chip to the target preset voltage based on the modified register state information.

[0169] In an exemplary embodiment, the first obtaining unit 502 includes:

[0170] A startup module, configured to start the target power chip in response to configuring the general input / output signal pin to a high level;

[0171] A reading module, configured to read the current register state information of the target power chip based on the target serial interface of the baseboard management controller, wherein the current register state information represents the coding information of the power voltage output by the target power chip;

[0172] The conversion module is used to convert the coding information of the power supply voltage into the first standard voltage.

[0173] In an exemplary embodiment, the transmission unit 504 includes:

[0174] A ninth processing module, configured to generate the voltage adjustment instruction when the target memory module is connected to the server mainboard for the first time;

[0175] In response to the first triggering operation on the voltage adjustment instruction, transmitting the first standard voltage to the target operating system; or

[0176] Obtain a first memory model of a first memory module inserted into a target memory slot connected to a memory controller on a mainboard of the server;

[0177] generating the voltage adjustment instruction when it is detected that the memory model of the memory module inserted into the target memory slot is changed from the first memory model to a second memory model, wherein the second memory model is the memory model of the second memory module;

[0178] In response to the first triggering operation on the voltage adjustment instruction, transmitting the first standard voltage to the target operating system; or

[0179] In a case where a memory performance tuning control is configured on the management interface of the baseboard manager, generating the voltage adjustment instruction in response to a second trigger operation on the memory performance tuning control;

[0180] In response to the first triggering operation of the voltage adjustment instruction, the first standard voltage of a group of memory modules inserted into a pre-selected group of memory slots is obtained, and the first standard voltage is transmitted to the target operating system.

[0181] The above device instructs to obtain the first standard power output by the target power chip on the server motherboard through the baseboard management controller, and in the target operating system, based on the first standard power, perform memory performance tests under N preset voltages, and by comparing the memory performance indicators under different preset power supplies, determine the optimal voltage value (target preset voltage) corresponding to the current motherboard, so as to modify the power voltage output by the target power chip to the target preset voltage. In other words, the embodiment of the present application intelligently performs memory performance tests of N preset voltages based on the first standard voltage obtained, and then dynamically determines the optimal voltage value for each server memory based on the test results, thereby achieving the technical effect of improving the flexibility of memory tuning.

[0182] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0183] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0184] Optionally, in this embodiment, the computer program may be configured to perform the following steps by means of the computer program:

[0185] S1, based on a baseboard management controller integrated on a server motherboard, obtaining a first standard voltage output by a target power chip, wherein the first standard voltage provides a memory voltage for a group of memory modules of the server;

[0186] S2, in response to a first trigger operation on a voltage adjustment instruction, transmitting the first standard voltage to the target operating system;

[0187] S3, determining N preset voltages based on the first standard voltage, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1;

[0188] S4, performing a memory performance test based on the N preset voltages to obtain a target test result, wherein the target test result includes N performance indicators corresponding to the N preset voltages;

[0189] S5, determining a target preset voltage from the N preset voltages based on the N performance indicators;

[0190] S6, modifying the power voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0191] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0192] The embodiment of the present application also provides an electronic device, such as Figure 6 As shown, the electronic device includes a memory 602 and a processor 604. The memory 602 stores a computer program, and the processor 604 is configured to execute the steps in any of the above method embodiments through the computer program.

[0193] Optionally, in this embodiment, the processor 604 may be configured to perform the following steps through a computer program:

[0194] S1, based on a baseboard management controller integrated on a server motherboard, obtaining a first standard voltage output by a target power chip, wherein the first standard voltage provides a memory voltage for a group of memory modules of the server;

[0195] S2, in response to a first trigger operation on a voltage adjustment instruction, transmitting the first standard voltage to the target operating system;

[0196] S3, determining N preset voltages based on the first standard voltage, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1;

[0197] S4, performing a memory performance test based on the N preset voltages to obtain a target test result, wherein the target test result includes N performance indicators corresponding to the N preset voltages;

[0198] S5, determining a target preset voltage from the N preset voltages based on the N performance indicators;

[0199] S6, modifying the power voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0200] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0201] Alternatively, a person skilled in the art may understand that: Figure 6 The structure shown is for illustration only. Figure 6The structure of the electronic device is not limited. For example, the electronic device may also include Figure 6 More or fewer components (such as network interfaces, etc.) as shown in, or with Figure 6 Different configurations shown.

[0202] Among them, the memory 602 can be used to store software programs and modules, such as the program instructions / modules corresponding to the memory voltage processing method and the memory voltage processing device in the embodiment of the present application. The processor 604 executes various functional applications and data processing by running the software programs and modules stored in the memory 602, that is, realizing the above-mentioned memory voltage processing method. The memory 602 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 602 may further include a memory remotely arranged relative to the processor 604, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. Among them, the memory 602 can be specifically, but not limited to, used to store information such as a first standard voltage, N preset voltages, and N performance indicators. As an example, such as Figure 6 As shown, the memory 602 may include, but is not limited to, the first acquisition unit 502, the transmission unit 504, the first processing unit 506, the second processing unit 508, the third processing unit 510, and the fourth processing unit 512 in the memory voltage processing device. In addition, other module units in the verification device of the soft decoding function may also be included but are not limited to the above, which will not be repeated in this example.

[0203] Optionally, the transmission device 606 is used to receive or send data via a network. Specific examples of the network may include a wired network and a wireless network. In one example, the transmission device 606 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices and routers via a network cable so as to communicate with the Internet or a local area network. In one example, the transmission device 606 is a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0204] In addition, the electronic device mentioned above further includes: a display 608; and a connection bus 610, which is used to connect various module components in the electronic device mentioned above.

[0205] In other embodiments, the electronic device may be a node in a distributed system, wherein the distributed system may be a blockchain system, and the blockchain system may be a distributed system formed by connecting the multiple nodes through network communication. Among them, the nodes may form a peer-to-peer (P2P) network, and any form of computing device, such as a server, terminal, or other electronic device, may become a node in the blockchain system by joining the peer-to-peer network.

[0206] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0207] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0208] The embodiments of the present application also provide a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any one of the above method embodiments.

[0209] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0210] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for processing memory voltage, characterized in that: include: Based on a baseboard management controller integrated on a server mainboard, obtaining a first standard voltage output by a target power chip, wherein the first standard voltage provides a memory voltage for a group of memory modules of the server; In response to a first trigger operation on a voltage adjustment instruction, transmitting the first standard voltage to the target operating system; Based on the first standard voltage, determine N preset voltages, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1; Based on the N preset voltages, a memory performance test is performed to obtain a target test result, wherein the target test result includes N performance indicators corresponding to the N preset voltages; Based on the N performance indicators, determining a target preset voltage from the N preset voltages; The power voltage output by the target power chip is modified from the first standard voltage to the target preset voltage.

2. The method according to claim 1, characterized in that The determining N preset voltages based on the first standard voltage includes: Based on the voltage difference, sequentially determining n preset voltages that are smaller than the first standard voltage, wherein n is a positive integer greater than or equal to 1 and less than or equal to N; Based on the voltage difference, sequentially determine m preset voltages greater than the first standard power supply, wherein m is a positive integer greater than or equal to 1 and less than or equal to N, and the sum of n and m is equal to N; The n preset voltages and the m preset voltages are determined as the N preset voltages.

3. The method according to claim 1, characterized in that The performing of the memory performance test based on the N preset voltages to obtain a target test result includes: The following processing is performed on the i-th preset voltage among the N preset voltages to obtain the i-th performance indicator, where i is a positive integer greater than or equal to 1 and less than or equal to N: Based on the i-th preset voltage, perform M memory performance tests to obtain M test data, where M is a positive integer greater than or equal to 1; An averaging operation is performed on the M test data to obtain the i-th performance indicator, wherein the target test result includes the i-th performance indicator.

4. The method according to claim 1, characterized in that: The determining a target preset voltage from the N preset voltages based on the N performance indicators includes: Arrange the N performance indicators in ascending order according to the values ​​of the performance indicators to obtain a target sorting result; Based on the target ranking result, determining the target performance indicator with the highest ranking from the N performance indicators; A preset voltage corresponding to the target performance indicator is determined as the target preset voltage.

5. The method according to claim 1, characterized in that: The step of modifying the power supply voltage output by the target power supply chip from the first standard voltage to the target preset voltage includes: Sending the target preset voltage to the target power chip via the baseboard management controller; generating a target control signal in response to the received target preset voltage, wherein the target control signal represents a control logic for modifying a register of the target power chip based on the target preset voltage; Based on the control logic, modify a specific bit of the register to obtain modified register state information; Based on the modified register state information, the first standard voltage output by the target power chip is adjusted to the target preset voltage.

6. The method according to claim 1, characterized in that The method of obtaining a first standard voltage output by a target power chip based on a baseboard management controller integrated on a server mainboard includes: In response to configuring the general input / output signal pin to a high level, starting the target power chip; Based on the target serial interface of the baseboard management controller, read the current register state information of the target power chip, wherein the current register state information represents the encoding information of the power voltage output by the target power chip; The encoded information of the power supply voltage is converted into the first standard voltage.

7. The method according to any one of claims 1 to 6, characterized in that The transmitting the first standard voltage to the target operating system in response to a first triggering operation on a voltage adjustment instruction comprises: When the target memory module is connected to the server mainboard for the first time, generating the voltage adjustment instruction; In response to the first triggering operation on the voltage adjustment instruction, transmitting the first standard voltage to the target operating system; or Obtain a first memory model of a first memory module inserted into a target memory slot connected to a memory controller on a mainboard of the server; generating the voltage adjustment instruction when it is detected that the memory model of the memory module inserted into the target memory slot is changed from the first memory model to a second memory model, wherein the second memory model is the memory model of the second memory module; In response to the first triggering operation on the voltage adjustment instruction, transmitting the first standard voltage to the target operating system; or In a case where a memory performance tuning control is configured on the management interface of the baseboard manager, generating the voltage adjustment instruction in response to a second trigger operation on the memory performance tuning control; In response to the first triggering operation of the voltage adjustment instruction, the first standard voltage of a group of memory modules inserted into a pre-selected group of memory slots is obtained, and the first standard voltage is transmitted to the target operating system.

8. A memory voltage processing device, characterized in that: include: A first acquisition unit, configured to acquire a first standard voltage output by a target power chip based on a baseboard management controller integrated on a server mainboard, wherein the first standard voltage provides a memory voltage for a group of memory modules of the server; a transmission unit, configured to transmit the first standard voltage to the target operating system in response to a first trigger operation on a voltage adjustment instruction; A first processing unit, configured to determine N preset voltages based on the first standard voltage, wherein a voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1; A second processing unit, configured to perform a memory performance test based on the N preset voltages to obtain a target test result, wherein the target test result includes N performance indicators corresponding to the N preset voltages; A third processing unit, configured to determine a target preset voltage from the N preset voltages based on the N performance indicators; The fourth processing unit is used to modify the power voltage output by the target power chip from the first standard voltage to the target preset voltage.

9. A computer-readable storage medium, characterized in that: The computer readable storage medium stores a computer program, wherein the computer program is executed by the processor. When executed, the steps of the method described in any one of claims 1 to 7 are implemented.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

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