Satellite-borne coarse pointing device control method and satellite-borne coarse pointing control device

Abstract

The invention discloses a control method of spaceborne coarse pointing equipment and spaceborne coarse pointing control equipment. The control method comprises the following steps: regularly comparing and refreshing key parts of a program segment; performing real-time comparison and rewriting on key control parameters of the soft core side; soft core side soft reset and system-on-chip overall reset are carried out; and performing processor local bus data interaction verification. According to the control method of the satellite-borne coarse pointing device and the satellite-borne coarse pointing control device, single event upset resisting measures are specifically taken for the soft core side and the logic side of the on-chip control system of the coarse pointing mechanism and modules which are possibly influenced by single event upset in the data transmission process; the precise, stable and safe control of the satellite-borne coarse pointing mechanism is ensured; the control equipment adopts a soft core processor on the FPGA to carry out operation, and the soft core processor realizes the replacement of the DSP and prevents the DSP from being influenced by single event upset.

Description

Technical Field

[0001] The invention relates to a control method of a satellite-borne coarse pointing device and a satellite-borne coarse pointing control device. Background Art

[0002] CPA (Coarse Pointing Assembly) is an important component of space optical communication terminals. Its main function is to achieve rapid capture and rough tracking of targets, laying the foundation for subsequent fine tracking and communication. However, the space environment is complex and harsh, especially SEU (Single Event Upset), which may cause CPA control logic errors, data loss or damage, or even system failures, affecting the reliability and stability of CPA control.

[0003] SEU is a phenomenon in electronic devices caused by high-energy particles (such as those in cosmic rays). When these particles pass through sensitive areas in integrated circuits, they can cause localized charge accumulation, which can cause unexpected changes in logic states or temporary failures in circuit functions.

[0004] At the same time, with the vigorous development of commercial aerospace, spacecraft have strict restrictions on the size, weight and cost of the equipment carried. As an important part of CPA, the miniaturization and low cost of the control system are imminent. Therefore, the development of a miniaturized and SEU-resistant on-chip control system for the satellite-borne coarse pointing mechanism is becoming more and more important and urgent.

[0005] The hardware of the existing CPA control system includes DSP (Digital Signal Processing) chips and FPGA (Field Programmable Gate Array), supplemented by specific peripheral circuits. DSP performs floating-point operations, which can achieve precise control of the coarse pointing mechanism, but it cannot guarantee the reliability and safety of the control system in harsh environments. At the same time, the combination of DSP and FPGA takes up a lot of circuit board space and is very expensive, which cannot meet the requirements of the booming commercial aerospace industry for miniaturization and low cost of onboard equipment. Summary of the invention

[0006] The purpose of the present invention is to provide a control method of a satellite-borne coarse pointing device and a satellite-borne coarse pointing control device, which have the advantages of strong single-particle upset resistance and miniaturization of the device.

[0007] To achieve the above object, the present invention provides a control method for a satellite-borne coarse pointing device, which comprises:

[0008] Regular comparison and refresh of key parts of program segments;

[0009] and / or, real-time comparison and rewriting of key control parameters on the soft core side;

[0010] and / or, soft reset on the soft core side and overall reset of the system on chip;

[0011] and / or, processor local bus data interaction verification.

[0012] Optionally, the periodic comparison and refreshing of the key parts of the program segment includes:

[0013] Store program segments in flash memory and identify key parts of the soft-core control program;

[0014] The compiler generated after the soft core control program is compiled identifies the specific address space (A1, A2, A3, A4, A5) and corresponding data (Da1, Da2, Da3, Da4, Da5) of the storage area where the key data of the program segment is located;

[0015] Storing two identical copies of the key data in a free area of ​​the flash memory;

[0016] After the program runs normally, within the first 5 seconds, two copies of Da1 data are read from the flash memory, and at the same time, data Da1 is read from the corresponding address space A1. The three copies of data are compared in pairs. If the three copies of data are the same, the execution continues; if one program in the flash memory is different from the other two, the execution continues, and the correct data is written to the logic side, and the logic side writes the data to the corresponding flash memory area; if the flash memory data is the same but different from the data read from address A1, the flash memory data is written to the A1 address; if the three copies of data are different, the coarse pointing mechanism enters the standby state;

[0017] After the program runs normally, the second 5 seconds are used to compare the Da2 data, and the third 5 seconds are used to compare the Da3 data. The key data are compared and refreshed every 25 seconds to avoid the accumulation of errors and achieve uninterrupted recovery control.

[0018] Optionally, the key parts include position reception, position calculation and loop closure.

[0019] Optionally, the real-time comparison and rewriting of the key control parameters on the soft core side specifically includes:

[0020] Determine key control parameters, including electrical phase angle;

[0021] Four key control parameters, D, D1, D2, and D3, are defined in the form of global variables, and the same value is assigned to these four numbers during initialization; wherein D is used for normal control of the coarse pointing mechanism, and D1, D2, and D3 are used for comparison;

[0022] In each control cycle, the D1, D2 and D3 are compared in pairs. If the three values ​​are equal, the D1 data is rewritten to D; if two of the values ​​are the same and one of them is different, the same value is rewritten to D; if the three values ​​compared this time are all different, the three values ​​D1, D2, and D3 are compared with D respectively. If one of them is the same, the same value is rewritten to D; if the three values ​​are all different and are also different from D, the coarse pointing mechanism is put into standby state.

[0023] Optionally, the soft core side soft reset and the overall system on chip reset specifically include:

[0024] The soft core side outputs 0xAA to the logic side through the processor local bus at the beginning of each control cycle, and outputs 0x55 to the logic side through the processor local bus after the control cycle ends. Each control cycle is 1ms; the logic side compares the received data, and if the value changes in each control cycle, the soft core side is not processed. If the value does not change for 20ms, the soft core side is reset; while resetting the soft core side, the number of resets of the soft core side is also counted. If the resets exceed 5 times in a row, the logic side immediately cuts off the output of the PWM wave and resets the entire on-chip system.

[0025] Optionally, the processor local bus data interaction verification specifically includes:

[0026] In the control process of the coarse pointing mechanism, data transmission between the soft core side and the logic side is transmitted through the processor local bus. The data bit width of the processor local bus for transmitting data is 32 bits. The data bit width is divided, and the 0th to 23rd bits store the high, medium and low bytes of the valid data to be transmitted, and the 24th to 31st bits are used to store the check byte; when the soft core side writes data to the logic side, the soft core side first adds the high, medium and low bytes of the valid data, and the obtained sum is assigned to the lower 8 bits to obtain the checksum part; after the logic side receives the data, the high, medium and low bits of the received data are summed by byte and compared with the check bits; if the comparison results are consistent, the logic side adopts the data, if the comparison results are inconsistent, the data is discarded and the soft core side is notified to rewrite the data; when the data on the logic side needs to be transmitted, the high, medium and low bytes are also added and written to the checksum position; after reading, the soft core side grabs the high, medium and low bytes for summing and compares them with the checksum position; if the comparison results are consistent, the data is adopted, if not, the data is read again.

[0027] The present invention also provides a satellite-borne coarse pointing control device, the control device is used in the control method as described above, and the control device comprises:

[0028] An FPGA module, the FPGA module comprising a soft core processor, a logic side and a soft core side;

[0029] A peripheral circuit is electrically connected to the FPGA module, and the peripheral circuit includes:

[0030] Level conversion module, isolation module, PWM signal output module, signal interaction module, program refresh module, flash memory module, power supply module and telemetry and remote control module.

[0031] Optionally, the control device does not include a digital signal processing module.

[0032] Optionally, the logic side includes three parts, which are, from top to bottom, an input-output unit, a user logic unit and a basic unit; the input-output unit is used to interact with the peripheral circuit and the soft core side; the user logic unit is used to implement logic control of the processor local bus and receive data from the soft core side; the basic unit includes a logic side reset module, a watchdog module, a coarse pointing mechanism over-speed protection module, a coarse pointing mechanism over-current protection module, an azimuth axis pitch axis encoder data receiving and control module, an azimuth axis pitch axis motor current loop control module, a PWM wave generation module, a telemetry and remote control interface control module and a reconstruction module;

[0033] And / or, the soft core side includes a remote control command receiving and parsing module, a position parsing module, a closed-loop control module for a position loop and a speed loop, a telemetry data uploading module, a key control parameter refreshing module, a key program segment refreshing module, and a module for interacting with the logic side;

[0034] And / or, the soft core side and the logic side are communicatively connected via a processor local bus.

[0035] Optionally, the control device further comprises a program dual backup module, wherein the program dual backup module stores two identical configuration programs of the on-chip control system in two identical non-volatile flash memories, respectively, and the two programs serve as backups for each other; if one of the programs is overturned, it is started and controlled by the other program, and the two programs can also be used to repair and modify each other;

[0036] And / or, the control device also includes an on-track programming module, which is used to divide the configuration program into several frames, add a frame header, a total number of packets, and a current packet sequence number to each frame, and add a CRC check and a sum check at the end of the frame.

[0037] In summary, compared with the prior art, the control method of the satellite-borne coarse pointing device and the satellite-borne coarse pointing control device provided by the present invention have the following beneficial effects:

[0038] The control method and the satellite-borne coarse pointing device of the present invention have taken targeted measures to resist single-particle upsets for the soft-core side, logic side and modules that may be affected by single-particle upsets during data transmission of the on-chip control system of the coarse pointing mechanism, thereby ensuring the precise, stable and safe control of the satellite-borne coarse pointing mechanism; the control device uses a soft-core processor on the FPGA for calculation, and the soft-core processor replaces the DSP to avoid the DSP being affected by single-particle upsets. Not only can the real-time and precise control of the satellite-borne coarse pointing device be achieved, but the anti-interference capability of the on-chip system is also greatly improved, ensuring the reliability and safety of the CPA in harsh environments. At the same time, by streamlining the hardware, the miniaturization and low cost of the on-chip system of the coarse pointing mechanism of space laser communication are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a structural diagram of the satellite-borne coarse pointing control device of the present invention.

[0040] Figure 2 This is a structural diagram of the system-on-chip software design of the present invention.

[0041] Figure 3 This is a data partition diagram of the key parts of the program segment on the soft core side of the present invention.

[0042] Figure 4 It is a schematic diagram for comparing data of key parts of the program segment on the soft core side of the present invention.

[0043] Figure 5 This is a diagram of the PLB bus interaction data separation of the present invention.

[0044] Figure 6 This is a frame format diagram of the reconstructed frame of the present invention.

[0045] Figure 7 The present invention is a flow chart of a control method for a satellite-borne coarse pointing device. DETAILED DESCRIPTION

[0046] The following will be combined with the attached embodiment of the present invention Figure 1 ~Attached Figure 7 , the technical solutions, structural features, objectives achieved and effects in the embodiments of the present invention are described in detail.

[0047] It should be noted that the drawings are in a very simplified form and use non-precise proportions. They are only used to conveniently and clearly assist in explaining the embodiments of the present invention, and are not used to limit the conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention.

[0048] It should be noted that, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only the elements explicitly listed, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0049] like Figure 7 As shown, the present invention provides a control method for a satellite-borne coarse pointing device, the control method comprising:

[0050] Regular comparison and refresh of key parts of program segments; real-time comparison and rewriting of key control parameters on the soft core side; soft reset on the soft core side and overall reset of the on-chip system; interactive verification of processor local bus data.

[0051] Among them, the regular comparison and refresh of key parts of the program segment specifically includes:

[0052] The key parts of the program segment are stored in the BRAM area of ​​FPGA, which is easily affected by SEU. The consequences of overturning the key parts of the program segment may be serious or even completely out of control of the mechanism, so the program segment needs to be protected. The program segment is stored in the flash memory (FLASH), and the program segment is read out from the flash regularly for comparison and update. Specifically, the key parts of the soft core control program are first identified, including position reception, position calculation and closed loop.

[0053] The compiler elf file generated after the soft core control program is compiled is as follows Figure 3 As shown, the specific address space (A1, A2, A3, A4, A5) and the corresponding data (Da1, Da2, Da3, Da4, Da5) of the storage area where the key data of the program segment are located are identified.

[0054] Store two identical copies of critical data in a free area of ​​the flash memory, avoiding the program storage area of ​​the FPGA.

[0055] After the program runs normally, two copies of Da1 data are read from the flash memory within the first 5 seconds, and data Da1 is read from the corresponding address space A1 at the same time, and the three copies of data are compared two by two, such as Figure 4As shown, if the three copies of data are the same, continue to execute; if one program in the flash memory is different from the other two, continue to execute and write the correct data to the logic side, and the logic side writes the data to the corresponding flash memory area; if the flash memory data is the same but different from the data read from address A1, write the flash memory data to address A1; if the three copies of data are different, let the coarse pointing mechanism enter the standby state.

[0056] After the program runs normally, the second 5 seconds are used to compare the Da2 data, and the third 5 seconds are used to compare the Da3 data. The key data are compared and refreshed every 25 seconds to avoid the accumulation of errors and achieve uninterrupted recovery control.

[0057] By regularly comparing and refreshing key parts of program segments, especially real-time comparing and rewriting some global variables with fixed values, potential errors can be eliminated and error accumulation can be prevented.

[0058] In the control process of the coarse pointing mechanism, the global variables in the program data segment on the soft core side, especially some key parameters, are fixed values, which are easily affected by SEU and cause the mechanism to enter an out-of-control state. For example, the electrical phase angle, angular velocity of rotation and soft limit of the motor, when affected by SEU, are likely to cause the motor to lose control or be unable to drive the motor to the correct position. In the present invention, these key variables are compared and rewritten in real time, and the real-time comparison and rewriting of the key control parameters on the soft core side specifically includes: determining the key control parameters, and the key control parameters include the electrical phase angle, angular velocity of rotation and soft limit, etc.

[0059] Taking the electrical phase angle as an example, four key control parameters are defined in the form of global variables: D, D1, D2, and D3. These four numbers are assigned the same value during initialization; D is used for normal control of the coarse pointing mechanism, and D1, D2, and D3 are used for comparison.

[0060] In each control cycle, D1, D2 and D3 are compared in pairs. If the three values ​​are equal, the D1 data is rewritten to D; if two of the values ​​are the same and one is different, the same value is rewritten to D; if the three values ​​compared this time are all different, the three values ​​D1, D2 and D3 are compared with D respectively. If one of them is the same, the same value is rewritten to D; if the three values ​​are all different and are also different from D, the coarse pointing mechanism is put into standby mode. In this way, all key parameters identified are compared and rewritten to eliminate potential errors, prevent error accumulation, and protect the safety of the mechanism.

[0061] Although the key parts of the program segment and the key control parameters of the motor on the soft core side are protected, the soft core side may still be affected by SEU, causing the program to run away and fall into an infinite loop, thereby causing the entire control system to stagnate and affect the safety control of the mechanism. For this reason, the reset of the soft core side and the reset of the entire on-chip system are designed, and the safety of the coarse pointing mechanism is guaranteed by combining the two reset measures. The soft core side soft reset and the overall reset of the on-chip system specifically include: the soft core side outputs 0xAA to the logic side through the PLB (Processor Local Bus) bus at the beginning of each control cycle, and outputs 0x55 to the logic side through the processor local bus after the control cycle ends. Each control cycle is 1ms; the logic side compares the received data. If the value changes in each control cycle, the soft core side will not be processed. If the value does not change for 20ms continuously, the soft core side will be reset; while resetting the soft core side, the number of resets of the soft core side is also counted. If the reset is repeated for more than 5 times, the logic side immediately cuts off the output of the PWM wave and resets the entire on-chip system.

[0062] By soft resetting the soft core side and resetting the entire system on chip, the soft core side and the entire system on chip can be prevented from running away.

[0063] like Figure 5 As shown, the processor local bus data interaction verification specifically includes: in the control process of the coarse pointing mechanism, data is transmitted between the soft core side and the logic side through the processor local bus. The data bit width of the processor local bus data transmission is 32 bits. The data bit width is divided, and the 0th to 23rd bits (bit0-bit23) store the high, medium and low bytes of the valid data to be transmitted, and the 24th to 31st bits (bit24-bit31) are used to store the checksum byte. When the soft core side writes data to the logic side, the soft core side first adds the high, medium and low bytes of the valid data, and assigns the lower 8 bits of the sum to obtain the checksum part; after the logic side receives the data, it sums the high, medium and low bits of the received data byte by byte and compares them with the check bits; if the comparison result is consistent, the logic side adopts the data; if the comparison result is inconsistent, the data is discarded and the soft core side is notified to rewrite the data; when the data on the logic side needs to be transmitted, the high, medium and low bytes are also added and written to the checksum position; after reading, the soft core side grabs the high, medium and low bytes, sums them and compares them with the checksum position; if the comparison result is consistent, the data is adopted; if it is inconsistent, the data is read again.

[0064] Through PLB (Processor Local Bus) data interaction verification, the accuracy of data interaction between the soft core side and the logic side is ensured.

[0065] like Figure 1As shown, the present invention also provides a satellite-borne coarse pointing control device, the control device is used for the control method as mentioned above, and the control device includes an FPGA module and peripheral circuits.

[0066] like Figure 2 As shown, the FPGA module includes a soft core processor, a logic side and a soft core side. The soft core side and the logic side are connected through the processor local bus communication, and the processor local bus is used to read and write the logic side data, thereby realizing all the functions used to control the coarse pointing mechanism. The soft core side and the logic side interact with each other to realize the precise, stable and safe control of CPA.

[0067] In this embodiment, the soft-core processor is the MicroBlaze soft-core in the FPGA module. MicroBlaze is a soft-core processor in Xilinx FPGA, which has high flexibility and customizability and can be integrated into FPGA to build a system on chip. The on-chip control system of the satellite coarse pointing control device mechanism of this embodiment uses the FPGA (Field Programmable Gate Array) supporting the MicroBlaze soft-core as the control core, and realizes functions including the creation of the MicroBlaze soft-core, the driving of the two-dimensional motor, the control and monitoring of the high-precision code disk, the control of the refresh chip, the dual storage and switching of the program, and the reconstruction of the program.

[0068] The peripheral circuit is electrically connected to the FPGA module, wherein the peripheral circuit includes a level conversion module, an isolation module, a PWM signal output module, a signal interaction module, a program refresh module, a flash memory module, a power supply module and a telemetry and remote control module.

[0069] The level conversion module realizes the bidirectional conversion of TTL and LVTTL signals. The isolation module adopts a high-level data isolator to isolate the electrical noise and interference of signal transmission in different voltage domains, and ensure the safety of signal integrity. The PWM (Pulse Width Modulation) signal output module adopts a dedicated three-phase bridge chip, and the output signal is used to drive the two-dimensional motor action. The signal interaction module is used to interact with the encoder circuit. The signal interaction module and the telemetry and remote control module use the RS422 interface to communicate, and use a high-level dedicated communication chip to realize the reading and control of the encoder signal. The program refresh module uses a dedicated readback refresh chip JFMRS01RH, which can realize the functions of timed readback refresh and program switching of FPGA programs. The readback refresh chip JFMRS01RH is used to regularly detect the SEF1 state of FPGA and refresh FPGA, which can reduce the cumulative effect of SEU. At the same time, when it is detected that the FPGA enters an abnormal state, it can automatically reload and reconfigure all the data of the FPGA used by the system on chip, so that the coarse pointing mechanism system on chip can re-enter the normal working state.

[0070] The flash memory module is used to store the main backup program. The flash memory module is used to store the main program and the backup program. Two high-grade NOR FLASH chips JFM29LV641RH are used as storage areas for storing the main program and the backup program. They are connected to the FPGA through the readback refresh chip to realize the dual backup and switching of the program. The on-chip control system of the coarse pointing mechanism integrates the soft core into the FPGA, and there is no need to burn the soft core program separately. The program of the on-chip control system is stored in the radiation-resistant NORFLASH. Since the on-chip system runs in outer space, the environment is harsh and there are many cosmic rays. There is still a very small possibility that the configuration program stored in the FLASH will be affected by SEU, resulting in the unavailability of the configuration program. Therefore, a program double backup measure is designed, that is, two identical configuration programs A and B of the on-chip control system are stored in two identical NOR FLASH. The two programs back up each other. If the A program is overturned, it can be started and controlled by the B program. At the same time, the A program can be repaired and modified according to the B program, and vice versa.

[0071] The telemetry and remote control module is used to interact with the outside world.

[0072] In this embodiment, the FPGA module serving as the control core is divided into two parts: a logic side and a soft core side. During the control process, the soft core side and the logic side interact with each other to achieve accurate, stable and safe control of the FPGA module.

[0073] The specific functions of the soft core side include receiving and parsing remote control commands, position analysis, closed-loop control of the position loop and speed loop, uploading telemetry data, refreshing key control parameters, refreshing key program segments, and interacting with the logic side.

[0074] The control device of the present invention does not include a DSP (Digital Signal Processing) module. The control device of the present invention abandons the DSP module in hardware, and only uses FPGA as a common coarse pointing control system with a control core, uses the MicroBlaze core in the FPGA for floating-point operations, and uses the FPGA as the core of the on-chip control system of the satellite-borne coarse pointing mechanism. The hardware system no longer includes a DSP, and the peripheral circuits of the DSP are also eliminated, which can reduce the circuit board area and significantly reduce the hardware cost.

[0075] The logic side consists of three parts, from top to bottom, namely input-output unit (IO unit), user logic unit (user_logic unit) and basic unit (base unit). The input-output unit is used to interact with peripheral circuits and the soft core side; as the top-level module of the logic side, the input-output unit mainly implements the instantiation of external IO (input and output) and PLB bus, and the input-output unit serves as an interactive bridge between FPGA peripheral devices and the soft core side.

[0076] The user logic unit is used to realize the logic control of the processor local bus and receive data from the soft core side. The basic unit is the lowest level of the logic side, including the logic side reset module, watchdog module, coarse pointing mechanism over-speed protection module, coarse pointing mechanism over-current protection module, azimuth axis pitch axis encoder data receiving and control module, azimuth axis pitch axis motor current loop control module, PWM wave generation module, telemetry remote control interface control module and reconstruction module.

[0077] The soft core side includes a remote control command receiving and parsing module, a position parsing module, a closed-loop control module for the position loop and the speed loop, a telemetry data uploading module, a key control parameter refresh module, a key program segment refresh module, and a module for interacting with the logic side.

[0078] The control device also includes a program dual backup module, which stores two identical configuration programs of the on-chip control system in two identical non-volatile flash memories, and the two programs back up each other. If one of the programs is overturned, it can be started and controlled by the other program. The two programs can also be used to repair and modify each other.

[0079] Although the configuration program of the on-chip system is stored in the radiation-resistant NOR FLASH, there is still a very small possibility that the SEU may cause the coarse pointing mechanism on-chip control system to lose control, or when the existing program cannot meet the actual use requirements, the program needs to be upgraded. Therefore, an on-orbit programming module is also configured on the control device. Figure 6As shown, the on-orbit programming module is used to divide the configuration program into several frames, add a frame header, a total number of packets, and a current packet sequence number to each frame, and add a CRC (Cyclic Redundancy Check) checksum and checksum to the end of the frame. The current mode is switched to the on-orbit programming mode through an instruction, and the reconstructed data frame is sent to the system-on-chip at a fixed interval in the frame format through the remote control port. After the system-on-chip receives the on-orbit programming data, the CRC check calculates the data to generate a check value, and attaches the check value to the end of the data frame. After receiving the data, the same calculation is performed, and the calculated check value is compared with the received check value. If the two check values ​​are the same, it means that there is no error in the data transmission process; if they are different, it means that the data may have an error. By setting up the on-orbit programming module, the system-on-chip has the on-orbit programming function.

[0080] In addition, in the embodiment of the present invention, the program on the logic side will also be affected by SEU. In order to avoid the program on the logic side from failing to run due to the influence of SEU. For the key functions of the program on the logic side, a triple-module redundancy design is performed and the ECC (Error Correcting Code) check of the FIFO (First In First Out) is turned on, which specifically includes: identifying the key functions on the logic side, such as the current loop control module and the PWM generation module, and performing TMR (Triple Modular Redundancy) on these key function modules; in the TMR triple-module redundancy design, for the key function modules, three identical modules are used to run simultaneously. These three modules receive the same input and process independently. The output result of each module will be judged by a majority voter. If the output results of two or three of the three modules are consistent, then this result is considered to be the correct output; if the output results of the three modules are inconsistent, it indicates that one or more of the modules have failed. The TMR triple-module redundancy design can effectively improve the reliability and fault tolerance of the system. Even if one of the modules fails, the system can still rely on the other two normal modules to continue working, thereby reducing the risk of system failure due to a single module failure. At the same time, the TMR design can also detect and locate faulty modules so that they can be repaired or replaced in time.

[0081] In addition, the ECC function is enabled for all FIFOs on the logic side. The FIFO on the logic side is mainly used in the use of telemetry and remote control serial ports. The specific process is to check the ECC function during the configuration process of generating the FIFO IP core. When data is written to and read from the FIFO, the ECC logic will perform error detection. If a correctable error is detected, it will be automatically corrected to minimize the impact of SEU on FIFO data transmission.

[0082] Specifically, when data is written to the FIFO, the ECC encoder encodes the data according to a specific algorithm and generates additional check bits. These check bits are stored in the FIFO together with the original data. When data is read from the FIFO, the ECC decoder checks the read data and the check bits. If an error is found in the data, the decoder determines the location of the error and corrects it.

[0083] By enabling the ECC function, you can improve data reliability, enhance system stability, and protect critical data.

[0084] In addition, the implementation process of the on-chip control system of the present invention is as follows:

[0085] (1) Use Base System Builder to create an XPS project to generate the basic architecture of the system on chip. Select the bus type, FPGA model, single core or multi-core, input clock frequency, system clock frequency, storage space size, floating-point operation enable, and other configuration options. After completing the basic configuration, add and configure commonly used peripherals.

[0086] (2) Use the ISE Project Navigator development tool to create a new project and implement all the functions of the base unit, including logic side reset, soft core watchdog, coarse pointing mechanism over-speed protection, coarse pointing mechanism over-current protection, azimuth axis pitch axis encoder data reception and control, azimuth axis pitch axis motor current loop control, PWM generation, telemetry and remote control interface control and reconstruction, etc.

[0087] (3) Add the base unit as a peripheral to the infrastructure generated in the first step, and generate the logic side of the system on chip through the user_logic unit and IO unit.

[0088] (4) Configure the soft core in Xilinx Platform Studio software, including external clock, reset, interrupt mode, interrupt priority, space allocation, connection with the logic side, clock and IO constraints. After the configuration is completed, the netlist file and bitstream file can be generated.

[0089] (5) After all the data is generated, you can export the soft core design in the Xilinx Platform Studio software and jump to the Xilinx SDK software to develop the software, realizing functions including receiving and parsing remote control commands, position analysis, closed-loop control of position loop and speed loop, uploading telemetry data, refreshing key control parameters, refreshing key program segments, and interacting with the logic side.

[0090] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A control method for a satellite-borne coarse pointing device, characterized in that: The control method includes: regular comparison and refreshing of key parts of program segments; and / or, real-time comparison and rewriting of key control parameters on the soft core side; and / or, soft reset on the soft core side and overall reset of the system on chip; and / or, processor local bus data interaction verification.

2. The control method for a satellite-borne coarse pointing device according to claim 1, characterized in that: The periodic comparison and refreshing of the key parts of the program segment includes: Store program segments in flash memory and identify key parts of the soft-core control program; The compiler generated after the soft core control program is compiled identifies the specific address space (A1, A2, A3, A4, A5) and corresponding data (Da1, Da2, Da3, Da4, Da5) of the storage area where the key data of the program segment is located; Storing two identical copies of the key data in a free area of ​​the flash memory; After the program runs normally, within the first 5 seconds, two copies of Da1 data are read from the flash memory, and at the same time, data Da1 is read from the corresponding address space A1. The three copies of data are compared in pairs. If the three copies of data are the same, the execution continues; if one program in the flash memory is different from the other two, the execution continues, and the correct data is written to the logic side, and the logic side writes the data to the corresponding flash memory area; if the flash memory data is the same but different from the data read from address A1, the flash memory data is written to the A1 address; if the three copies of data are different, the coarse pointing mechanism enters the standby state; After the program runs normally, the second 5 seconds are used to compare the Da2 data, and the third 5 seconds are used to compare the Da3 data. The key data are compared and refreshed every 25 seconds to avoid the accumulation of errors and achieve uninterrupted recovery control.

3. The control method for a satellite-borne coarse pointing device according to claim 2, characterized in that: The key parts include position reception, position calculation and loop closure.

4. The control method for a satellite-borne coarse pointing device according to claim 1, characterized in that: The real-time comparison and rewriting of the key control parameters on the soft core side specifically includes: Determine key control parameters, including electrical phase angle; Four key control parameters, D, D1, D2, and D3, are defined in the form of global variables, and the same value is assigned to these four numbers during initialization; wherein D is used for normal control of the coarse pointing mechanism, and D1, D2, and D3 are used for comparison; In each control cycle, the D1, D2 and D3 are compared in pairs. If the three values ​​are equal, the D1 data is rewritten to D; if two of the values ​​are the same and one of them is different, the same value is rewritten to D; if the three values ​​compared this time are all different, the three values ​​D1, D2, and D3 are compared with D respectively. If one of them is the same, the same value is rewritten to D; if the three values ​​are all different and are also different from D, the coarse pointing mechanism is put into standby state.

5. The control method for a satellite-borne coarse pointing device according to claim 1, characterized in that: The soft core side soft reset and the overall system on chip reset specifically include: The soft core side outputs 0xAA to the logic side through the processor local bus at the beginning of each control cycle, and outputs 0x55 to the logic side through the processor local bus after the control cycle ends. Each control cycle is 1ms; the logic side compares the received data, and if the value changes in each control cycle, the soft core side is not processed. If the value does not change for 20ms, the soft core side is reset; while resetting the soft core side, the number of resets of the soft core side is also counted. If the resets exceed 5 times in a row, the logic side immediately cuts off the output of the PWM wave and resets the entire on-chip system.

6. The control method for a satellite-borne coarse pointing device according to claim 1, characterized in that: The processor local bus data interaction verification specifically includes: In the control process of the coarse pointing mechanism, data transmission between the soft core side and the logic side is transmitted through the processor local bus. The data bit width of the processor local bus for transmitting data is 32 bits. The data bit width is divided, and the 0th to 23rd bits store the high, medium and low bytes of the valid data to be transmitted, and the 24th to 31st bits are used to store the check byte; when the soft core side writes data to the logic side, the soft core side first adds the high, medium and low bytes of the valid data, and the obtained sum is assigned to the lower 8 bits to obtain the checksum part; after the logic side receives the data, the high, medium and low bits of the received data are summed by byte and compared with the check bits; if the comparison results are consistent, the logic side adopts the data, if the comparison results are inconsistent, the data is discarded and the soft core side is notified to rewrite the data; when the data on the logic side needs to be transmitted, the high, medium and low bytes are also added and written to the checksum position; after reading, the soft core side grabs the high, medium and low bytes for summing and compares them with the checksum position; if the comparison results are consistent, the data is adopted, if not, the data is read again.

7. A satellite-borne coarse pointing control device, characterized in that: The control device is used for the control method according to any one of claims 1 to 6, and the control device comprises: An FPGA module, the FPGA module comprising a soft core processor, a logic side and a soft core side; A peripheral circuit is electrically connected to the FPGA module, and the peripheral circuit includes: Level conversion module, isolation module, PWM signal output module, signal interaction module, program refresh module, flash memory module, power supply module and telemetry and remote control module.

8. The satellite-borne coarse pointing control device according to claim 7, characterized in that: The control device does not include a digital signal processing module.

9. The satellite-borne coarse pointing control device according to claim 7, characterized in that: The logic side includes three parts, which are input and output unit, user logic unit and basic unit from top to bottom; the input and output unit is used to interact with the peripheral circuit and the soft core side; the user logic unit is used to realize the logic control of the processor local bus and receive the data of the soft core side; the basic unit includes a logic side reset module, a watchdog module, a coarse pointing mechanism over-speed protection module, a coarse pointing mechanism over-current protection module, an azimuth axis pitch axis encoder data receiving and control module, an azimuth axis pitch axis motor current loop control module, a PWM wave generation module, a telemetry and remote control interface control module and a reconstruction module; And / or, the soft core side includes a remote control command receiving and parsing module, a position parsing module, a closed-loop control module for a position loop and a speed loop, a telemetry data uploading module, a key control parameter refreshing module, a key program segment refreshing module, and a module for interacting with the logic side; And / or, the soft core side and the logic side are communicatively connected via a processor local bus.

10. The satellite-borne coarse pointing control device according to claim 7, characterized in that: The control device also includes a program dual backup module, which stores two identical configuration programs of the on-chip control system in two identical non-volatile flash memories, respectively, and the two programs serve as backups for each other; if one of the programs is overturned, it is started and controlled by the other program, and the two programs can also be used to repair and modify each other; And / or, the control device also includes an on-track programming module, which is used to divide the configuration program into several frames, add a frame header, a total number of packets, and a current packet sequence number to each frame, and add a CRC check and a sum check at the end of the frame.

Images