U2U3 multiplexing test fixture and test method

Abstract

The embodiment of the invention discloses a U2U3 multiplexing test fixture which comprises a test connecting plate, one end of the test connecting plate is provided with an SFF-8639 physical connector, the SFF-8639 physical connector is used for being in butt joint with a U.2 interface or a U.3 interface, and the other end of the test connecting plate is provided with an SMP interface set. According to the U2U3 multiplexing test fixture, the SFF-8639 physical connector is in butt joint with the U.2 or U.3 interface, the SMP interface group is connected with a test instrument or equipment, the SMP interface group is designed according to the standards of the U.2 or U.3 interface, the signal transmission requirements of the two interfaces can be met at the same time, and the test efficiency and the test accuracy are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of interface testing, and in particular to a U2U3 multiplexing test fixture and a test method. Background Art

[0002] In the current test market, independent fixtures, U.2 and U.3, are commonly used for verification of U.2 and U.3 interfaces. Although both fixtures are based on the same physical connector standard SFF-8639, they follow different communication protocols in terms of pin configuration - U.2 follows the SFF-8639 protocol, while U.3 uses the SFF-TA-1001 protocol.

[0003] This differentiated design leads to a significant problem: when different types of interfaces need to be verified on the same test motherboard, operators have to change fixtures to match the test requirements of different interfaces. This practice is not only inefficient, but more importantly, due to the differences in the fixtures themselves, each change will introduce new test parameter variables, especially when analyzing motherboard problems, because different fixtures have different related parameters, which greatly increases the complexity of problem diagnosis. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a U2U3 multiplexed test fixture to solve the problem that when verifying different types of interfaces on the same test motherboard, the operator has to replace the fixture to match the test requirements of different interfaces. This approach is not only inefficient, but more importantly, due to the differences in the fixtures themselves, each replacement will introduce new test parameter variables. In particular, when analyzing motherboard problems, different fixtures have different related parameters, which greatly increases the complexity of problem diagnosis.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] An embodiment of the present invention provides a U2U3 multiplexing test fixture, which includes: a test connection board, one end of which is provided with an SFF-8639 physical connector, and the SFF-8639 physical connector is used to connect to a U.2 interface or a U.3 interface, and the other end of the test connection board is provided with an SMP interface group, and the SMP interface group includes: a U.2RX3+ interface, a U.2RX3- interface, a U.2TX3- interface, a U.2TX3+ interface, a U.2RX2+ / U.3RX3+ interface, a U.2RX2- / U.3RX3- interface, and a U.2TX2- / U.3TX3-interface, U.2TX2+ / U.3TX3+interface, U.2RX1+ / U.3RX2+interface, U.2RX1- / U.3RX2-interface, U.2TX1+ / U.3TX2-interface, U.3RX1+interface, U.3RX1-interface, U.3TX1-interface, U.3TX1+interface, U.3RX0+interface, U.3RX0-interface, U.2RX0+interface, U.2RX0-interface, U.3TX0-interface, U.3TX0+interface, U.2TX0 -interface, U.2TX0+interface, CLK-interface, CLK+interface; wherein, the U.2RX3+interface, U.2RX3-interface, U.2TX3-interface, U.2TX3+interface, U.2RX0+interface, U.2RX0-interface, U.2TX0-interface, U.2TX0+interface are SMP interfaces corresponding to the U.2 interface, and the U.3RX1+interface, U.3RX1-interface, U.3TX1-interface, U.3TX1+interface, U.3RX0+interface, U.3RX0-interface, U.3TX0-interface, U.3T The X0+ interface is an SMP interface corresponding to the U.3 interface, and the U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+, CLK- interface, and CLK+ interface are SMP interfaces adapted to the U.2 interface and the U.3 interface.

[0007] As a preferred technical solution of the present invention, the U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX0+ interface, U.2RX0- interface, U.2TX0- interface, and U.2TX0+ interface are combined into a U.2 applicable interface group; the U.3RX1+ interface, U.3RX1- interface, U.3TX1- interface, U.3TX1+ interface, U.3RX0+ interface, U.3RX0- interface, U.3TX0- interface, and U.3TX0+ interface are combined into a U.3 applicable interface group; the U.2RX2+ / U.3RX3+ interface, U.2RX2- / The U.3RX3-interface, U.2TX2- / U.3TX3-interface, U.2TX2+ / U.3TX3+interface, U.2RX1+ / U.3RX2+interface, U.2RX1- / U.3RX2-interface, U.2TX1- / U.3TX2-interface, and U.2TX1+ / U.3TX2+interface are combined into a U.2-U.3-common interface group; the CLK-interface and CLK+interface are combined into a test interface group; the U.2 applicable interface group, U.2-U.3-common interface group, U.3 applicable interface group, and test interface group are arranged linearly at the other end of the test connection board according to the SFF-8639Pin definition.

[0008] As a preferred technical solution of the present invention, the U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX The connection ports of the SFF-8639 physical connector are all facing the SFF-8639 physical connector.

[0009] As a preferred technical solution of the present invention, the U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+ interface, CLK- interface, and CLK+ interface are all connected to the SFF-8639 physical connector through cables.

[0010] As a preferred technical solution of the present invention, the test connection board includes a rectangular portion and a fan-shaped portion, the SFF-8639 physical connector is arranged on one side of the rectangular portion, the fan-shaped portion is extended from the other side of the rectangular portion, and the SMP interface group is arranged along the circumference of the fan-shaped portion.

[0011] As a preferred technical solution of the present invention, the center of the sector-shaped portion is the midpoint of the other side of the rectangular portion.

[0012] As a preferred technical solution of the present invention, the SMP interface group is evenly arranged along the circumference of the sector-shaped portion, and the test connection plate is an axisymmetric structure.

[0013] As a preferred technical solution of the present invention, it also includes a plurality of detachable cable groups, one end of the detachable cable group is connected to the SFF-8639 physical connector, and the other end of the detachable cable group is detachably connected to the U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX0+ interface, U.2RX0- interface, U.2TX0- interface, U.2TX0+ interface, or, is detachably connected to the U.3RX1+ interface, U.3RX1- interface, U.3TX1- interface, U.3TX1+ interface, U.3RX0+ interface, U.3RX0- interface, U.3TX0- interface, U.3TX0+ interface.

[0014] As a preferred technical solution of the present invention, the CLK- interface and the CLK+ interface are connected to an oscilloscope via cables.

[0015] An embodiment of the present invention further provides a testing method, including the U2U3 multiplexing test fixture as described above, comprising the following steps:

[0016] Determining whether the test object of the U2U3 multiplexing test fixture is a U.2 interface or a U.3 interface;

[0017] If the test object of the U2U3 multiplexing test fixture is the U.2 interface, the SFF-8639 physical connector is connected to the U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3- interface through cables. 3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+ interface, U.2RX0+ interface, U.2RX0- interface, U.2TX0- interface, U.2TX0+ interface, CLK- interface, CLK+ interface, and connect the CLK- interface and CLK+ interface to the oscilloscope through cables;

[0018] If the test object of the U2U3 multiplexing test fixture is the U.3 interface, the SFF-8639 physical connector is connected to the U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface through cables. , U.2TX1- / U.3TX2-interface, U.2TX1+ / U.3TX2+interface, U.3RX1+interface, U.3RX1-interface, U.3TX1-interface, U.3TX1+interface, U.3RX0+interface, U.3RX0-interface, U.3TX0-interface, U.3TX0+interface, CLK-interface, CLK+interface, and connect the CLK-interface and CLK+ interface to the oscilloscope through cables;

[0019] The test result is obtained by observing and measuring the electrical signal waveform with the oscilloscope.

[0020] Compared with the prior art, the U2U3 multiplexing test fixture of the present invention is connected to the U.2 or U.3 interface through the SFF-8639 physical connector, and is connected to the test instrument or equipment through the SMP interface group. The SMP interface group is designed according to the standards of the U.2 and U.3 interfaces, and can simultaneously meet the signal transmission requirements of the two interfaces, thereby improving the test efficiency and test accuracy.

[0021] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0023] Figure 1 An exploded view of an assembly of a U2U3 multiplexing test fixture of the present invention;

[0024] Figure 2 A schematic diagram of an application scenario of a testing method of the present invention;

[0025] Figure 3 The present invention is a flow chart of a testing method.

[0026] Description of the symbols in the figure:

[0027] 1. Test connection board; 11. Rectangular part; 12. Fan-shaped part; 2. SFF-8639 physical connector; 3. SMP interface group;

[0028] 100. U2U3 multiplexing test fixture. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0031] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships described in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0032] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0033] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be connected, detachably connected, or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0035] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0036] See also Figure 1An embodiment of the present invention provides a U2U3 multiplexing test fixture 100, which includes: a test connection board 1, one end of the test connection board 1 is provided with an SFF-8639 physical connector 2, the SFF-8639 physical connector 2 is used to connect with a U.2 interface or a U.3 interface, and the other end of the test connection board 1 is provided with an SMP interface group 3, the SMP interface group 3 includes: a U.2RX3+ interface, a U.2RX3- interface, a U.2TX3- interface, a U.2TX3+ interface, a U.2RX2+ / U.3RX3+ interface, a U.2RX2- / U.3RX3- interface, a U.2TX 2- / U.3TX3-interface, U.2TX2+ / U.3TX3+interface, U.2RX1+ / U.3RX2+interface, U.2RX1- / U.3RX2-interface, U.2TX1+ / U.3TX2+interface, U.3RX1+interface, U.3RX1-interface, U.3TX1-interface, U.3TX1+interface, U.3RX0+interface, U.3RX0-interface, U.2RX0+interface, U.2RX0-interface, U.3TX0-interface, U.3TX0+interface, U.2T X0-interface, U.2TX0+interface, CLK-interface, CLK+interface; wherein, the U.2RX3+interface, U.2RX3-interface, U.2TX3-interface, U.2TX3+interface, U.2RX0+interface, U.2RX0-interface, U.2TX0-interface, U.2TX0+interface are SMP interfaces corresponding to the U.2 interface, and the U.3RX1+interface, U.3RX1-interface, U.3TX1-interface, U.3TX1+interface, U.3RX0+interface, U.3RX0-interface, U.3TX0-interface, U.3 The TX0+ interface is an SMP interface corresponding to the U.3 interface, and the U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+, CLK- interface, and CLK+ interface are SMP interfaces adapted to the U.2 interface and the U.3 interface.

[0037] In this embodiment, an SFF-8639 physical connector 2 is provided at one end of the U2U3 multiplexing test fixture 100, and this connector can be connected to the U.2 interface or the U.3 interface. It can be understood that U.2 and U.3 are two different interface standards, which belong to the prior art and are commonly used for connecting high-speed, large-capacity storage devices. Specifically, given that the existing U.2 interface and U.3 interface are both SFF-8639 physical connectors, the physical connector in this solution is an SFF-8639 physical connector 2 that can be connected to the U.2 interface and the U.3 interface. The other end of the U2U3 multiplexing test fixture 100 is provided with a group of SMP (Small Form-factor Pluggable) interfaces, which are used to connect to test equipment or measuring instruments for data transmission and signal measurement. Specifically, the SMP interface group 3 includes a variety of interfaces, which correspond to different signal lines in the U.2 and U.3 interfaces, for example, interfaces such as U.2RX3+, U.2RX3-, etc. are used to receive the third pair of differential signals of the U.2 interface, while interfaces such as U.3RX3+, U.3RX3-, etc. are used to receive the third pair of differential signals of the U.3 interface. At the same time, these interfaces also support signal multiplexing between U.2 and U.3, such as U.2RX2+ / U.3RX3+, U.2RX2- / U.3RX3-, etc. In addition, the SMP interface group 3 also includes clock signal interfaces (CLK- and CLK+), which are used to transmit clock signals to ensure the synchronization and accuracy of data transmission. An important feature of the U2U3 multiplexing test fixture 100 in this embodiment is that it supports multiplexing of U.2 and U.3 interfaces, which means that by adjusting the connection method between the SFF-8639 physical connector 2 and the SMP interface group 3, the same U2U3 multiplexing test fixture 100 can be used to test devices with U.2 interfaces and also can be used to test devices with U.3 interfaces. This multiplexing function greatly improves the flexibility and efficiency of the test fixture.

[0038] Preferably, on the test connection board 1, U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+ The corresponding interface names are marked next to the U.3RX1+ interface, U.3RX1- interface, U.3TX1- interface, U.3TX1+ interface, U.3RX0+ interface, U.3RX0- interface, U.2RX0+ interface, U.2RX0- interface, U.3TX0- interface, U.3TX0+ interface, U.2TX0- interface, U.2TX0+ interface, CLK- interface, and CLK+ interface. For example, U.2RX3+ is marked next to the U.2RX3- interface, and U.2RX3- is marked next to the U.2RX3+ interface.

[0039] Furthermore, the combination of U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX0+ interface, U.2RX0- interface, U.2TX0- interface, and U.2TX0+ interface is a U.2 applicable interface group; the combination of U.3RX1+ interface, U.3RX1- interface, U.3TX1- interface, U.3TX1+ interface, U.3RX0+ interface, U.3RX0- interface, U.3TX0- interface, and U.3TX0+ interface is a U.3 applicable interface group; the combination of U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3-interface, U.2TX2- / U.3TX3-interface, U.2TX2+ / U.3TX3+interface, U.2RX1+ / U.3RX2+interface, U.2RX1- / U.3RX2-interface, U.2TX1- / U.3TX2-interface, and U.2TX1+ / U.3TX2+interface are combined into the U.2-U.3-common interface group; the CLK-interface and the CLK+interface are combined into the test interface group; the U.2 applicable interface group, the U.2-U.3-common interface group, the U.3 applicable interface group, and the test interface group are arranged linearly in sequence at the other end of the test connection board 1.

[0040] In this embodiment, the SMP interface in the U.2 applicable interface group is specifically used for communication and data transmission with the device of the U.2 interface, the SMP interface in the U.3 applicable interface group is specifically used for communication and data transmission with the device of the U.3 interface, the SMP interface in the U.2-U.3-shared interface group can be connected to the device of the U.2 interface and the device of the U.3 interface, and the SMP interface in the test interface group is used to transmit the clock signal to ensure the synchronization and accuracy of data transmission. At the other end of the test connection board 1, the U.2 applicable interface group, the U.2-U.3-shared interface group, the U.3 applicable interface group, and the test interface group are arranged linearly according to the SFF-8639Pin definition, with unified standards, easy to identify, and convenient for users to connect and test.

[0041] Furthermore, the SMP interfaces in the prior art all use a 90° vertical interface, that is, the direction of the connection port is perpendicular to the plate surface of the fixture. This results in the cable being bent 90° at the SMP interface when wiring the SMP interface in the prior art. Long-term use will cause the cable to bend and cause parameter drift, thereby having a certain impact on the accuracy and consistency of the test data. Based on the defects of the above-mentioned prior art, the U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+ interface, U.3RX1+ interface, U.3RX1 The connection ports of the -interface, U.3TX1-interface, U.3TX1+interface, U.3RX0+interface, U.3RX0-interface, U.2RX0+interface, U.2RX0-interface, U.3TX0-interface, U.3TX0+interface, U.2TX0-interface, U.2TX0+interface, CLK-interface, and CLK+ interface are all facing the SFF-8639 physical connector 2, so that when the SFF-8639 physical connector 2 and the SMP interface group 3 are connected by cable, the cable can be kept flat and not affected by bending for a long time, thereby improving durability and stability, and ensuring the accuracy and consistency of test data.

[0042] Furthermore, it needs to be explained that the U2U3 multiplexing test fixture 100 proposed in this solution connects the SFF-8639 physical connector 2 and the SMP interface group 3 according to actual test requirements, and realizes the docking test of the U.2 interface or the U.3 interface through different connection methods between the SFF-8639 physical connector 2 and the SMP interface group 3. For example, when testing the U.2 interface, the U.2 applicable interface group, the U.2-U.3-common interface group, and the test interface group are connected to the SFF-8639 physical connector 2 through a cable; when testing the U.3 interface, the U.3 applicable interface group, the U.2-U.3-common interface group, and the test interface group are connected to the SFF-8639 physical connector 2 through a cable. It can be understood that no matter whether the U.2 interface or the U.3 interface is tested, the U.2-U .3- The common interface group and the test interface group are both connected to the SFF-8639 physical connector 2 through cables. In order to reduce the workload of testers, in this embodiment, the U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+ interface, CLK- interface, and CLK+ interface are all connected to the SFF-8639 physical connector 2 through cables, that is, the U.2-U.3- ​​common interface group and the test interface group are both connected to the SFF-8639 physical connector 2 through cables.

[0043] Furthermore, the test connection board 1 includes a rectangular portion 11 and a fan-shaped portion 12, the SFF-8639 physical connector 2 is arranged on one side of the rectangular portion 11, the fan-shaped portion 12 is formed by extending the other side of the rectangular portion 11, and the SMP interface group 3 is arranged along the circumference of the fan-shaped portion 12. In this embodiment, the design of the fan-shaped portion 12 allows more SMP interfaces to be arranged in a limited space, thereby improving space utilization, and the SMP interface group 3 is arranged along the circumference, so that each SMP interface has a relatively independent position, is not easy to be confused, and is convenient for users to connect and test.

[0044] Specifically, the center of the sector 12 is the midpoint of the other side of the rectangular portion 11. Specifically, the SMP interface groups 3 are evenly arranged along the circumference of the sector 12. Specifically, the test connection board 1 is an axisymmetric structure.

[0045] In this embodiment, the center of the sector 12 is set at the midpoint of the side of the rectangular portion 11, which ensures the symmetry of the test connection board 1 in appearance and layout, and the SMP interface group 3 is evenly distributed along the circumference, which not only ensures the number of SMP interfaces, but also allows each SMP interface to have enough space for connection and operation. More importantly, the cable lengths when the SFF-8639 physical connector 2 is connected to each SMP interface in the SMP interface group 3 are the same or have a small difference, and the difference in signal transmission delay caused by the difference in cable length will be minimized, thereby ensuring the accuracy of the test results.

[0046] Furthermore, the U2U3 multiplexing test fixture 100 also includes a plurality of detachable cable groups, one end of the detachable cable group is connected to the SFF-8639 physical connector 2, and the other end of the detachable cable group is detachably connected to the U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX0+ interface, U.2RX0- interface, U.2TX0- interface, U.2TX0+ interface, or, is detachably connected to the U.3RX1+ interface, U.3RX1- interface, U.3TX1- interface, U.3TX1+ interface, U.3RX0+ interface, U.3RX0- interface, U.3TX0- interface, U.3TX0+ interface. When the U2U3 multiplexing test fixture 100 of this embodiment tests the U.2 interface, one end of the detachable cable group is connected to the SFF-8639 physical connector 2, and the other end is detachably connected to the U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX0+ interface, U.2RX0- interface, U.2TX0- interface, and U.2TX0+ interface. When the U2U3 multiplexing test fixture 100 of this embodiment tests the U.3 interface, one end of the detachable cable group is connected to the SFF-8639 physical connector 2, and the other end is detachably connected to the U.3RX1+ interface, U.3RX1- interface, U.3TX1- interface, U.3TX1+ interface, U.3RX0+ interface, U.3RX0- interface, U.3TX0- interface, and U.3TX0+ interface.

[0047] Furthermore, the CLK-interface and the CLK+interface are connected to an oscilloscope via cables. It is understood that an oscilloscope is an electronic measuring instrument used to observe and measure the waveform of an electrical signal. In a test system, the oscilloscope can display the waveform of the clock signal transmitted by the CLK-interface and the CLK+interface in real time, thereby helping engineers analyze the stability and accuracy of the clock signal.

[0048] See also Figure 2 and Figure 3The embodiment of the present invention further provides a testing method, including the U2U3 multiplexing test fixture 100 as described above, for testing a device to be tested having a U.2 interface and / or a U.3 interface, comprising the following steps:

[0049] S100 , determining whether the test object of the U2U3 multiplexing test fixture 100 is a U.2 interface or a U.3 interface.

[0050] S200. If the test object of the U2U3 multiplexing test fixture 100 is a U.2 interface, the SFF-8639 physical connector 2 is connected to the U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U .3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+ interface, U.2RX0+ interface, U.2RX0- interface, U.2TX0- interface, U.2TX0+ interface, CLK- interface, CLK+ interface, and connect the CLK- interface and CLK+ interface to the oscilloscope through cables.

[0051] Optionally, the oscilloscope can be connected to the CLK-interface and the CLK+ interface through a cable and can also be connected to a TX interface, such as the U.2TX3-interface, U.2TX3+interface, U.2TX2- / U.3TX3-interface, U.2TX2+ / U.3TX3+interface, U.2TX1- / U.3TX2-interface, U.2TX1+ / U.3TX2+interface, U.2TX0-interface, and U.2TX0+interface, to achieve signal integrity analysis and confirm whether the TX consistency requirements of the PCI-SIG specification are met.

[0052] S300, if the test object of the U2U3 multiplexing test fixture 100 is a U.3 interface, connect the SFF-8639 physical connector 2 to the U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX 2-interface, U.2TX1- / U.3TX2-interface, U.2TX1+ / U.3TX2+ interface, U.3RX1+ interface, U.3RX1-interface, U.3TX1-interface, U.3TX1+ interface, U.3RX0+ interface, U.3RX0-interface, U.3TX0-interface, U.3TX0+ interface, CLK-interface, CLK+ interface, and connect the CLK-interface and CLK+ interface to the oscilloscope through cables.

[0053] Optionally, in addition to being connected to the CLK-interface and the CLK+ interface through a cable, the oscilloscope can also be connected to a TX interface, such as the U.2TX2- / U.3TX3-interface, U.2TX2+ / U.3TX3+ interface, U.2TX1- / U.3TX2-interface, U.2TX1+ / U.3TX2+ interface, U.3TX1-interface, U.3TX1+ interface, U.3TX0-interface, and U.3TX0+ interface, to achieve signal integrity analysis and confirm whether the TX consistency requirements of the PCI-SIG specification are met.

[0054] S400: Observe and measure the electrical signal waveform using the oscilloscope to obtain a test result.

[0055] Compared with the prior art, the U2U3 multiplexing test fixture of the present invention is connected to the U.2 or U.3 interface through the SFF-8639 physical connector, and is connected to the test instrument or equipment through the SMP interface group. The SMP interface group is designed according to the standards of the U.2 and U.3 interfaces, and can simultaneously meet the signal transmission requirements of the two interfaces, thereby improving the test efficiency and test accuracy.

[0056] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A U2U3 multiplexing test fixture, characterized in that: include: A test connection board, one end of which is provided with an SFF-8239 physical connector, the SFF-8639 physical connector is used to connect with a U.2 interface or a U.3 interface, and the other end of the test connection board is provided with an SMP interface group, the SMP interface group includes: U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3RX3+ interface 3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+ interface, U.3RX1+ interface, U.3RX1- interface, U.3TX1- interface, U.3TX1+ interface, U.3RX0+ interface, U.3RX0- interface, U.2RX0+ interface, U.2RX0- interface, U.3TX0- interface, U.3TX0+ interface, U.2TX0- interface, U.2TX0+ interface , CLK-interface, CLK+interface; wherein the U.2RX3+interface, U.2RX3-interface, U.2TX3-interface, U.2TX3+interface, U.2RX0+interface, U.2RX0-interface, U.2TX0-interface, U.2TX0+interface are SMP interfaces corresponding to the U.2 interface, and the U.3RX1+interface, U.3RX1-interface, U.3TX1-interface, U.3TX1+interface, U.3RX0+interface, U.3RX0-interface, U.3TX0-interface, U.3TX0+interface are Corresponding to the SMP interface of the U.3 interface, the U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+, CLK- interface, and CLK+ interface are SMP interfaces adapted to the U.2 interface and the U.3 interface.

2. A U2U3 multiplexing test fixture according to claim 1, characterized in that: The combination of the U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX0+ interface, U.2RX0- interface, U.2TX0- interface, and U.2TX0+ interface is a U.2 applicable interface group; the combination of the U.3RX1+ interface, U.3RX1- interface, U.3TX1- interface, U.3TX1+ interface, U.3RX0+ interface, U.3RX0- interface, U.3TX0- interface, and U.3TX0+ interface is a U.3 applicable interface group; the combination of the U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- The interface, U.2TX2- / U.3TX3-interface, U.2TX2+ / U.3TX3+interface, U.2RX1+ / U.3RX2+interface, U.2RX1- / U.3RX2-interface, U.2TX1- / U.3TX2-interface, and U.2TX1+ / U.3TX2+interface are combined into a U.2-U.3-common interface group; the CLK-interface and CLK+interface are combined into a test interface group; the U.2 applicable interface group, U.2-U.3-common interface group, U.3 applicable interface group, and test interface group are arranged linearly at the other end of the test connection board according to the SFF-8639Pin definition.

3. A U2U3 multiplexing test fixture according to claim 1, characterized in that: The U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2 The connection ports of TX1+ / U.3TX2+ interface, U.3RX1+ interface, U.3RX1- interface, U.3TX1- interface, U.3TX1+ interface, U.3RX0+ interface, U.3RX0- interface, U.2RX0+ interface, U.2RX0- interface, U.3TX0- interface, U.3TX0+ interface, U.2TX0- interface, U.2TX0+ interface, CLK- interface, and CLK+ interface are all facing the SFF-8639 physical connector.

4. A U2U3 multiplexing test fixture according to claim 1, characterized in that: The U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+ interface, CLK- interface, and CLK+ interface are all connected to the SFF-8639 physical connector through cables.

5. A U2U3 multiplexing test fixture according to claim 1, characterized in that: The test connection board includes a rectangular portion and a fan-shaped portion, the SFF-8639 physical connector is arranged on one side of the rectangular portion, the fan-shaped portion is formed by extending the other side of the rectangular portion, and the SMP interface group is arranged along the circumference of the fan-shaped portion.

6. A U2U3 multiplexing test fixture according to claim 5, characterized in that: The center of the sector portion is the midpoint of the other side of the rectangular portion.

7. A U2U3 multiplexing test fixture according to claim 5, characterized in that: The SMP interface groups are evenly arranged along the circumference of the sector-shaped portion, and the test connection plate is an axisymmetric structure.

8. The U2U3 multiplexing test fixture according to claim 1, characterized in that: It also includes a plurality of detachable cable groups, one end of the detachable cable group is connected to the SFF-8639 physical connector, and the other end of the detachable cable group is detachably connected to the U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX0+ interface, U.2RX0- interface, U.2TX0- interface, U.2TX0+ interface, or, is detachably connected to the U.3RX1+ interface, U.3RX1- interface, U.3TX1- interface, U.3TX1+ interface, U.3RX0+ interface, U.3RX0- interface, U.3TX0- interface, U.3TX0+ interface.

9. A U2U3 multiplexing test fixture according to claim 1, characterized in that: The CLK- interface and the CLK+ interface are connected to the oscilloscope via cables.

10. A testing method, characterized in that: The U2U3 multiplexing test fixture according to any one of claims 1 to 9 comprises the following steps: Determining whether the test object of the U2U3 multiplexing test fixture is a U.2 interface or a U.3 interface; If the test object of the U2U3 multiplexing test fixture is the U.2 interface, the SFF-8639 physical connector is connected to the U.2RX3+ interface, U.2RX3- interface, U.2TX3- interface, U.2TX3+ interface, U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3- interface through cables. 3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface, U.2TX1- / U.3TX2- interface, U.2TX1+ / U.3TX2+ interface, U.2RX0+ interface, U.2RX0- interface, U.2TX0- interface, U.2TX0+ interface, CLK- interface, CLK+ interface, and connect the CLK- interface and CLK+ interface to the oscilloscope through cables; If the test object of the U2U3 multiplexing test fixture is the U.3 interface, the SFF-8639 physical connector is connected to the U.2RX2+ / U.3RX3+ interface, U.2RX2- / U.3RX3- interface, U.2TX2- / U.3TX3- interface, U.2TX2+ / U.3TX3+ interface, U.2RX1+ / U.3RX2+ interface, U.2RX1- / U.3RX2- interface through cables. , U.2TX1- / U.3TX2-interface, U.2TX1+ / U.3TX2+interface, U.3RX1+interface, U.3RX1-interface, U.3TX1-interface, U.3TX1+interface, U.3RX0+interface, U.3RX0-interface, U.3TX0-interface, U.3TX0+interface, CLK-interface, CLK+interface, and connect the CLK-interface and CLK+ interface to the oscilloscope through cables; The test result is obtained by observing and measuring the electrical signal waveform with the oscilloscope.

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