JTAG-based NPU automatic test method

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Through the automated testing method based on JTAG, the problems of inefficient and insufficient coverage of traditional NPU tests are solved, and comprehensive, accurate and efficient automation of NPU tests are achieved.

CN119415405APending Publication Date: 2025-02-11HANGZHOU NATCHIP SCI & TECH CO LTD

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Patent Information

Application Number: CN202411905537.2
Authority / Receiving Office: CN · China
Patent Type: Applications(China)
Current Assignee / Owner
Filing Date: 2024-12-23
Publication Date: 2025-02-11

AI Technical Summary

Technical Problem

Traditional NPU testing methods are inefficient and difficult to fully cover all test parameters, there is a risk of omission, and manual testing cannot achieve efficient and accurate testing.

Method used

Using an automated test method based on JTAG, we automatically generate test data and test models, and automatically run and compare test results to ensure that each operator supported by the NPU can be tested comprehensively and accurately.

Benefits of technology

It realizes automation of NPU testing, improves test efficiency and coverage, reduces interference from human factors, and ensures chip quality.

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Abstract

The invention discloses a JTAG (Joint Test Action Group)-based NPU (Network Processing Unit) automatic test method. The method specifically comprises the following steps: selecting a to-be-measured sub-list and a test parameter of each test item in each to-be-measured sub-list; obtaining a test parameter of a test item of a to-be-measured sub-piece, and generating a test model and test data; compiling the test model into an NPU model file capable of running on the NPU; importing the NPU model file and the test data into a test program of the PC simulator and running the NPU model file and the test data; importing the test program, the NPU model file, the test data and the PC simulator output data into a chip memory, and running the test program on the chip to obtain a test result of the test item; and circulating the operation until each test item in all the to-be-measured sub-lists in the to-be-measured sub-list is tested. According to the invention, automation of the test process is realized by using the test script, each operator supported by the NPU can be comprehensively tested, the test cost is saved, the test efficiency is improved, and the chip quality is ensured.

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Description

Technical Field

[0001] The invention belongs to the field of computer technology, in particular to the field of chip testing technology, and specifically relates to a JTAG-based NPU automatic testing method. Background Art

[0002] With the rapid development of artificial intelligence technology, the importance of neural network processing unit NPU (Neural Processing Unit) in chip design has become increasingly prominent. NPU is specifically used to process operator operations in neural networks, and its performance is directly related to the artificial intelligence processing capabilities of the entire system. During the chip testing phase, in order to ensure that the NPU operators can be executed accurately, it is necessary to conduct comprehensive tests on each operator supported by the NPU.

[0003] Traditional NPU testing methods are mostly manual. For each set of test parameters for each operator, a test model needs to be built separately, model files and test data need to be generated, downloaded to the chip memory for running, and the results compared. Traditional methods are inefficient and difficult to cover all test parameters. In addition, due to the large number of operators, manual testing cannot achieve full coverage and there is a risk of omissions. In order to improve test efficiency and coverage, an automated testing method is needed that can automatically generate test data, automatically run tests, and automatically compare test results to ensure that operators supported by the NPU can be tested comprehensively and accurately. Summary of the invention

[0004] The purpose of the present invention is to provide a JTAG-based NPU automated testing method, which can effectively perform comprehensive automated testing on each operator supported by the NPU, save testing costs, improve testing efficiency, and ensure chip quality.

[0005] The method of the present invention comprises the following steps: S1. Select a list of operators to be tested and test parameters of each test item in each operator to be tested; S2. Obtain test parameters of a test item of an operator to be tested, and generate a test model and test data; S3. Use the NPU compiler to compile the test model into an NPU model file that can run on the NPU; S4. Import the NPU model file and test data into the test program of the PC simulator and run it; S5. Import the test program, NPU model file, test data and PC simulator output data into the chip memory through the debugger GDB (GNUDebugger) and JTAG interface, run the test program on the chip, and obtain the test result of the test item; S6. Execute steps S2 to S5 in a loop until all test items in all operators to be tested in the list of operators to be tested are tested.

[0006] Further, step S1 specifically includes: S11. In the operator list supported by the NPU, select one or more operators to be tested to form a list of operators to be tested; S12. For the selected list of operators to be tested, one or more test items are set for each operator. Each test item corresponds to a set of test parameters. The test parameters include: data dimension information, number of quantization bits, and operator private attributes.

[0007] Further, step S2 specifically includes: S21. According to the determined list of operators to be tested and the test parameters of each test item in each operator, obtain the test parameters of a test item in one of the operators to be tested; S22. Generate corresponding test data and test model according to the determined operator to be tested and test parameters; The test data is generated by the random number function of the Numpy library and saved as a binary file; The test model is built using the TensorFlow or PyTorch machine learning platform, and the model file of the corresponding machine learning platform is generated.

[0008] Further, step S3 specifically includes: S31. Generate a compilation configuration file required by the NPU compiler according to the test parameters. The compilation configuration file includes the path of the model file generated by the machine learning framework, the model input node name, the data dimension information corresponding to the model input node, and the generated NPU model file name and format; S32. The NPU compiler reads the compilation configuration file and compiles the test model into a binary NPU model file that can run on the NPU. The NPU model file contains: instructions, weights, and temporary data size.

[0009] Further, step S4 specifically includes: S41. Load the test data generated in step S2 and the NPU model file generated in step S3 on the PC simulator; S42. Run the test program on the PC simulator to obtain the model output results, and save the output results into a binary file.

[0010] Further, step S5 specifically includes: S51. Import the test program and test data generated by S2, the NPU model file generated by step S3, and the PC simulator output data generated by step S4 into the chip memory through the GDB and JTAG interfaces; S52. When the CPU in the chip runs the test program, the NPU in the chip is called to run the NPU model file, and the model output result is obtained after the NPU runs; The CPU compares the output result of the model with the output result of the PC simulator in step S4. If the results are the same, the test item passes the test, otherwise the test fails; S53. After the program is finished running, exit GDB.

[0011] Further, step S6 specifically includes: S61. According to each test item in each operator to be tested in the list of operators to be tested generated in step S1, determine whether there is a new test item to be tested; S62. If there are new test items to be tested, return to step S2 to continue execution, otherwise end the test.

[0012] The method of the present invention automatically generates test data and test models, runs them on a PC simulator to obtain output results, then imports the test data, test models and output results of the PC simulator into the chip, runs the model with the NPU, and compares the output results with those of the PC simulator, so as to comprehensively test various operators supported by the NPU and improve test efficiency. On the other hand, through automated testing, the interference of human factors is reduced, and the accuracy and reliability of the test are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a simplified flow chart of the present invention; Figure 2 is an example diagram of generating a model file in the present invention; Figure 3 It is a flow chart of loading, running and exiting a program through GDB and JTAG interface of the present invention. DETAILED DESCRIPTION

[0014] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be noted that the accompanying drawings are only used for illustrative purposes and cannot be understood as limiting this patent. At the same time, the present invention can be implemented in various forms and should not be limited by the embodiments described herein. The following embodiments are provided to make the present invention easier to understand and more completely presented to relevant technicians in the field.

[0015] like Figure 1 As shown, a JTAG-based NPU automated testing method is specifically: S1. Select a list of operators to be tested and test parameters of each test item in each operator to be tested; S11. In the operator list supported by the NPU, select one or more operators to be tested to form a list of operators to be tested; For example, select Add and Conv2D operators as operators to be tested; S12. For the selected list of operators to be tested, one or more test items are set for each operator. Each test item corresponds to a set of test parameters. The test parameters include: data dimension information, number of quantization bits, and operator private attributes.

[0016] For example, the Add operator contains three test items, and the test parameters of each test item are: Test Item 0: SHAPE:

[1000] QUANT_BITS: 16 Test Item 1: SHAPE: [1,16,16,64] QUANT_BITS: 16 Test Item 2: SHAPE: [2,1,1,200] QUANT_BITS: 16 The Conv2D operator contains 2 test items, and the test parameters of each test item are: Test Item 0: IN_HEIGHT: 10 IN_WIDTH: 10 IN_CHANNEL: 16 OUT_CHANNEL: 32 BATCH: 1 FILTER_HEIGHT: 1 FILTER_WIDTH: 1 PADDING: VALID QUANT_BITS: 8 Test Item 1: IN_HEIGHT: 8 IN_WIDTH: 8 IN_CHANNEL: 64 OUT_CHANNEL: 16 BATCH: 2 FILTER_HEIGHT: 3 FILTER_WIDTH: 3 PADDING: SAME QUANT_BITS: 8 S2. Obtain test parameters of a test item of an operator to be tested, and generate a test model and test data; S21. According to the determined list of operators to be tested and the test parameters of each test item in each operator, obtain the test parameters of a test item in one of the operators to be tested; for example, select the Add operator as the operator to be tested, and select test item 0: SHAPE:

[1000] QUANT_BITS: 16 as the test item parameter to be tested; S22. Generate corresponding test data and test model according to the determined operator to be tested and test parameters; The test data is generated by the random number function of the Numpy library and saved as a binary file; for example, use the numpy.random.uniform function of Numpy to generate 1000 random data between -1 and 1 as input data and save it as the in_data.bin file.

[0017] The test model is built using the TensorFlow or PyTorch machine learning platform, and the model file of the corresponding machine learning platform is generated. For example, use TensorFlow as the machine learning platform, build a test model, and export the TensorFlow model file: model.pb.

[0018] S3. Use the NPU compiler to compile the test model into an NPU model file that can run on the NPU.

[0019] S31. Generate the compilation configuration file required by the NPU compiler according to the test parameters. The compilation configuration file includes the path of the model file generated by the machine learning framework, the model input node name, the data dimension information corresponding to the model input node, and the generated NPU model file name and format; for example, the specific content of the compilation configuration file config.yaml is: INPUT_OPS: data:

[1000] MODEL_FILE: model.pb OUTPUT_OPS: [result] OUTPUT_FILE: model.bin OUTPUT_TYPE: binary S32. The NPU compiler reads the compilation configuration file and compiles the test model into a binary NPU model file that can run on the NPU. The NPU model file contains: instructions, weights, and temporary data size. For example, Figure 2As shown, the input files are model.pb generated by S22 and config.yaml written by S31. Run the compiler: npu_compileconfig.yaml to generate the model.bin NPU model file.

[0020] S4. Import the NPU model file and test data into the test program of the PC simulator and run it; S41. Load the test data generated in step S2 and the NPU model file generated in step S3 on the PC simulator; for example, the NPU test model is model.bin, the test data is in_data.bin, compile the test program on the PC simulator, and generate an executable file main.elf.

[0021] S42. Run the test program on the PC simulator to obtain the model output result, and save the output result as a binary file. For example, run the test model executable program, . / main.elf, and save the output result in pc_out_data.bin.

[0022] S5. Import the test program, NPU model file, test data and PC simulator output data into the chip memory through the debugger GDB (GNUDebugger) and JTAG interface, and run the test program on the chip. Figure 3 As shown, the steps are as follows:

[0023] S51. Import the test program and the test data generated by S2, the NPU model file generated by step S3, and the PC simulator output data generated by step S4 into the chip memory through the GDB and JTAG interfaces; for example, the NPU test model is model.bin, the memory address to be accessed in the program is 0x10000000, the test data is in_data.bin, the memory address to be accessed in the program is 0x10010000, the PC simulator output data is pc_out_data.bin, the memory address to be accessed in the program is 0x10020000, and the test program executable file is main.elf. Import them all into the memory through JTAG.

[0024] Add in the .gdbinit script: target remote 127.0.0.1:1025 load restore model.bin binary 0x10000000 restore in_data.bin binary 0x10010000 restore pc_out_data.bin binary 0x10020000 Taking the riscv64 tool chain as an example, execute riscv64-unknown-elf-gdb main.elf, and the tool chain will automatically execute the .gdbinit script.

[0025] S52. When the CPU in the chip runs the test program, the NPU in the chip is called to run the NPU model file, and the model output result is obtained after the NPU runs; The CPU compares the model output result with the output result of the PC simulator in step S4. If the results are the same, the test item passes the test, otherwise the test fails.

[0026] For example, in the .gdbinit script of S51, add: continue. When the .gdbinit script runs, the program will automatically start running. Run the test model in the program to get the model output result, and compare it with the expected result of pc_out_data.bin generated by S42. If the result is consistent, [Add case0] TEST PASSED is printed through the serial port, indicating that the Add operator test item 0 test passed; otherwise, [Add case0] TEST FAILED is printed, indicating that the test failed.

[0027] S53. After the program is finished running, exit GDB.

[0028] For example, add quit in the .gdbinit script of S52; when the .gdbinit script is running, GDB will automatically exit after the program is finished.

[0029] S6. Execute steps S2 to S5 in a loop until all test items in all operators to be tested in the list of operators to be tested are tested.

[0030] S61. According to each test item in each operator to be tested in the list of operators to be tested generated in step S1, determine whether there is a new test item to be tested; for example, after running Add operator test item 0, continue to run Add operator test item 1, Add operator test item 2, Conv2D operator test item 0, Conv2D operator test item 1; S62. If there are new test items to be tested, return to step S2 to continue execution, otherwise end the test.

[0031] For example, after running 3 test items of Add and 2 test items of Conv2D, the test ends. Check the test results. If TEST PASSED is printed for all test items, the final test result is considered to be passed; otherwise, the test fails.

Claims

1. A JTAG-based NPU automated testing method, characterized in that: The details are as follows: S1. Select a list of operators to be tested and test parameters of each test item in each operator to be tested; S2. Obtain test parameters of a test item of an operator to be tested, and generate a test model and test data; S3. Use the NPU compiler to compile the test model into an NPU model file that can run on the NPU; S4. Import the NPU model file and test data into the test program of the PC simulator and run it; S5. Import the test program, NPU model file, test data and PC simulator output data into the chip memory through the debugger GDB and JTAG interface, run the test program on the chip, and obtain the test result of the test item; S6. Execute steps S2 to S5 in a loop until all test items in all operators to be tested in the list of operators to be tested are tested.

2. The JTAG-based NPU automated testing method according to claim 1, characterized in that: Step S1 specifically includes: S11. In the operator list supported by the NPU, select one or more operators to be tested to form a list of operators to be tested; S12. For the selected list of operators to be tested, one or more test items are set for each operator. Each test item corresponds to a set of test parameters. The test parameters include: data dimension information, number of quantization bits, and operator private attributes.

3. The JTAG-based NPU automated testing method according to claim 1, characterized in that: Step S2 specifically includes: S21. According to the determined list of operators to be tested and the test parameters of each test item in each operator, obtain the test parameters of a test item in one of the operators to be tested; S22. Generate corresponding test data and test model according to the determined operator to be tested and test parameters; The test data is generated by the random number function of the Numpy library and saved as a binary file; The test model is built using the TensorFlow or PyTorch machine learning platform, and the model file of the corresponding machine learning platform is generated.

4. The JTAG-based NPU automated testing method according to claim 1, characterized in that: Step S3 specifically includes: S31. Generate a compilation configuration file required by the NPU compiler according to the test parameters. The compilation configuration file includes the path of the model file generated by the machine learning framework, the model input node name, the data dimension information corresponding to the model input node, and the generated NPU model file name and format; S32. The NPU compiler reads the compilation configuration file and compiles the test model into a binary NPU model file that can run on the NPU. The NPU model file contains: instructions, weights, and temporary data size.

5. The JTAG-based NPU automated testing method according to claim 1, characterized in that: Step S4 specifically includes: S41. Load the test data generated in step S2 and the NPU model file generated in step S3 on the PC simulator; S42. Run the test program on the PC simulator to obtain the model output results, and save the output results into a binary file.

6. The JTAG-based NPU automated testing method according to claim 1, characterized in that: Step S5 specifically includes: S51. Import the test program and test data generated by S2, the NPU model file generated by step S3, and the PC simulator output data generated by step S4 into the chip memory through the GDB and JTAG interfaces; S52. When the CPU in the chip runs the test program, the NPU in the chip is called to run the NPU model file, and the model output result is obtained after the NPU runs; The CPU compares the output result of the model with the output result of the PC simulator in step S4. If the results are the same, the test item passes the test, otherwise the test fails; S53. After the program is finished running, exit GDB.

7. The JTAG-based NPU automated testing method according to claim 1, characterized in that: Step S6 specifically includes: S61. According to each test item in each operator to be tested in the list of operators to be tested generated in step S1, determine whether there is a new test item to be tested; S62. If there are new test items to be tested, return to step S2 to continue execution, otherwise end the test.