Safe starting system and method based on heterogeneous multi-core SoC chip

Abstract

The invention belongs to the technical field of SoC chips, and relates to a safety starting system and method based on a heterogeneous multi-core SoC chip, and the system comprises a safety subsystem, a heterogeneous processor module, a shared memory module and a safety starting system bus. The security subsystem, the heterogeneous processor module and the shared memory module communicate through a security starting system bus, the heterogeneous processor module comprises heterogeneous processors, and the heterogeneous processors are started according to guidance of a security core; the shared memory module is used for storing instructions required when the heterogeneous processors are started; the security subsystem comprises a security core, a security algorithm module, an exclusive memory module, a security subsystem bus and a security subsystem DMA (Direct Memory Access); the exclusive memory module comprises an ROM (Read Only Memory) and an RAM (Random Access Memory). According to the invention, the problem of inter-chip low-speed interconnection caused by an external trusted module technology is solved, meanwhile, the security risk caused by exposure of an inter-chip bus is reduced, and the delay and bandwidth performance is enhanced.

Description

Technical Field

[0001] The present invention belongs to the technical field of SoC chips and relates to a secure startup system and method based on a heterogeneous multi-core SoC chip. Background Art

[0002] Nowadays, more and more processing cores with different architectures are integrated into SoC chips to meet the current rich application requirements. However, there are many security issues in the startup process of heterogeneous multi-core systems, such as the risk of network attacks, malware tampering with the boot loader, and malicious damage to code data.

[0003] The traditional approach is to use an external trusted platform module, such as STMicroelectronics' SEFASE TPM chip, to place TPM technology as a separate chip module on the motherboard to achieve secure boot. However, the main disadvantage of this approach is that it does not provide a third party with an isolated execution environment, and only acts as a secure slave device. Once the system is compromised, the TPM module is easily bypassed. Summary of the invention

[0004] In order to solve the defects existing in the prior art, the present invention proposes a secure boot system based on a heterogeneous multi-core SoC chip, including a security subsystem, a heterogeneous processor module, a shared memory module and a secure boot system bus. The security subsystem, the heterogeneous processor module and the shared memory module communicate through the secure boot system bus, wherein the heterogeneous processor module includes various heterogeneous processors, and each heterogeneous processor is started according to the guidance of the security core; the shared memory module is used to store the instructions required for the startup of each heterogeneous processor; the security subsystem includes a security core, a security algorithm module, an exclusive memory module, a security subsystem bus and a security subsystem DMA, the exclusive memory module includes ROM and RAM, the security core or the security subsystem DMA can access various peripherals and storage space of the SoC chip, and the heterogeneous processors cannot access the internal space of the security subsystem.

[0005] The present invention also proposes a secure boot method based on a heterogeneous multi-core SoC chip, comprising the following steps:

[0006] Step 1: The system powers on the safety core and each heterogeneous processor, the safety core releases reset, and each heterogeneous processor is in reset state;

[0007] Step 2: The security core starts up. The security core runs the first-level bootloader program in the ROM, loads the configuration parameters related to the security core, and transfers the second-level bootloader program in the FLASH to the RAM of the security subsystem. Then, the second-level bootloader program stored in the RAM is transferred to the security algorithm module through the security subsystem DMA, and the security core starts the HASH operation.

[0008] Step 3: The expected value of the HASH operation and the secondary bootloader program are stored in RAM. After the HASH operation is completed, the security core compares the HASH operation value with the expected value:

[0009] If the HASH operation value is not equal to the expected value, the verification fails, and the security core transfers the backup program of the secondary bootloader program from another address range of FLASH to the security subsystem RAM and re-executes the HASH operation;

[0010] If the HASH operation value is equal to the expected value, the verification is passed and the security subsystem continues to guide the heterogeneous processors to start;

[0011] Step 4: The security core transfers the verified secondary bootloader program of each heterogeneous processor to the startup address corresponding to the shared memory module, and releases the reset of each heterogeneous processor. Each heterogeneous processor jumps to the startup address to run, and each heterogeneous processor completes the secure startup.

[0012] The present invention solves the problem of low-speed interconnection between chips caused by external trusted module technology, while reducing the security risks caused by inter-chip bus exposure and enhancing latency and bandwidth performance. The present invention can prevent the device from being attacked by network power and thus face the risk of malicious damage to key technical parameters, communication protocols, core sensitive information, etc. The present invention can meet the current rich application needs and provide platform security services. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a system structure diagram of the present invention;

[0014] Figure 2 The figure is a flow chart of the method of the present invention. DETAILED DESCRIPTION

[0015] In order to better understand the purpose, technical solution and function of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings, but the present invention can be implemented in a variety of different ways as defined and covered by the claims. The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention, and the exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention.

[0016] In a specific embodiment of the present invention, Figure 1As shown, the present invention proposes a secure boot system based on a heterogeneous multi-core SoC chip, the secure boot system includes a security subsystem, a heterogeneous processor module, a shared memory module, and a secure boot system bus, etc. The security subsystem, the heterogeneous processor module and the shared memory module communicate through the secure boot system bus. The heterogeneous processor module includes various heterogeneous processors, and each heterogeneous processor is started according to the guidance of the security core. The shared memory module is used to store the instructions required for each heterogeneous processor to start.

[0017] The security subsystem includes a security core, a security algorithm module, an exclusive memory module, a security subsystem bus, and a security subsystem DMA, etc. The exclusive memory module includes ROM, RAM, etc. Among them, the security core or the security subsystem DMA can access the peripherals and storage space of the SoC chip, but the heterogeneous processors on the SoC chip cannot access the internal space of the security subsystem, which further guides the secure startup of multiple processors.

[0018] In the secure boot system of the present invention, the secure core in the secure subsystem releases reset, and a first-level bootloader program is stored in the ROM, and the secure core is first started from the ROM. Then the second-level bootloader program stored in the secure subsystem RAM is transferred to the secure algorithm module through DMA, and then the secure algorithm module verifies the startup program of each heterogeneous processor, and transfers the verified program to the shared memory module on the secure boot system bus, guides each heterogeneous processor to start, releases reset one by one, and guides each heterogeneous processor to jump to the address corresponding to the corresponding startup control register to achieve trusted startup.

[0019] In a specific embodiment of the present invention, Figure 2 As shown, based on the above secure boot system, the present invention proposes a secure boot method based on a heterogeneous multi-core SoC chip, and the specific steps include:

[0020] Step 1: The system is powered on, and the safety core is reset. The system powers on the safety core and each heterogeneous processor. The safety core is reset first, and each heterogeneous processor is in a reset state.

[0021] Step 2: The secure core starts. The secure core runs the first-level bootloader program in the ROM, loads configuration parameters related to the secure core, such as DMA paths, and then transfers the second-level bootloader program in the FLASH outside the SoC chip to the secure subsystem RAM.

[0022] Then, the secondary bootloader program stored in the security subsystem RAM is transferred to the security algorithm module through DMA, and the HASH operation is started to judge the integrity and authenticity of the secondary bootloader startup program.

[0023] Step 3: The security core starts the HASH operation. The expected value of the HASH operation and the secondary bootloader program are stored in the security subsystem RAM. After the HASH operation is completed, the security core compares the HASH operation value with the expected value. If the HASH operation value is not equal to the expected value, the verification fails. The security core transfers the backup program of the secondary bootloader program from another address range of the FLASH to the security subsystem RAM, and then transfers it to the security algorithm module to re-execute the HASH operation; if the HASH operation value is equal to the expected value, the verification passes, and the security subsystem continues to guide the heterogeneous processors to start.

[0024] Step 4: Each heterogeneous processor starts up. The security core transfers the verified programs of each heterogeneous processor to the startup address corresponding to the shared memory module, and releases the reset of each heterogeneous processor. Each heterogeneous processor jumps to the address to run, and each heterogeneous processor completes the secure startup.

[0025] The present invention has the following beneficial technical effects:

[0026] 1. Suitable for heterogeneous multi-core SoC platforms, the security subsystem is integrated into the SoC chip, interconnected with various heterogeneous processors through an on-chip bus bridge, and the security subsystem is used to ensure the secure startup of various heterogeneous processors.

[0027] 2. The security subsystem of the present invention can access various peripherals and storage space of the SoC chip, but the heterogeneous processors of the SoC chip cannot access the exclusive parts of the security subsystem, that is, the necessary exclusive resources are allocated to the security subsystem in terms of hardware resources.

[0028] 3. Determine the startup mode of the security core and each heterogeneous processor respectively. The security core is powered on unconditionally to start up, first complete the initialization of its exclusive part, and provide security services for each heterogeneous processor. Then guide each heterogeneous processor to start up, and the security subsystem measures the program to achieve trusted startup.

[0029] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art may make various changes or modifications within the scope of the claims, which should all be included in the protection scope of the present invention.

Claims

1. A secure boot system based on a heterogeneous multi-core SoC chip, characterized in that: It includes a security subsystem, a heterogeneous processor module, a shared memory module and a secure boot system bus. The security subsystem, the heterogeneous processor module and the shared memory module communicate through the secure boot system bus. The heterogeneous processor module includes various heterogeneous processors, and each heterogeneous processor is started according to the guidance of the security core; the shared memory module is used to store the instructions required for the startup of each heterogeneous processor; the security subsystem includes a security core, a security algorithm module, an exclusive memory module, a security subsystem bus and a security subsystem DMA. The exclusive memory module includes ROM and RAM. The security core or the security subsystem DMA can access various peripherals and storage space of the SoC chip, and the heterogeneous processors cannot access the internal space of the security subsystem.

2. A secure startup method based on the system of claim 1, characterized in that: The steps include: Step 1: The system powers on the safety core and each heterogeneous processor, the safety core releases reset, and each heterogeneous processor is in reset state; Step 2: The security core starts up. The security core runs the first-level bootloader program in the ROM, loads the configuration parameters related to the security core, and transfers the second-level bootloader program in the FLASH to the RAM of the security subsystem. Then, the secondary bootloader program stored in RAM is transferred to the security algorithm module through the security subsystem DMA, and the security core starts the HASH operation; Step 3: The expected value of the HASH operation and the secondary bootloader program are stored in RAM. After the HASH operation is completed, the security core compares the HASH operation value with the expected value: If the HASH operation value is not equal to the expected value, the verification fails, and the security core transfers the backup program of the secondary bootloader program from another address range of FLASH to the security subsystem RAM and re-executes the HASH operation; If the HASH operation value is equal to the expected value, the verification is passed and the security subsystem continues to guide the heterogeneous processors to start; Step 4: The security core transfers the verified secondary bootloader program of each heterogeneous processor to the startup address corresponding to the shared memory module, and releases the reset of each heterogeneous processor. Each heterogeneous processor jumps to the startup address to run, and each heterogeneous processor completes the secure startup.

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