Instruction processing method and device, computer equipment, readable storage medium and program product

Abstract

The invention relates to an instruction processing method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: when a shading program in a graphics processor executes a calculation instruction of a special function, obtaining a calculation instruction code corresponding to the calculation instruction; obtaining a target offset address and a target range of the Taylor lookup table by taking the calculation instruction code as an index; obtaining a target Taylor lookup table according to the target offset address and the target range; and determining a calculation result of the special function according to the target Taylor lookup table. By means of the method, the calculation process of the special function can be simplified, and the read-write period duration is shortened.

Description

Technical Field

[0001] The present application relates to the technical field of image instruction processing, and in particular to an instruction processing method, apparatus, computer equipment, computer-readable storage medium and computer program product. Background Art

[0002] Graphics Processing Unit (GPU) is widely used in large-scale data computing due to its excellent parallel computing capabilities. The essence of computer computing is binary computing, so GPU is good at binary multiplication and addition operations, shift operations, Boolean operations, etc. When faced with the explosive growth of special functions, GPU faces considerable challenges.

[0003] At present, the commonly used special function processing method on GPU is to use Taylor SeriesExpansion to approximate the value of special functions. It is necessary to pre-calculate the Taylor lookup table of each special function and store the intermediate results in the hardware; when calculating, the intermediate results are obtained from the Taylor lookup table as needed, and simple multiplication and addition operations are performed to approximate the special function. Although the existing methods are simple to calculate and have fast reading speed, they can only calculate a few basic special functions. When faced with more complex special functions, although several basic special functions can be used to construct them, the operation is complicated and the read and write cycle time is long. Summary of the invention

[0004] Based on this, it is necessary to provide an instruction processing method, apparatus, computer device, computer-readable storage medium and computer program product that can reduce the read and write time cycle in response to the above technical problems.

[0005] In a first aspect, the present application provides an instruction processing method, the method comprising:

[0006] When the shader program in the graphics processor executes a calculation instruction of a special function, obtaining a calculation instruction code corresponding to the calculation instruction;

[0007] Using the calculation instruction code as an index, obtaining a target offset address and a target range of a Taylor lookup table;

[0008] Obtaining a target Taylor lookup table according to the target offset address and the target range;

[0009] The calculation result of the special function is determined according to the target Taylor lookup table.

[0010] In one embodiment, before acquiring the target Taylor lookup table according to the target offset address and the target range, the method includes:

[0011] Obtain an instruction set, wherein the instruction set includes a plurality of instructions; each instruction carries an instruction code; the instruction code is determined when the compiler calls a shading program; and the instruction set is generated based on the running of the shading program;

[0012] Acquire a target instruction from the instruction set, and a target instruction code corresponding to the target instruction; the target instruction represents a calculation instruction of a special function;

[0013] Obtaining a Taylor lookup table for each target instruction encoding;

[0014] The target instruction is encoded as a row index, and the offset address and range of each Taylor lookup table are associated with the corresponding Taylor lookup table.

[0015] In one embodiment, the offset address and range of the Taylor lookup table are stored in a register, and the Taylor lookup table is stored in a buffer; the buffer is determined based on a storage unit;

[0016] Using the calculation instruction code as an index, obtaining the target offset address and target range of the Taylor lookup table includes:

[0017] Using the calculation instruction code as an index, obtaining a target offset address and a target range of a Taylor lookup table from the register;

[0018] Accordingly, obtaining a target Taylor lookup table according to the target offset address and the target range includes:

[0019] The target Taylor lookup table is obtained from the buffer according to the target offset address and the target range.

[0020] In one embodiment, determining the calculation result of the special function according to the target Taylor lookup table includes:

[0021] When the index of the special function satisfies the target range, obtaining a first parameter from the target Taylor lookup table;

[0022] Determining a second parameter according to a target search index of the index; the target search index represents an index of a variable that is closest to the index;

[0023] Based on the first parameter and the second parameter, a calculation result of the special function is determined.

[0024] In one embodiment, before acquiring the target Taylor lookup table according to the target offset address and the target range, the method includes:

[0025] Obtain an instruction set, wherein the instruction set includes a plurality of instructions; each instruction carries an instruction code; the instruction code is determined when a compiler calls a shading program; and the instruction set is generated based on the shading program;

[0026] Acquire a target instruction from the instruction set, and a target instruction code corresponding to the target instruction; the target instruction represents a calculation instruction of a special function;

[0027] The obtained Taylor lookup table of each target instruction encoding is stored in the main memory, and the virtual address of each Taylor lookup table stored in the main memory is obtained;

[0028] Using the target instruction code as an index, the virtual address of each Taylor lookup table and the range of the Taylor lookup table are associated and stored;

[0029] Determine the main memory physical address of the offset address of each Taylor lookup table according to the virtual address of each Taylor lookup table;

[0030] The main memory physical address of the offset address and the serial number of the cache line of the first cache are stored in association, wherein the cache line of the first cache stores a portion of the Taylor lookup table.

[0031] In one embodiment, the range of the Taylor lookup table is associated with a virtual address of the Taylor lookup table stored in a main memory and stored in a register, and the target offset address and target range of the Taylor lookup table are obtained by using the calculation instruction code as an index, including:

[0032] Using the calculation instruction code of the special function as an index, obtaining the target virtual address and the target range of the Taylor lookup table from a register;

[0033] Determine the main memory physical address of the target offset address of the Taylor lookup table according to the target virtual address;

[0034] According to the target offset address and the target range, a target Taylor lookup table is obtained, including:

[0035] In the case where the index of the special function satisfies the target range, a hit test is performed according to the main memory physical address of the target offset address; if a hit occurs, a target Taylor lookup table corresponding to the calculation instruction encoding is read from the cache line of the first cache;

[0036] If there is a miss, the target Taylor lookup table corresponding to the computing instruction encoding is read from the main memory, and the target Taylor lookup table is returned to the first cache.

[0037] In one embodiment, reading the target Taylor lookup table corresponding to the computing instruction encoding from the main memory and returning the target Taylor lookup table to the first cache includes:

[0038] In the case of a hit in the second cache, a target Taylor lookup table corresponding to the calculation instruction is read from the second cache, the target Taylor lookup table is returned to the first cache, and stored in a cache line of the first cache; the data stored in the second cache is a subset of the data stored in the main memory; the data stored in the first cache is a subset of the data stored in the second cache;

[0039] In case of a hit miss in the second cache, the target Taylor lookup table corresponding to the calculation instruction encoding is read from the main memory, and the target Taylor lookup table is returned to the first cache and stored in a cache line of the first cache.

[0040] In one embodiment, determining the main memory physical address of the target offset address of the Taylor lookup table according to the target virtual address includes:

[0041] Calculate an offset address according to the target virtual address of the Taylor lookup table;

[0042] The main memory physical address of the target offset address of the Taylor lookup table is determined according to the target virtual address and the offset address.

[0043] In one embodiment, determining the calculation result of the special function according to the target Taylor lookup table includes:

[0044] Determine the group value of the special function according to the mapping relationship between the index of the first cache and the group value and the obtained index of the special function;

[0045] determining a first parameter of the target Taylor lookup table according to the group of values;

[0046] Determine a second parameter according to a target search index of the index; the target search index represents an index closest to the index;

[0047] Based on the first parameter and the second parameter, a calculation result of the special function is determined.

[0048] In one embodiment, the first parameter includes a constant term coefficient, a linear term coefficient, and a quadratic term coefficient; the second parameter includes a polynomial; and determining the calculation result of the special function based on the first parameter and the second parameter includes:

[0049] Determining an initial calculation result of the special function based on the constant term coefficient, the linear term coefficient, the quadratic term coefficient and the polynomial;

[0050] According to the normalization rules, the mantissa value, the order value, and the sign bit in the initial calculation result are corrected;

[0051] The calculation result of the special function is obtained according to the modified mantissa value, order value, and sign bit.

[0052] In one embodiment, the special function includes a first special function and a second special function; before acquiring the target Taylor lookup table according to the target offset address and the target range, the method includes:

[0053] Obtain an instruction set, wherein the instruction set includes a plurality of instructions; each instruction carries an instruction code; the instruction code is determined when the compiler calls a shading program; and the instruction set is generated based on the running of the shading program;

[0054] Acquire a target instruction from the instruction set, and a target instruction code corresponding to the target instruction; the target instruction represents a calculation instruction of a special function;

[0055] If the target instruction code is a first target instruction code, obtaining a first Taylor lookup table for each of the first target instruction codes; the first target instruction code represents a code of a calculation instruction of a first special function;

[0056] Using the first target instruction code as a row index, associating the offset address and range of each first Taylor lookup table with the corresponding first Taylor lookup table;

[0057] If the target instruction code is a second target instruction code, storing the obtained second Taylor lookup table of each second target instruction code in the main memory, and obtaining the virtual address of each second Taylor lookup table stored in the main memory; the second target instruction code represents the code of the calculation instruction of the second special function;

[0058] Using the second target instruction code as an index, the virtual address of each second Taylor lookup table and the range of the second Taylor lookup table are associated and stored;

[0059] Determine the main memory physical address of the offset address of each second Taylor lookup table according to the virtual address of each second Taylor lookup table;

[0060] The main memory physical address of the offset address and the serial number of the cache line of the first cache are stored in association, wherein the cache line of the first cache stores a portion of the Taylor lookup table.

[0061] In one embodiment, the special function includes a first special function and a second special function; the offset address and range of a first Taylor lookup table corresponding to the first special function are stored in a register; the first Taylor lookup table is stored in a buffer; the buffer is determined based on a storage unit; the range of a second Taylor lookup table corresponding to the second special function is associated with a virtual address of the second Taylor lookup table stored in a main memory and is stored in a register;

[0062] Before obtaining the target offset address and target range of the Taylor lookup table using the calculation instruction encoding as an index, it also includes:

[0063] Determining the type of the computing instruction code corresponding to the computing instruction;

[0064] Using the calculation instruction encoding as an index, obtain the target offset address and target range of the Taylor lookup table, including:

[0065] If the calculation instruction code is the first calculation instruction code, using the first calculation instruction code as an index, obtaining the target offset address and target range of the first Taylor lookup table from the register;

[0066] Accordingly, according to the target offset address and the target range, the target Taylor lookup table is obtained, including:

[0067] According to the target offset address and the target range, acquiring the first Taylor lookup table from the buffer as a target Taylor lookup table;

[0068] If the computing instruction code is a second computing instruction code, using the second computing instruction code as an index, obtaining a target virtual address and a target range of the second Taylor lookup table from the register;

[0069] Determine a main memory physical address of a target offset address of the second Taylor lookup table according to the target virtual address;

[0070] Accordingly, according to the target offset address and the target range, the target Taylor lookup table is obtained, including:

[0071] In the case where the argument of the second special function satisfies the target range, a hit test is performed according to the main memory physical address of the target offset address; if a hit occurs, the second Taylor lookup table corresponding to the second calculation instruction encoding is read from the cache line of the first cache as the target Taylor lookup table;

[0072] If there is no hit, the second Taylor lookup table corresponding to the second computing instruction encoding is read from the main memory as the target Taylor lookup table, and the target Taylor lookup table is returned to the first cache; wherein the first cache is determined based on the storage unit.

[0073] In a second aspect, the present application further provides an instruction processing device, the device comprising:

[0074] A first acquisition module, configured to acquire a calculation instruction code corresponding to a calculation instruction of a special function when a shader program in a graphics processor executes the calculation instruction of the special function;

[0075] A second acquisition module is used to acquire a target offset address and a target range of a Taylor lookup table by using the calculation instruction code as an index;

[0076] A third acquisition module, configured to acquire a target Taylor lookup table according to the target offset address and the target range;

[0077] A calculation module is used to determine the calculation result of the special function according to the target Taylor lookup table.

[0078] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0079] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0080] In a fifth aspect, the present application also provides a computer program product, including a computer program, which implements the steps of the above method when executed by a processor.

[0081] In the above instruction processing method, device, computer equipment, computer-readable storage medium and computer program product, each special function corresponds to a Taylor lookup table. When executing the calculation of the special function, the calculation result of the special function is directly determined by the parameters in the corresponding Taylor lookup table, thereby avoiding the need to split the special function into sub-special functions with Taylor lookup tables when there is no corresponding Taylor lookup table for a special function. Each time a sub-special function is executed, several cycles are required to read, calculate, store data, etc. of the calculation instruction. Compared with splitting the special function into sub-special functions with Taylor lookup tables, the data is read, calculated and stored when the sub-special functions are executed, thereby simplifying the calculation process of the special function and reducing the length of the read and write cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0083] FIG1 is a schematic diagram of a method for processing instructions executed within a GPU in one embodiment;

[0084] FIG2 is a schematic flow chart of an instruction processing method in one embodiment;

[0085] FIG3 is a flow chart of steps before obtaining a target Taylor lookup table in one embodiment;

[0086] FIG4 is a schematic diagram of an embodiment of an offset address and range associated with a corresponding Taylor lookup table;

[0087] FIG5 is a schematic diagram of a process for obtaining a target Taylor lookup table in one embodiment;

[0088] FIG6 is a schematic diagram of a method for processing instructions executed within a GSFU based on a buffer in one embodiment;

[0089] FIG7 is a schematic diagram of a flow chart of determining a calculation result of a special function in one embodiment;

[0090] FIG8 is a flow chart of steps before obtaining a target Taylor lookup table in another embodiment;

[0091] FIG9 is a schematic diagram of an offset address and range associated with a corresponding Taylor lookup table in another embodiment;

[0092] FIG10 is a schematic diagram of a process for obtaining a target Taylor lookup table in another embodiment;

[0093] FIG11 is a schematic diagram of a cache-based GSFU internal execution instruction processing method in another embodiment;

[0094] FIG12 is a schematic diagram of a process of returning a target Taylor lookup table to a first cache in one embodiment;

[0095] FIG13 is a schematic diagram of a flow chart of determining a main memory physical address of a target offset address in one embodiment;

[0096] FIG14 is a schematic diagram of a flow chart of determining a calculation result of a special function in another embodiment;

[0097] FIG15 is a flow chart showing steps before obtaining a target Taylor lookup table in another embodiment;

[0098] FIG16 is a schematic diagram of a process for obtaining a target Taylor lookup table in another embodiment;

[0099] FIG17 is a block diagram of a structure of an instruction processing device in one embodiment;

[0100] FIG. 18 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0101] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0102] The relevant special function calculation method is to use Taylor expansion to approximate the special function.

[0103] The Taylor expansion formula is as follows:

[0104] Formula (1)

[0105] Formula (2)

[0106] Among them, record , , and for:

[0107] Formula (3)

[0108] Formula (4)

[0109] Formula (5)

[0110] Formula (6)

[0111] It is the distance Recent search indexes, , , It is the Taylor lookup table value that needs to be calculated in advance and saved in the hardware.

[0112] The above formula is recorded as:

[0113] Formula (7)

[0114] Therefore, when calculating special functions, we only need to calculate and , and then read the value of the Taylor lookup table , , , we can transform complex special function operations into a series of simple multiplication and addition operations.

[0115] The Taylor expansion method is a widely used method because it is simple to operate, more in line with the characteristics of computer calculations, and can read memory data quickly and get results quickly. However, due to the objective condition of limited memory space, only a few sets of Taylor expansion lookup tables can be stored in the memory, so this method supports very few types of special functions.

[0116] The following is the Taylor expansion method to calculate function process.

[0117] Formula (8)

[0118] Formula (9)

[0119] Formula (10)

[0120] Through the above steps, we can know that function If the traditional Taylor expansion method is used for calculation, it needs to be divided into three steps, of which the first step [Formula (8)] and the third step [Formula (10)] are special functions. Each time a special function is executed, several cycles are required to read the instruction data, calculate the data, store the data, etc. Therefore, the time overhead of using the traditional Taylor expansion method is very large, and it is no longer suitable for complex special function calculations.

[0121] Therefore, the instruction processing method provided in the embodiment of the present application can be applied to a graphics processing unit GPU, as shown in FIG1 , which is an internal schematic diagram of a GPU.

[0122] The program running in the GPU is called a shader. After the shader is called by the compiler, the content in the shader is converted from a high-level programming language into a set of instructions that can be executed on the GPU. Each shader contains several instructions, and multiple shaders can be run simultaneously in the GPU. The execution of instructions in the GPU depends on the thread bundle (Wave), which reads, writes and calculates in a single instruction stream multiple data stream (SIMD). Each thread bundle contains multiple sub-units (lanes), each of which stores a set of data for calculation or to be saved, and the sub-units execute in parallel. We often operate instructions in SIMD32 or SIMD64, that is, the thread bundle contains 32 or 64 parallel computing sub-units. There are two important modules inside the GPU - the thread scheduling unit (WVC, WaveRegister Controller) and the computing unit (ALU, Arithmetic and Logic Unit). The thread scheduling unit is responsible for managing and scheduling thread bundles. Each thread bundle executes one instruction. After confirming the instruction executed by the current thread bundle, the thread scheduling unit sends the thread bundle to the computing unit. The computing unit is the arithmetic logic unit, which is the core component for executing instructions and is responsible for arithmetic operations, logical operations, bit operations, jump judgment and other operations.

[0123] In an exemplary embodiment, as shown in FIG2 , a method for processing instructions is provided, which is described by taking the method applied to a GPU as an example, and includes the following steps S202 to S208 . Among them:

[0124] Step S202: when the shader in the graphics processor executes a calculation instruction of a special function, a calculation instruction code corresponding to the calculation instruction is obtained.

[0125] Each shader program contains several instructions, and the GPU can run multiple shaders at the same time. Instructions can be calculation instructions for common functions or calculation instructions for special functions. Each calculation instruction generates a corresponding calculation instruction code through the compiler.

[0126] Optionally, when the shader program in the graphics processor GPU starts to execute, the execution scheduling unit WVC in FIG1 selects to execute a certain thread bundle and sends the thread bundle to the computing unit ALU. If the current thread bundle is executing a computing instruction of a special function, the computing unit ALU will send the instruction code opcode of the special function to the general function processing unit GSFU, and accordingly, the GPU receives the computing instruction code opcode corresponding to the computing instruction through the general function processing unit GSFU.

[0127] Step S204, using the calculation instruction code as an index, obtaining the target offset address and target range of the Taylor lookup table.

[0128] Optionally, the GPU uses the calculation instruction code opcode as an index through the general purpose function processing unit GSFU to search and obtain the target offset address base and target range range of the Taylor lookup table in the register reg.

[0129] Step S206, obtaining a target Taylor lookup table according to the target offset address and the target range.

[0130] Among them, each special function corresponds to a Taylor lookup table.

[0131] Optionally, the GPU obtains the target Taylor lookup table at a corresponding position in the storage unit SRAM according to the target offset address base and the target range range through the general function processing unit GSFU.

[0132] Step S208, determining the calculation result of the special function according to the target Taylor lookup table.

[0133] Optionally, after the GPU obtains the target Taylor lookup table through the general function processing unit GSFU, it obtains the corresponding items in the table, such as the first parameter abc, the second parameter ; Then, multiplication and addition operations are performed according to formula (7) to calculate the result of the special function, which is returned to the calculation unit ALU to output the calculation result.

[0134] In the above instruction processing method, each special function corresponds to a Taylor lookup table. When executing the calculation of the special function, the calculation result of the special function is directly determined by the parameters in the corresponding Taylor lookup table, thereby avoiding the need to split the special function into sub-special functions with Taylor lookup tables when there is no corresponding Taylor lookup table for a special function. Each time a sub-special function is executed, several cycles are required to read, calculate, store, etc. the data of the calculation instruction. Compared with the existing method of splitting the special function into sub-special functions with Taylor lookup tables, the data is read, calculated and stored when the sub-special functions are executed, thereby simplifying the calculation process of the special function and reducing the length of the read and write cycle.

[0135] In an exemplary embodiment, as shown in FIG3 , before obtaining the target Taylor lookup table according to the target offset address and the target range, steps S302 to S308 are included. Among them:

[0136] Step S302, obtaining an instruction set, the instruction set including a plurality of instructions; each instruction carries an instruction code; the instruction code is determined when the compiler calls the shading program; the instruction set is generated based on the running of the shading program.

[0137] Optionally, the GPU analyzes the instructions in the shader program through a compiler to generate an instruction set, which includes a number of instructions, wherein the instructions may include ordinary calculation instructions, shift operation instructions, logical operation instructions, jump instructions, data transfer instructions, input and output instructions, etc. When the GPU calls the shader program through the compiler, it determines the instruction code of each instruction in the instruction set.

[0138] Step S304, obtaining a target instruction and a target instruction code corresponding to the target instruction from the instruction set; the target instruction represents a calculation instruction of a special function.

[0139] Optionally, the GPU captures special function instructions in the instruction set as target instructions through the driver, and obtains their instruction encoding opcodes, such as , ,…, wait.

[0140] Step S306, obtaining a Taylor lookup table for each target instruction code.

[0141] Optionally, the GPU sets a Taylor lookup table corresponding to each target instruction code through a driver.

[0142] Step S308 , using the target instruction code as a row index, associating the offset address and range of each Taylor lookup table with the corresponding Taylor lookup table.

[0143] Optionally, the GPU stores the offset address and range of each Taylor lookup table in the register reg through the driver; then the offset address base and range range of each Taylor lookup table and the corresponding Taylor lookup table are loaded into the storage unit SRAM; this step requires driver assistance and consumes a certain number of cycles to implement. Finally, the offset addresses and ranges loaded into the register are associated with the Taylor lookup tables loaded into the SRAM to establish a one-to-one mapping relationship. As shown in Figure 4, the left side is the register reg and the right side is the SRAM; the storage order of the two is based on the opcode and corresponds one to one. Table[0]_base and Table[0]_range correspond to gsfu_taylor_table[0], and so on. Therefore, the base and range of each special function correspond to a Taylor lookup table. When taking the lookup table of a special function, first use the opcode as the row index to find the corresponding base and range in reg, and then get the lookup table in SRAM through the base and range.

[0144] It should be noted that the input of the special function It is a floating point value. When calculating, it needs to be divided into three parts: sign, exp, and manti according to the IEEE-754 rule. Among them, sign refers to the sign bit, which is 0 for positive numbers and 1 for negative numbers; exp refers to the exponent value, and an offset needs to be added during actual calculation; manti refers to the mantissa value, which represents the part after the decimal point in binary. When it is a single-precision floating point number (32 bits), sign, exp, and manti have 1, 8, and 23 bits respectively, and the offset of exp is 127. Its expression is written as:

[0145] Formula (11)

[0146] For example, 10.25 is represented by:

[0147] Converted to binary, this is 0 10000010 010010000000000000000000.

[0148] That is, sign=0, exp= ,manti= .

[0149] The index value of the Taylor lookup table is the first several bits of manti, that is, .

[0150] In this embodiment, by statically loading the Taylor lookup table of each special function contained in the instructions of the shading program shader into the storage space SRAM in advance, and establishing a one-to-one mapping relationship with the base and range, when the calculation instructions of the special function can be executed again, each special function can correspond to a Taylor lookup table, and the calculation parameters can be directly obtained from the Taylor lookup table in the storage space, thereby simplifying the calculation process of the special function and reducing the read and write cycle time.

[0151] Continuing with the above embodiment, as shown in FIG5 , the offset address and range of the Taylor lookup table are stored in a register, and the Taylor lookup table is stored in a buffer; the buffer is determined based on a storage unit; using the calculation instruction code as an index, obtaining the target offset address and target range of the Taylor lookup table, including step S502:

[0152] Step S502, using the calculation instruction code as an index, obtaining the target offset address and target range of the Taylor lookup table from the register.

[0153] Optionally, the GPU calls a special function in the shader program Shader. , calculate the instruction encoding opcode.

[0154] The GPU uses the special function processing unit GSFU to use opcode as the row index to find the target offset address base and the target range range in the register reg; assuming that the target offset address base and the target range range occupy R bytes, The length is R bytes and all 1. The specific calculation formulas for base and range are as follows:

[0155] Formula (12)

[0156] Formula (13)

[0157] Accordingly, according to the target offset address and the target range, the target Taylor lookup table is obtained, including step S504:

[0158] Step S504, obtaining a target Taylor lookup table from the buffer according to the target offset address and the target range.

[0159] The buffer buffer is determined based on the storage unit SRAM.

[0160] Optionally, the GPU uses the storage unit SRAM as a buffer.

[0161] Optionally, look up the corresponding Taylor lookup table in the buffer buffer according to the target offset address base and the target range range , the formula is as follows:

[0162] Formula (14)

[0163] As shown in FIG6 , the GPU calculates the instruction encoding opcode as a row index, searches for base and range from register reg, and searches for the corresponding target Taylor lookup table in SRAM according to base and range.

[0164] In this embodiment, by using the storage unit SRAM as a buffer, the processing speed can be improved when processing more complex special functions.

[0165] Continuing from the previous embodiment, as shown in FIG. 7 , the calculation result of the special function is determined according to the target Taylor lookup table, including steps S702 to S706:

[0166] Step S702: when the index of the special function satisfies the target range, obtain the first parameter from the target Taylor lookup table.

[0167] Optionally, the GPU determines whether the special function index is within the target range through the special function processing unit GSFU. If the special function index x is less than or equal to range, the special function Taylor lookup table is used. Find the three first parameters abc: , , , they are stored in groups of three on the same line, and each variable occupies S bytes; It is all 1s with a length of S bytes. The search formula for the first parameter abc is:

[0168] Formula (15)

[0169] Formula (16)

[0170] Formula (17)

[0171] If the index x of the special function is greater than range , it means the index is out of bounds and an error marker is returned.

[0172] Step S704, determine the second parameter according to the target search index of the index.

[0173] The target lookup index represents the index of the variable that is closest to the index.

[0174] Optionally, the special function is indexed as x and the target search index is X0. When the variable After that, the GPU calculates the Cvt module according to formula (6) , and then calculate The value of .

[0175] Formula (6)

[0176] Then the GPU uses the module Cvt to and Substitute it into formula (7) to calculate the final result:

[0177] Formula (7)

[0178] Step S706: Determine a calculation result of the special function based on the first parameter and the second parameter.

[0179] Optionally, the GPU determines the initial calculation result of the special function based on the constant term coefficient a, the first-order term coefficient b, the second-order term coefficient c and the polynomial through the general special function processing unit GSFU; corrects the mantissa value, order value and sign bit in the initial calculation result according to the normalization rule; and obtains the calculation result of the special function based on the corrected mantissa value, order value and sign bit. Because floating-point numbers have the requirement of normalization, that is, the first digit after the decimal point must be 1, after obtaining the calculation result of the second parameter, the mantissa value manti is shifted left by several bits to meet the normalization requirement, and the order value exp is subtracted from the corresponding number of bits of the mantissa value manti left shift, and the processed sign bit sign, order value exp and mantissa value manti are assembled into a complete float number and returned to the calculation unit ALU.

[0180] As shown in Figure 6, the left side is the preprocessing stage and the right side is the execution stage.

[0181] In the preprocessing stage:

[0182] The GPU analyzes the instructions in the shader program through the compiler and generates an instruction set. The instruction set includes several instructions, including ordinary calculation instructions, shift operation instructions, logical operation instructions, jump instructions, data transfer instructions, input and output instructions, etc. When the GPU calls the shader program through the compiler, it determines the instruction encoding of each instruction in the instruction set. The GPU grabs the special function instructions in the instruction set as the target instruction through the driver, and obtains their instruction encoding opcode, such as , ,…, Etc. The GPU sets the Taylor lookup table corresponding to each target instruction code through the driver. The GPU stores the offset address and range of each Taylor lookup table in the register reg through the driver; then the offset address base and range range of each Taylor lookup table and the corresponding Taylor lookup table are loaded into the storage unit SRAM; this step requires driver assistance and consumes a certain number of cycles to implement. Finally, the offset addresses and ranges loaded into the register are associated with the Taylor lookup tables loaded into the SRAM to establish a one-to-one mapping relationship. As shown in Figure 4, the left side is the register reg and the right side is the SRAM; the storage order of the two is based on the opcode and corresponds one to one. Table[0]_base and Table[0]_range correspond to gsfu_taylor_table[0], and so on. Therefore, the base and range of each special function correspond to a Taylor lookup table. When taking the lookup table of a special function, first use opcode as the row index to find the corresponding base and range in reg, and then get the lookup table in SRAM through base and range.

[0183] During the execution phase:

[0184] The GPU calls a special function in the shader program Shader. , calculate the instruction code opcode. The GPU uses the special function processing unit GSFU to use opcode as the row index to find the target offset address base and target range range in the register reg. According to the target offset address base and target range range, the corresponding Taylor lookup table is found in the buffer buffer. The GPU uses the special function processing unit GSFU to determine whether the special function index is within the target range. If the special function index x is less than or equal to range, the special function's Taylor lookup table is used. Find the three first parameters abc: , , , they are stored in groups of three on the same line, and each variable occupies S bytes; The index x of the special function is greater than the range , it means the index is out of bounds and an error flag is returned. The index of the special function is x, and the target search index is X0. When the variable After that, the GPU calculates the Cvt module according to formula (6) , and then calculate Then the GPU uses the module Cvt to and Substitute into formula (7) to calculate the final result. Because floating-point numbers have a normalization requirement, that is, the first digit after the decimal point must be 1, so after obtaining the calculation result of the second parameter, the mantissa value manti is shifted left by a number of bits to meet the normalization requirement, and at the same time, the exponent value exp is subtracted from the corresponding number of bits of the mantissa value manti left shift, and the processed sign bit sign, exponent value exp, and mantissa value manti are assembled into a complete float number and returned to the calculation unit ALU.

[0185] In this embodiment, the calculation result of the special function can be quickly determined by reading the first parameter and the second parameter from the target Taylor table.

[0186] In another exemplary embodiment, as shown in FIG8 , before obtaining the target Taylor lookup table according to the target offset address and the target range, steps S802 to S812 are included. In which:

[0187] Step S802, obtaining an instruction set, the instruction set including a plurality of instructions; each instruction carries an instruction code; the instruction code is determined when the compiler calls the shading program; the instruction set is generated based on the shading program.

[0188] Optionally, the GPU analyzes the instructions in the shader program through a compiler to generate an instruction set, which includes a number of instructions, wherein the instructions may include ordinary calculation instructions, shift operation instructions, logical operation instructions, jump instructions, data transfer instructions, input and output instructions, etc. When the GPU calls the shader program through the compiler, it determines the instruction code of each instruction in the instruction set.

[0189] Step S804, obtaining a target instruction and a target instruction code corresponding to the target instruction from the instruction set; the target instruction represents a calculation instruction of a special function.

[0190] Optionally, the GPU captures special function instructions in the instruction set as target instructions through the driver, and obtains their instruction encoding opcodes, such as , ,…, wait.

[0191] Step S806, storing the obtained Taylor lookup table of each target instruction code in the main memory, and obtaining the virtual address of each Taylor lookup table stored in the main memory.

[0192] The VA address is the virtual address of the main memory, which is usually 40 bits, unlike the buffer-based storage method, whose base is the offset address in the SRAM, which is usually only a few bits.

[0193] Optionally, the GPU sets reg and the corresponding Taylor lookup table through the driver, and copies the lookup table to the external main memory.

[0194] Step S808 , using the target instruction code as an index, the virtual address of each Taylor lookup table and the range of the Taylor lookup table are associated and stored.

[0195] Optionally, the GPU driver driver uses the target instruction code as an index to associate the virtual address VA of each Taylor lookup table with the range range of the Taylor lookup table and stores them in the register reg, as shown in FIG9 .

[0196] Step S810, determining the main memory physical address of the offset address of each Taylor lookup table according to the virtual address of each Taylor lookup table.

[0197] Optionally, when the input to a special function is When it is a single-precision floating point number (32 bits), the GPU obtains the 1-bit sign, the 8-bit exponent exp, and the 23-bit mantissa manti. The offset address (VA+manti) is calculated based on the VA address. Based on the virtual address and the offset address, the main memory physical address of the offset address is calculated.

[0198] Step S812, storing the main memory physical address of the offset address and the serial number of the cache line of the first cache in association with each other, wherein the cache line of the first cache stores a portion of the Taylor lookup table.

[0199] When SRAM is used as cache, it is divided into m cache rows, each row has 2K bits of data, which is used to record the actual The data is shown in Figure 9.

[0200] Optionally, the GPU associates the main memory physical address of the offset address and the number of the cache line of the first cache and stores it in a tag tag. The tag tag stores the status information of the cache line of the first cache, including: Valid (1 bit) whether the current cache line has valid data, the main memory physical address base_addr (40 bits) corresponding to the cache line, whether the current line is locked (1 bit), whether the cache line hits hit / miss info (4 bits), and the cache line number cache_id. In this way, the mapping relationship between reg and SRAM as cache is constructed.

[0201] In this embodiment, the cache-based approach does not require the driver to do additional work, and the required partial data of the lookup table can be dynamically loaded during execution, and more types of special functions can be supported.

[0202] In an exemplary embodiment, as shown in FIG10 , the range of the Taylor lookup table is associated with the virtual address of the Taylor lookup table stored in the main memory and stored in the register, and the target offset address and the target range of the Taylor lookup table are obtained by using the calculation instruction encoding as an index, including steps S1002 to S1004:

[0203] Step S1002, using the calculation instruction code of the special function as an index, obtaining the target virtual address and target range of the Taylor lookup table from the register.

[0204] Optionally, the GPU obtains the target virtual address base and target range range of the Taylor lookup table from the register reg by using the calculation instruction encoding of the special function as an index through the special function processing unit GSFU.

[0205] Step S1004, determining the main memory physical address of the target offset address of the Taylor lookup table according to the target virtual address.

[0206] Optionally, the GPU calculates an offset address (VA+manti) according to the VA address through a special function processing unit GSFU, and calculates a main memory physical address of the offset address, that is, a main memory physical address of a cache line in the first cache, according to the virtual address and the offset address.

[0207] Accordingly, according to the target offset address and the target range, the target Taylor lookup table is obtained, including steps S1006 to S1008:

[0208] Step S1006, when the index of the special function meets the target range, a hit test is performed according to the main memory physical address of the target offset address; if a hit occurs, the target Taylor lookup table corresponding to the calculation instruction code is read from the cache line of the first cache.

[0209] Optionally, before doing the hit / miss test, you need to check the actual records in the cache. Data, take out the VA virtual address and range from register reg, if , then it means that the index is out of bounds, and the error flag error is returned. Otherwise, that is, X is less than or equal to range, the main memory physical address corresponding to the cache line is calculated according to the VA address and the offset address, that is, the main memory physical address base_addr of the offset address, and then a hit / miss test is performed from the Tag. If hit (search hit), read the data from the SRAM. At this time, the SRAM is used as the first cache, that is, read the target Taylor lookup table corresponding to the calculation instruction encoding from the cache line in the first cache.

[0210] Step S1008: If there is no hit, the target Taylor lookup table corresponding to the calculation instruction code is read from the main memory, and the target Taylor lookup table is returned to the first cache.

[0211] Optionally, if there is a miss, the corresponding content needs to be read from the main memory, the Taylor lookup table is searched, and it is returned to the SRAM, and then returned from the SRAM to the ALU. It should be noted that at this time, the SRAM is used as the first cache.

[0212] As shown in Figure 11, the GPU calculates the offset address (VA+manti) based on the VA address, and reads the information of each cache in the SRAM from the Tag based on this, and performs a hit / miss test in the Hit Test module. If it is a hit (search hit), read the data from the SRAM, otherwise it is a miss (search miss), and it is necessary to enter the miss queue, read the corresponding content from the main memory, search the Taylor lookup table, return it to the SRAM, and then return it from the SRAM to the ALU.

[0213] In this embodiment, the cache-based approach does not require the driver to do additional work, and the required partial data of the lookup table can be dynamically loaded during execution, and more types of special functions can be supported. When there is no special function in the cache, it can be obtained from the main memory.

[0214] In an exemplary embodiment, as shown in FIG12 , a target Taylor lookup table corresponding to a computing instruction encoding is read from a main memory, and the target Taylor lookup table is returned to a first cache, including steps S1202 to S1204:

[0215] Step S1202, in the case of a hit in the second cache, read the target Taylor lookup table corresponding to the calculation instruction from the second cache, return the target Taylor lookup table to the first cache, and store it in the cache line of the first cache; the data stored in the second cache is a subset of the data stored in the main memory; the data stored in the first cache is a subset of the data stored in the second cache.

[0216] The data storage capacity of the first cache is smaller than that of the second cache, which is smaller than that of the main memory. However, in terms of read and write speed, the read and write speed of the first cache is greater than that of the second cache, which is greater than that of the main memory.

[0217] Optionally, as shown in Figure 11, if the first cache misses, the least recently used algorithm LRU is used to select a cache line from the tag and lock it, enter the miss-fifo queue, and query the second cache L2 cache for data information. If the hit is in the L2 cache, the data is read and written back to the locked cache line in the SRAM in the GSFU, and the tag information is updated and the cache line is unlocked.

[0218] Step S1204, in the case of a hit miss in the second cache, the target Taylor lookup table corresponding to the calculation instruction encoding is read from the main memory, and the target Taylor lookup table is returned to the first cache and stored in the cache line of the first cache.

[0219] Alternatively, if the second cache L2 cache also misses, the data has to be read from the external main memory and returned.

[0220] In this embodiment, the target Taylor lookup table is obtained more quickly through two-level cache, so that the calculation result of the special function is calculated quickly, thereby improving the calculation efficiency.

[0221] In an exemplary embodiment, as shown in FIG13 , determining the main memory physical address of the target offset address of the Taylor lookup table according to the target virtual address includes steps S1302 to S1304:

[0222] Step S1302, calculating the offset address according to the target virtual address of the Taylor lookup table.

[0223] Step S1304, determining the main memory physical address of the target offset address of the Taylor lookup table according to the target virtual address and the offset address.

[0224] Optionally, the GPU calculates the offset address (VA+manti) according to the target virtual address of the Taylor lookup table, and calculates the main memory physical address of the offset address according to the VA address and the offset address, that is, the main memory physical address corresponding to the cache line, which can be recorded as base_addr.

[0225] In an exemplary embodiment, as shown in FIG14 , determining the calculation result of the special function according to the target Taylor lookup table includes steps S1402 to S1408:

[0226] Step S1402: Determine the group value of the special function according to the mapping relationship between the index of the first cache and the group value and the obtained index of the special function.

[0227] Because a cache row is 2K bits, and a set of a, b, and c only has a few dozen bits, a cache row can store multiple sets of values. is the group index. The storage order in each group is shown in Figure 9, from left to right. , a, b, c, where Occupies D bits, a, b, c each occupy S bits, It is all 1s with a length of S bytes. It is all 1s with a length of D+3S bytes.

[0228] In practical applications, first extract the group value and group index ,like , then take out the current group value :

[0229] Formula (18)

[0230] Formula (19)

[0231] Step S1404: determining a first parameter of the target Taylor lookup table according to the group value.

[0232] Then extract the values ​​of a, b, and c:

[0233] Formula (20)

[0234] Formula (21)

[0235] Formula (22)

[0236] Step S1406, determine the second parameter according to the target search index of the index.

[0237] The target search index represents the index closest to the distance index.

[0238] Optionally, the special function is indexed as x and the target search index is X0. When the variable After that, the GPU calculates the Cvt module according to formula (6) , and then calculate The value of .

[0239] Formula (6)

[0240] Then the GPU uses the module Cvt to and Substitute it into formula (7) to calculate the final result:

[0241] Formula (7)

[0242] Step S1408: Determine a calculation result of the special function based on the first parameter and the second parameter.

[0243] The first parameter includes the constant term coefficient a, the linear term coefficient b and the quadratic term coefficient c; the second parameter includes the polynomial ; Based on the first parameter and the second parameter, determining the calculation result of the special function, including:

[0244] Optionally, the GPU determines the initial calculation result of the special function through the general special function processing unit GSFU based on the constant term coefficient a, the first-order term coefficient b, the second-order term coefficient c and the polynomial; corrects the mantissa value, order value and sign bit in the initial calculation result according to the normalization rule; and obtains the calculation result of the special function based on the corrected mantissa value, order value and sign bit. Because floating-point numbers have the requirement of normalization, that is, the first digit after the decimal point must be 1, after obtaining the calculation result of the special function, the mantissa value manti is shifted left by several bits to meet the normalization requirement, and the order value exp is subtracted from the corresponding number of bits of the mantissa value manti left shift, and the processed sign bit sign, order value exp and mantissa value manti are assembled into a complete float number and returned to the calculation unit ALU.

[0245] As shown in Figure 11, the left side is the preprocessing stage and the right side is the execution stage.

[0246] In the preprocessing stage:

[0247] The GPU analyzes the instructions in the shader program through the compiler and generates an instruction set. The instruction set includes several instructions, including ordinary calculation instructions, shift operation instructions, logical operation instructions, jump instructions, data transfer instructions, input and output instructions, etc. When the GPU calls the shader program through the compiler, it determines the instruction encoding of each instruction in the instruction set. It grabs the special function instructions in the instruction set as the target instructions and obtains their instruction encoding opcode, such as , ,…, etc. Set reg and the corresponding Taylor lookup table, and copy the lookup table to the external main memory. At the same time, the GPU driver uses the target instruction code as an index to associate the virtual address VA of each Taylor lookup table with the range of the Taylor lookup table and store it in the register reg. When it is a single-precision floating point number (32 bits), the GPU obtains a 1-bit sign, an 8-bit exponent, and a 23-bit mantissa. The offset address (VA+manti) is calculated based on the VA address. The main memory physical address of the offset address is calculated based on the virtual address and the offset address. When SRAM is used as a cache, it is divided into m cache rows, each with 2K bits of data, which is used to record the actual As shown in Figure 9. The GPU associates the main memory physical address of the offset address and the cache line number of the first cache into the tag tag. The tag tag stores the status information of the cache line of the first cache, including: whether the current cache line has valid data Valid (1 bit), the main memory physical address base_addr (40 bits) corresponding to the cache line, whether the current line is locked Lock (1 bit), whether the cache line hits hit / miss info (4 bits), and the cache line number cache_id. In this way, the mapping relationship between reg and SRAM as cache is constructed.

[0248] During the execution phase:

[0249] A special function is called in the shader. , the instruction is encoded as opcode. Using opcode as the row index, get the VA address of the function from Reg. When it is a single-precision floating point number (32 bits), we get the 1-bit sign bit, the 8-bit exponent value, and the 23-bit mantissa value. According to the VA address, the offset address (VA+manti) is calculated, and the information of each cache in the SRAM is read from the tag. The hit / miss test is performed in the Hit Test module. If it is a hit, it directly enters the SRAM to read the corresponding Because a row of cache is 2K bits, and a set of a, b, and c only has a few dozen bits, a row of cache can store multiple sets of values. is the group index. The storage order in each group is shown in Figure 9, from left to right. , a, b, c, where Occupies D bits, a, b, c each occupy S bits, It is all 1s with a length of S bytes. First extract the group value and index within group ,like , then take out the current group value :Then extract the values ​​of a, b, and c. If it misses, use the least recently used algorithm LRU to select a cache line from the tag and lock it, enter the miss-fifo queue, and query the second cache L2 cache for data information. If the hit is in the L2 cache, then read the data and write it back to the locked cache line in the SRAM in the GSFU, update the tag information and unlock the cache line; if the L2 cache also misses, then read the data from the external main memory (MainMemory) and return it, so as to get , , Three data, this time takes a long time. When the variable , , Then, the module Cvt is calculated according to formula (2-6) , and then calculate The values ​​of , and then they can be brought into formula (7) to calculate the final result: Because floating-point numbers have a normalization requirement, that is, the first digit after the decimal point must be 1, after obtaining the calculation result of (7), manti is shifted left by a certain number of bits to achieve the normalization requirement, and exp is subtracted from the corresponding number of bits of manti left shifted. The processed sign, exp, and manti are combined into a complete float number and returned to the calculation unit ALU. The ALU returns the result to the current thread warp.

[0250] In an optional embodiment, based on the buffer method, the data will be statically loaded into the SRAM by the driver before the kernel executes; based on the cache method, the driver only stores the VA virtual address of each special function into the register of GSFU, and performs cache hit / miss judgment when the kernel executes. If it misses, it will dynamically search from the external cache and main memory. Both methods can be used as GSFU scheduling implementation strategies, and can be selected according to the actual work tasks.

[0251] In another embodiment, the buffer-based approach and the cache-based approach can be combined, and a portion of the SRAM is divided out as a buffer and another portion is divided out as a cache. The combination of the buffer-based approach and the cache-based approach also includes a preprocessing stage and an execution stage.

[0252] As shown in FIG. 15 , in the preprocessing stage, the special functions include a first special function and a second special function; before obtaining the target Taylor lookup table according to the target offset address and the target range, steps S1502 to S1516 are included, wherein:

[0253] Step S1502, obtaining an instruction set, the instruction set including a number of instructions; each instruction carries an instruction code; the instruction code is determined when the compiler calls the shading program; the instruction set is generated based on the running of the shading program.

[0254] Optionally, the GPU analyzes the instructions in the shader program through a compiler to generate an instruction set, which includes a number of instructions, wherein the instructions may include ordinary calculation instructions, shift operation instructions, logical operation instructions, jump instructions, data transfer instructions, input and output instructions, etc. When the GPU calls the shader program through the compiler, it determines the instruction code of each instruction in the instruction set.

[0255] Step S1504, obtaining a target instruction and a target instruction code corresponding to the target instruction from the instruction set.

[0256] Among them, the target instruction represents the calculation instruction of the special function.

[0257] Optionally, the GPU captures special function instructions in the instruction set as target instructions through the driver, and obtains their instruction encoding opcodes, such as , ,…, wait.

[0258] Optionally, some basic special functions, such as reciprocal, square root, exponential function, logarithmic function, trigonometric function, etc., are used as the first special function, and their corresponding instruction encoding opcodes, such as GSFU 00 , GSFU 01 ,…,GSFU 0n-1 Etc. Some complex special functions, such as sigmoid function, relu function, softmax function, etc. and their variant functions are used as the second special function, and their corresponding instruction encoding opcodes, such as GSFU 10 , GSFU 11 ,…,GSFU 1n-1 wait.

[0259] Step S1506: if the target instruction code is a first target instruction code, obtain a first Taylor lookup table of each first target instruction code.

[0260] The first target instruction code represents the code of the calculation instruction of the first special function.

[0261] Optionally, the GPU obtains a Taylor lookup table for each target instruction code, including a first Taylor lookup table for the target instruction code corresponding to the first special function instruction, and a second Taylor lookup table for the target instruction code corresponding to the second special function instruction.

[0262] Step S1508 , using the first target instruction code as a row index, associating the offset address and range of each first Taylor lookup table with the corresponding first Taylor lookup table.

[0263] Optionally, the GPU stores the offset address and range of each first Taylor lookup table in the register reg through the driver; then the offset address base and range range of each first Taylor lookup table and the corresponding first Taylor lookup table are loaded into the storage unit SRAM; this step requires driver-assisted execution and consumes a certain number of cycles to implement. Finally, the offset addresses and ranges loaded into the register are associated with the first Taylor lookup tables loaded into the SRAM to establish a one-to-one mapping relationship. As shown in Figure 4, the left side is the register reg and the right side is the SRAM; the storage order of the two is based on the opcode and corresponds one to one. Table[0]_base and Table[0]_range correspond to gsfu_taylor_table[0], and so on. Therefore, the base and range of each first special function correspond to a first Taylor lookup table. When taking the first Taylor lookup table of a first special function, first use the opcode as the row index to find the corresponding base and range in reg, and then get the first Taylor lookup table in SRAM through the base and range.

[0264] The above steps S1506 to S1508 are for storing the first Taylor lookup table in a buffer manner.

[0265] Step S1510, if the target instruction code is the second target instruction code, store the obtained second Taylor lookup table of each second target instruction code in the main memory, and obtain the virtual address of each second Taylor lookup table stored in the main memory.

[0266] The second target instruction code represents the code of the calculation instruction of the second special function. The VA address is the virtual address of the main memory. It is usually 40 bits, unlike the buffer-based storage method, whose base is the offset address in the SRAM, which is usually only a few bits.

[0267] Optionally, the GPU sets reg and a corresponding second Taylor lookup table through a driver, copies the second Taylor lookup table to an external main memory, and obtains a virtual address VA at which each second Taylor lookup table is stored in the main memory.

[0268] Step S1512: using the second target instruction code as an index, the virtual address of each second Taylor lookup table is associated with the range of the second Taylor lookup table and stored.

[0269] Optionally, the GPU driver driver uses the second target instruction code as an index to associate the virtual address VA of each second Taylor lookup table with the range range of the second Taylor lookup table and store them in the register reg, as shown in FIG9 .

[0270] Step S1514, determining the main memory physical address of the offset address of each second Taylor lookup table according to the virtual address of each second Taylor lookup table.

[0271] Optionally, when the input of the second special function When it is a single-precision floating point number (32 bits), the GPU obtains the 1-bit sign, the 8-bit exponent exp, and the 23-bit mantissa manti. The offset address (VA+manti) is calculated based on the VA address. Based on the virtual address and the offset address, the main memory physical address of the offset address is calculated.

[0272] Step S1516, storing the main memory physical address of the offset address and the serial number of the cache line of the first cache in association with each other, wherein the cache line of the first cache stores a portion of the Taylor lookup table.

[0273] When SRAM is used as cache, it is divided into m cache rows, each row has 2K bits of data, which is used to record the actual The data is shown in Figure 9.

[0274] Optionally, the GPU associates the main memory physical address of the offset address and the number of the cache line of the first cache and stores it in a tag tag. The tag tag stores the status information of the cache line of the first cache, including: Valid (1 bit) whether the current cache line has valid data, the main memory physical address base_addr (40 bits) corresponding to the cache line, whether the current line is locked (1 bit), whether the cache line hits hit / miss info (4 bits), and the cache line number cache_id. In this way, the mapping relationship between reg and SRAM as cache is constructed.

[0275] The above steps S1510 to S1516 are for storing the second Taylor lookup table in a cache manner.

[0276] In this embodiment, a first Taylor lookup table corresponding to the first special function is stored in a buffer in advance through a cache-based method and a buffer-based method; a second Taylor lookup table corresponding to the second special function is stored in a corresponding cache. Part of the data of the required Taylor lookup table can be dynamically loaded during execution.

[0277] In another embodiment, during the execution phase, as shown in FIG16 , the special function includes a first special function and a second special function; the offset address and range of the first Taylor lookup table corresponding to the first special function are stored in a register; the first Taylor lookup table is stored in a buffer; the buffer is determined based on a storage unit; the range of the second Taylor lookup table corresponding to the second special function is associated with a virtual address of the second Taylor lookup table stored in the main memory and is stored in the register;

[0278] Before obtaining the target offset address and target range of the Taylor lookup table by using the calculation instruction code as an index, step S1602 is also included:

[0279] Step S1602, determining the type of the computing instruction code corresponding to the computing instruction.

[0280] Optionally, the GPU may pre-determine the type of the computing instruction encoding, and determine whether the type of the computing instruction encoding is determined based on the first special function computing instruction or based on the second special function computing instruction.

[0281] The first special function is such as the inverse, square root, exponential function, logarithmic function, trigonometric function, etc., and its corresponding instruction encoding opcode is GSFU. 00 , GSFU 01 ,…,GSFU 0n-1 The second special function such as sigmoid function, relu function, softmax function and their variant functions are used as their corresponding instruction encoding opcode, such as GSFU 10 , GSFU 11 ,…,GSFU 1n-1 wait.

[0282] Using the calculation instruction code as an index, obtaining the target offset address and target range of the Taylor lookup table includes steps S1604, S1608 and S1610. Wherein:

[0283] Step S1604: if the calculation instruction code is the first calculation instruction code, the target offset address and target range of the first Taylor lookup table are obtained from the register using the first calculation instruction code as an index.

[0284] Optionally, if the computing instruction code is a first computing instruction code, the GPU uses the general function processing unit GSFU to encode the first computing instruction opcode 0x As the index, the target offset address base and the target range range of the first Taylor lookup table are searched and obtained in the register reg.

[0285] Accordingly, according to the target offset address and the target range, a target Taylor lookup table is obtained, including step S1606, according to the target offset address and the target range, obtaining a first Taylor lookup table from the buffer as the target Taylor lookup table.

[0286] The buffer is determined based on the storage unit SRAM, and a part of the SRAM is used as the buffer.

[0287] Optionally, the GPU uses the storage unit SRAM as a buffer.

[0288] Optionally, the corresponding first Taylor lookup table is searched in the buffer buffer according to the target offset address base and the target range range , the formula is as follows:

[0289] Formula (14)

[0290] As shown in FIG. 4 , the GPU encodes the opcode as a row index through the first computing instruction, searches for base and range from the register reg, and searches for the corresponding target Taylor lookup table in the SRAM according to the base and range.

[0291] Step S1608: If the calculation instruction code is the second calculation instruction code, the target virtual address and target range of the second Taylor lookup table are obtained from the register using the second calculation instruction code as an index.

[0292] Optionally, if the computing instruction code is the second computing instruction code, the GPU obtains the target virtual address base and target range range of the second Taylor lookup table from the register reg through the special function processing unit GSFU using the second computing instruction code of the second special function as an index.

[0293] Step S1610, determining the main memory physical address of the target offset address of the Taylor lookup table according to the target virtual address.

[0294] Optionally, the GPU calculates an offset address (VA+manti) according to the VA address through a special function processing unit GSFU, and calculates a main memory physical address of the offset address, that is, a main memory physical address of a cache line in the first cache, according to the virtual address and the offset address.

[0295] Accordingly, according to the target offset address and the target range, the target Taylor lookup table is obtained, including steps S1612 to S1614. Among them:

[0296] Step S1612, when the independent variable of the second special function meets the target range, a hit test is performed according to the main memory physical address of the target offset address; if a hit occurs, the second Taylor lookup table corresponding to the second calculation instruction encoding is read from the cache line of the first cache as the target Taylor lookup table.

[0297] The first cache is determined based on a storage unit SRAM, and a part of the SRAM is used as cache.

[0298] Optionally, before performing the hit / miss test, it is necessary to Data, take out the VA virtual address and range from register reg, if , then it means that the index is out of bounds, and the error flag error is returned. Otherwise, that is, X is less than or equal to range, the main memory physical address corresponding to the cache line is calculated according to the VA address and the offset address, that is, the main memory physical address base_addr of the offset address, and then a hit / miss test is performed from the Tag. If hit (search hit), read the data from the SRAM. At this time, the SRAM is used as the first cache, that is, read the target Taylor lookup table corresponding to the calculation instruction encoding from the cache line in the first cache.

[0299] Step S1614, if there is no hit, read the second Taylor lookup table corresponding to the second computing instruction code from the main memory as the target Taylor lookup table, and return the target Taylor lookup table to the first cache; wherein the first cache is determined based on the storage unit.

[0300] Optionally, as shown in Figure 11, the GPU calculates the offset address (VA+manti) based on the VA address, reads the information of each cache in the SRAM from the Tag based on this, and performs a hit / miss test in the Hit Test module. If it is a hit (search hit), read the data from the SRAM, otherwise it is a miss (search miss), it is necessary to enter the miss queue, read the corresponding content from the main memory, search the second Taylor lookup table, return it to the SRAM, and then return it from the SRAM to the ALU.

[0301] In this embodiment, a part of the SRAM is divided out as a buffer and the other part is used as a cache. This method can not only quickly obtain results when calculating basic special functions, but also save hundreds of cycles of calculation overhead caused by existing methods when calculating complex special functions. It truly adapts to the function and allows each part of GSFU to be responsible for the calculation of various special functions more accurately. It has great flexibility while taking into account execution efficiency.

[0302] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0303] Based on the same inventive concept, the embodiment of the present application also provides an instruction processing device for implementing the instruction processing method involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more instruction processing device embodiments provided below can refer to the limitations on the instruction processing method above, and will not be repeated here.

[0304] In an exemplary embodiment, as shown in FIG. 17 , an instruction processing device is provided, including: a first acquisition module 1701, a second acquisition module 1702, a third acquisition module 1703 and a calculation module 1704, wherein:

[0305] The first acquisition module 1701 is used to acquire a calculation instruction code corresponding to a calculation instruction when a shader program in a graphics processor executes a calculation instruction of a special function.

[0306] The second acquisition module 1702 is used to acquire the target offset address and target range of the Taylor lookup table by using the calculation instruction code as an index.

[0307] The third acquisition module 1703 is used to acquire a target Taylor lookup table according to the target offset address and the target range.

[0308] The calculation module 1704 is used to determine the calculation result of the special function according to the target Taylor lookup table.

[0309] In one exemplary embodiment, an instruction processing device includes:

[0310] The first preprocessing module is used to obtain an instruction set, which includes a plurality of instructions; each instruction carries an instruction code; the instruction code is determined when the compiler calls a shading program; the instruction set is generated based on the operation of the shading program; a target instruction and a target instruction code corresponding to the target instruction are obtained from the instruction set; the target instruction represents a calculation instruction of a special function; a Taylor lookup table of each target instruction code is obtained; using the target instruction code as a row index, the offset address and range of each Taylor lookup table are associated with the corresponding Taylor lookup table.

[0311] In an exemplary embodiment, the offset address and range of the Taylor lookup table are stored in a register, and the Taylor lookup table is stored in a buffer; the buffer is determined based on the storage unit; the second acquisition module 1702 is used to obtain the target offset address and target range of the Taylor lookup table from the register using the calculation instruction code as an index;

[0312] Accordingly, the third acquisition module 1703 is used to acquire the target Taylor lookup table from the buffer according to the target offset address and the target range.

[0313] In an exemplary embodiment, the calculation module 1704 is used to obtain a first parameter from a target Taylor lookup table when the index of the special function meets the target range; determine a second parameter based on a target lookup index of the index; the target lookup index represents the index of a variable closest to the index; and determine a calculation result of the special function based on the first parameter and the second parameter.

[0314] In one exemplary embodiment, an instruction processing device includes:

[0315] The second preprocessing module is used to obtain an instruction set, which includes a number of instructions; each instruction carries an instruction code; the instruction code is determined when the compiler calls a shading program; the instruction set is generated based on the shading program; a target instruction and a target instruction code corresponding to the target instruction are obtained from the instruction set; the target instruction represents a calculation instruction of a special function; the Taylor lookup table of each target instruction code obtained is stored in the main memory, and the virtual address of each Taylor lookup table stored in the main memory is obtained; the virtual address of each Taylor lookup table and the range of the Taylor lookup table are associated and stored with the target instruction code as an index; the main memory physical address of the offset address of each Taylor lookup table is determined according to the virtual address of each Taylor lookup table; the main memory physical address of the offset address and the cache line number of the first cache are associated and stored, wherein the cache line of the first cache stores part of the Taylor lookup table.

[0316] In an exemplary embodiment, the range of the Taylor lookup table is associated with the virtual address of the Taylor lookup table stored in the main memory and is stored in the register. The second acquisition module 1702 is further used to obtain the target virtual address and the target range of the Taylor lookup table from the register by using the calculation instruction code of the special function as an index; determine the main memory physical address of the target offset address of the Taylor lookup table according to the target virtual address;

[0317] The third acquisition module 1703 is also used to perform a hit test according to the main memory physical address of the target offset address when the index of the special function meets the target range; if a hit occurs, the target Taylor lookup table corresponding to the calculation instruction code is read from the cache line of the first cache; if a miss occurs, the target Taylor lookup table corresponding to the calculation instruction code is read from the main memory, and the target Taylor lookup table is returned to the first cache.

[0318] In an exemplary embodiment, the third acquisition module 1703 is also used to, in the case of a hit in the second cache, read the target Taylor lookup table corresponding to the calculation instruction from the second cache, return the target Taylor lookup table to the first cache, and store it in the cache line of the first cache; the data stored in the second cache is a subset of the data stored in the main memory; the data stored in the first cache is a subset of the data stored in the second cache; in the case of a hit miss in the second cache, read the target Taylor lookup table corresponding to the calculation instruction encoding from the main memory, return the target Taylor lookup table to the first cache, and store it in the cache line of the first cache.

[0319] In an exemplary embodiment, the second acquisition module 1702 is further configured to calculate an offset address according to a target virtual address of the Taylor lookup table; and determine a main memory physical address of a target offset address of the Taylor lookup table according to the target virtual address and the offset address.

[0320] In an exemplary embodiment, the calculation module 1704 is also used to determine the group value of the special function based on the mapping relationship between the index and the group value of the first cache and the obtained index of the special function; determine the first parameter of the target Taylor lookup table based on the group value; determine the second parameter based on the target search index of the index; the target search index represents the index closest to the index; and determine the calculation result of the special function based on the first parameter and the second parameter.

[0321] In an exemplary embodiment, the first parameter includes a constant term coefficient, a linear term coefficient and a quadratic term coefficient; the second parameter includes a polynomial; the calculation module 1704 is also used to determine the initial calculation result of the special function based on the constant term coefficient, the linear term coefficient, the quadratic term coefficient and the polynomial; according to the normalization rule, the mantissa value, order value and sign bit in the initial calculation result are corrected; according to the corrected mantissa value, order value and sign bit, the calculation result of the special function is obtained.

[0322] Each module in the above instruction processing device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0323] In an exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be shown in FIG18. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store instruction data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, an instruction processing method is implemented.

[0324] Those skilled in the art will understand that the structure shown in FIG. 18 is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0325] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0326] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0327] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0328] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0329] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0330] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A command processing method, characterized in that: The method comprises: When the shader program in the graphics processor executes a calculation instruction of a special function, obtaining a calculation instruction code corresponding to the calculation instruction; Using the calculation instruction code as an index, obtaining a target offset address and a target range of a Taylor lookup table; Obtaining a target Taylor lookup table according to the target offset address and the target range; The calculation result of the special function is determined according to the target Taylor lookup table.

2. The method according to claim 1, characterized in that: Before acquiring the target Taylor lookup table according to the target offset address and the target range, the method includes: Obtain an instruction set, wherein the instruction set includes a plurality of instructions; each instruction carries an instruction code; the instruction code is determined when the compiler calls a shading program; and the instruction set is generated based on the running of the shading program; Acquire a target instruction from the instruction set, and a target instruction code corresponding to the target instruction; the target instruction represents a calculation instruction of a special function; Obtaining a Taylor lookup table for each target instruction encoding; The target instruction is encoded as a row index, and the offset address and range of each Taylor lookup table are associated with the corresponding Taylor lookup table.

3. The method according to claim 1, characterized in that The offset address and range of the Taylor lookup table are stored in a register, and the Taylor lookup table is stored in a buffer; The buffer is determined based on a storage unit; Using the calculation instruction code as an index, obtaining the target offset address and target range of the Taylor lookup table includes: Using the calculation instruction code as an index, obtaining a target offset address and a target range of a Taylor lookup table from the register; Accordingly, obtaining a target Taylor lookup table according to the target offset address and the target range includes: The target Taylor lookup table is obtained from the buffer according to the target offset address and the target range.

4. The method according to claim 1, characterized in that: Determining the calculation result of the special function according to the target Taylor lookup table includes: When the index of the special function satisfies the target range, obtaining a first parameter from the target Taylor lookup table; Determining a second parameter according to a target search index of the index; the target search index represents an index of a variable that is closest to the index; Based on the first parameter and the second parameter, a calculation result of the special function is determined.

5. The method according to claim 1, characterized in that Before acquiring the target Taylor lookup table according to the target offset address and the target range, the method includes: Obtain an instruction set, wherein the instruction set includes a plurality of instructions; each instruction carries an instruction code; the instruction code is determined when a compiler calls a shading program; and the instruction set is generated based on the shading program; Acquire a target instruction from the instruction set, and a target instruction code corresponding to the target instruction; the target instruction represents a calculation instruction of a special function; The obtained Taylor lookup table of each target instruction encoding is stored in the main memory, and the virtual address of each Taylor lookup table stored in the main memory is obtained; Using the target instruction code as an index, the virtual address of each Taylor lookup table and the range of the Taylor lookup table are associated and stored; Determine the main memory physical address of the offset address of each Taylor lookup table according to the virtual address of each Taylor lookup table; The main memory physical address of the offset address and the serial number of the cache line of the first cache are stored in association, wherein the cache line of the first cache stores a portion of the Taylor lookup table.

6. The method according to claim 1, characterized in that The range of the Taylor lookup table is associated with the virtual address of the Taylor lookup table stored in the main memory and stored in the register, and the target offset address and target range of the Taylor lookup table are obtained by using the calculation instruction code as an index, including: Using the calculation instruction code of the special function as an index, obtaining the target virtual address and the target range of the Taylor lookup table from a register; Determine the main memory physical address of the target offset address of the Taylor lookup table according to the target virtual address; According to the target offset address and the target range, a target Taylor lookup table is obtained, including: In the case where the index of the special function satisfies the target range, a hit test is performed according to the main memory physical address of the target offset address; if a hit occurs, a target Taylor lookup table corresponding to the calculation instruction encoding is read from the cache line of the first cache; If there is a miss, the target Taylor lookup table corresponding to the computing instruction encoding is read from the main memory, and the target Taylor lookup table is returned to the first cache.

7. The method according to claim 6, characterized in that The step of reading a target Taylor lookup table corresponding to the computing instruction encoding from the main memory and returning the target Taylor lookup table to the first cache comprises: In the case of a hit in the second cache, a target Taylor lookup table corresponding to the calculation instruction is read from the second cache, the target Taylor lookup table is returned to the first cache, and stored in a cache line of the first cache; the data stored in the second cache is a subset of the data stored in the main memory; the data stored in the first cache is a subset of the data stored in the second cache; In case of a hit miss in the second cache, the target Taylor lookup table corresponding to the calculation instruction encoding is read from the main memory, and the target Taylor lookup table is returned to the first cache and stored in a cache line of the first cache.

8. The method according to claim 6, characterized in that Determining the main memory physical address of the target offset address of the Taylor lookup table according to the target virtual address includes: Calculate an offset address according to the target virtual address of the Taylor lookup table; The main memory physical address of the target offset address of the Taylor lookup table is determined according to the target virtual address and the offset address.

9. The method according to claim 1, characterized in that: Determining the calculation result of the special function according to the target Taylor lookup table includes: Determine the group value of the special function according to the mapping relationship between the index of the first cache and the group value and the obtained index of the special function; determining a first parameter of the target Taylor lookup table according to the group of values; Determine a second parameter according to a target search index of the index; the target search index represents an index closest to the index; Based on the first parameter and the second parameter, a calculation result of the special function is determined.

10. The method according to claim 4 or 9, characterized in that: The first parameter includes a constant term coefficient, a linear term coefficient, and a quadratic term coefficient; the second parameter includes a polynomial; and determining the calculation result of the special function based on the first parameter and the second parameter includes: Determining an initial calculation result of the special function based on the constant term coefficient, the linear term coefficient, the quadratic term coefficient and the polynomial; According to the normalization rules, the mantissa value, the order value, and the sign bit in the initial calculation result are corrected; The calculation result of the special function is obtained according to the modified mantissa value, order value, and sign bit.

11. The method according to claim 1, characterized in that The special function includes a first special function and a second special function; before obtaining the target Taylor lookup table according to the target offset address and the target range, it includes: Obtain an instruction set, wherein the instruction set includes a plurality of instructions; each instruction carries an instruction code; the instruction code is determined when the compiler calls a shading program; and the instruction set is generated based on the running of the shading program; Acquire a target instruction from the instruction set, and a target instruction code corresponding to the target instruction; the target instruction represents a calculation instruction of a special function; If the target instruction code is a first target instruction code, obtaining a first Taylor lookup table for each of the first target instruction codes; the first target instruction code represents a code of a calculation instruction of a first special function; Using the first target instruction code as a row index, associating the offset address and range of each first Taylor lookup table with the corresponding first Taylor lookup table; If the target instruction code is a second target instruction code, storing the obtained second Taylor lookup table of each second target instruction code in the main memory, and obtaining the virtual address of each second Taylor lookup table stored in the main memory; the second target instruction code represents the code of the calculation instruction of the second special function; Using the second target instruction code as an index, the virtual address of each second Taylor lookup table and the range of the second Taylor lookup table are associated and stored; Determine the main memory physical address of the offset address of each second Taylor lookup table according to the virtual address of each second Taylor lookup table; The main memory physical address of the offset address and the serial number of the cache line of the first cache are stored in association, wherein the cache line of the first cache stores a portion of the Taylor lookup table.

12. The method according to claim 1, characterized in that The special function includes a first special function and a second special function; the offset address and range of the first Taylor lookup table corresponding to the first special function are stored in a register; the first Taylor lookup table is stored in a buffer; The buffer is determined based on the storage unit; the range of the second Taylor lookup table corresponding to the second special function is associated with the virtual address where the second Taylor lookup table is stored in the main memory and is stored in the register; Before obtaining the target offset address and target range of the Taylor lookup table using the calculation instruction encoding as an index, it also includes: Determining the type of the computing instruction code corresponding to the computing instruction; Using the calculation instruction encoding as an index, obtain the target offset address and target range of the Taylor lookup table, including: If the calculation instruction code is the first calculation instruction code, using the first calculation instruction code as an index, obtaining the target offset address and target range of the first Taylor lookup table from the register; Accordingly, according to the target offset address and the target range, the target Taylor lookup table is obtained, including: According to the target offset address and the target range, acquiring the first Taylor lookup table from the buffer as a target Taylor lookup table; If the computing instruction code is a second computing instruction code, using the second computing instruction code as an index, obtaining a target virtual address and a target range of the second Taylor lookup table from the register; Determine a main memory physical address of a target offset address of the second Taylor lookup table according to the target virtual address; Accordingly, according to the target offset address and the target range, the target Taylor lookup table is obtained, including: In the case where the argument of the second special function satisfies the target range, a hit test is performed according to the main memory physical address of the target offset address; if a hit occurs, the second Taylor lookup table corresponding to the second calculation instruction encoding is read from the cache line of the first cache as the target Taylor lookup table; If there is no hit, the second Taylor lookup table corresponding to the second computing instruction encoding is read from the main memory as the target Taylor lookup table, and the target Taylor lookup table is returned to the first cache; wherein the first cache is determined based on the storage unit.

13. An instruction processing device, characterized in that: The device comprises: A first acquisition module, configured to acquire a calculation instruction code corresponding to a calculation instruction of a special function when a shader program in a graphics processor executes the calculation instruction of the special function; A second acquisition module is used to acquire a target offset address and a target range of a Taylor lookup table by using the calculation instruction code as an index; A third acquisition module, configured to acquire a target Taylor lookup table according to the target offset address and the target range; A calculation module is used to determine the calculation result of the special function according to the target Taylor lookup table.

14. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 12 are implemented.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 12 are implemented.

16. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 12 are implemented.

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