Gate driving circuit, driving method thereof, display panel and display device

Abstract

The invention provides a gate driving circuit and a driving method thereof, a display panel and a display device, and relates to the technical field of display, the gate driving circuit comprises an input unit, a first output unit, a second output unit and an output control unit; wherein the control end of the first output unit is connected with a first node, and the first output unit is configured to transmit a signal of a first level end to the output end of the gate drive circuit according to an effective level signal of the first node; the control end of the second output unit is connected with a second node, and the second output unit is configured to transmit a signal of a second level end to the output end of the gate drive circuit according to an effective level signal of the second node; the input unit is configured to control the potential of a first node according to an input signal and a control signal of a clock signal end, and the output control unit is configured to control the potential of a second node according to an output signal of the input unit. Therefore, the narrow frame design of a display product can be realized.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a gate driving circuit and a driving method thereof, a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] At this stage, how to reduce the border width of display products to increase the screen-to-body ratio has become one of the technical problems that need to be solved urgently. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a gate driving circuit and a driving method thereof, a display panel and a display device, aiming to reduce the border width of the display product and increase the screen-to-body ratio of the display product.

[0005] In a first aspect, the present disclosure provides a gate driving circuit, including an input unit, a first output unit, a second output unit and an output control unit; wherein,

[0006] The control end of the first output unit is connected to the first node, and the first output unit is configured to transmit the signal of the first level end to the output end of the gate driving circuit according to the effective level signal of the first node;

[0007] The control end of the second output unit is connected to the second node, and the second output unit is configured to transmit the signal of the second level end to the output end of the gate driving circuit according to the effective level signal of the second node;

[0008] The input unit is connected to the input end, and is configured to control the potential of the first node according to the input signal of the input end and the control signal of the clock signal end. The output control unit is configured to control the potential of the second node at least according to the output signal of the input unit.

[0009] In a second aspect, based on the same inventive concept, the present disclosure provides a driving method of a gate driving circuit, which is applied to the gate driving circuit provided in the first aspect of the present disclosure, and the driving method includes:

[0010] In the first stage, under the control of the clock signal, the input unit is turned on, the first level signal at the input end is transmitted to the first node, the first output unit is controlled to be turned on and the second output unit is turned off, and the signal at the first level end is transmitted to the output end of the gate driving circuit;

[0011] In the second stage, under the control of the clock signal, the input unit is turned off, the first node maintains the level signal of the first stage, the first output unit remains turned on, the second output unit remains turned off, and the output end of the gate driving circuit keeps outputting the signal of the first level end;

[0012] In the third stage, under the control of the clock signal, the input unit is turned on, the second level signal at the input end is transmitted to the first node, the first output unit is controlled to be turned off, and the output control unit is controlled to output a valid level signal to the second node, so that the second output unit is turned on, and the signal at the second level end is transmitted to the output end of the gate driving circuit;

[0013] In the fourth stage, the signal at the input end becomes a first level signal, under the control of the clock signal, the input unit is turned off, the first node maintains the second level signal of the third stage, and the output end of the gate driving circuit maintains outputting the signal at the second level end;

[0014] In the fifth stage, under the control of the clock signal, the input unit is turned on, the first level signal at the input end is transmitted to the first node, the first output unit is controlled to be turned on and the second output unit is turned off, and the signal at the first level end is transmitted to the output end of the gate drive circuit.

[0015] In a third aspect, based on the same inventive concept, the present disclosure further provides a display panel, comprising the gate driving circuit provided in the first aspect of the present disclosure.

[0016] In a fourth aspect, based on the same inventive concept, the present disclosure further provides a display device, comprising the display panel provided in the third aspect of the present disclosure.

[0017] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0018] In the gate drive circuit and its driving method, display panel and display device provided by the present disclosure, one of the first output unit and the second output unit is turned on. When the first output unit is turned on in response to the effective level signal of the first node, the signal of the first level end is transmitted to the output end of the gate drive circuit; when the second output unit is turned on in response to the effective level signal of the second node, the signal of the second level end is transmitted to the output end of the gate drive circuit. The signals of the first level end and the second level end are one low level and the other high level. The gate drive circuit of the present disclosure introduces an input unit, and the potential of the first node can be controlled by the output signal of the input unit and the clock signal, and introduces an output control unit, which controls the potential of the second node at least according to the output signal of the input unit. Therefore, through the cooperation of the input unit, the output control unit, and the input signal and the clock signal, the first output unit and the second output unit can be controlled to be turned on in time-sharing and output a high level signal or a low level signal, which is conducive to simplifying the structure of the gate drive circuit. When the gate drive circuit is applied to a display product, it is conducive to reducing the space occupied by the gate drive circuit in the display panel, which is conducive to improving the space utilization rate of the display product. When the gate driving circuit is located in the border area of ​​the display panel, it is beneficial to reduce the border width of the display product, realize a narrow border or an ultra-narrow border design, and increase the screen-to-body ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 Shown is a circuit schematic diagram of a gate driving circuit provided by an embodiment of the present disclosure;

[0022] Figure 2 FIG. 1 is a schematic diagram showing a case where the gate driving circuit in the embodiment of the present disclosure is applied to a display panel;

[0023] Figure 3 Another circuit diagram of a gate driving circuit provided by an embodiment of the present disclosure is shown;

[0024] Figure 4 Shown is a detailed structural diagram of a gate driving circuit provided by an embodiment of the present disclosure;

[0025] Figure 5Another circuit diagram of a gate driving circuit provided by an embodiment of the present disclosure is shown;

[0026] Figure 6 Another detailed structural diagram of the gate driving circuit provided by the embodiment of the present disclosure is shown;

[0027] Figure 7 Another circuit diagram of a gate driving circuit provided by an embodiment of the present disclosure is shown;

[0028] Figure 8 Another detailed structural diagram of the gate driving circuit provided by the embodiment of the present disclosure is shown;

[0029] Fig. 9 Another detailed structural diagram of the gate driving circuit provided by the embodiment of the present disclosure is shown;

[0030] Fig.10 The figure shows a driving timing diagram of a single gate drive provided by an embodiment of the present disclosure;

[0031] Fig.11 Shown is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0033] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0034] Figure 1 FIG. 1 is a schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure. Please refer to FIG. Figure 1 The embodiment of the present disclosure provides a gate driving circuit 100, which includes an input unit 10, a first output unit 21, a second output unit 22 and an output control unit 30; wherein,

[0035] The control end of the first output unit 21 is connected to the first node N1, and the first output unit 21 is configured to transmit the signal of the first level end VGL to the output end OUT of the gate driving circuit 100 according to the effective level signal of the first node N1;

[0036] The control end of the second output unit 22 is connected to the second node N2, and the second output unit 22 is configured to transmit the signal of the second level end VGH to the output end OUT of the gate driving circuit 100 according to the effective level signal of the second node N2;

[0037] The input unit 10 is connected to the input terminal IN, and is configured to control the potential of the first node N1 according to the input signal of the input terminal IN and the control signal of the clock signal terminal CK. The output control unit 30 is configured to control the potential of the second node N2 at least according to the output signal of the input unit 10.

[0038] In order to realize the screen display of the display product, a pixel driving circuit 01 is usually introduced into the display product to drive the pixel. The pixel driving circuit 01 generates a signal for driving the pixel to emit light under the cooperation of gate control signals, data signals, power signals and other signals. Figure 2 FIG. 1 is a schematic diagram showing a gate driving circuit 100 in an embodiment of the present disclosure when applied to a display panel. Figure 2 When the gate drive circuit 100 provided by the present disclosure is applied to a display product, the gate drive circuit 100 is used to provide a gate drive signal to the pixel drive circuit 01 in the display product, such as providing a scan signal to the pixel drive circuit through a scan line, providing a light-emitting control signal to the pixel drive circuit through a light-emitting control line, etc. The aforementioned scan signal may be, for example, a signal for controlling the pixel drive circuit to enter a reset phase, or a signal for controlling the pixel drive circuit to enter a data writing phase. In the reset phase, the gate of the driving transistor in the pixel drive circuit may be reset, or the anode of the light-emitting element may be reset. The aforementioned light-emitting control signal may be, for example, a signal for controlling the pixel drive circuit to enter a light-emitting phase. In the light-emitting phase, the pixel connected to the pixel drive circuit emits light. It should be noted that Figure 2 Only one form of the gate driving circuit 100 in the display panel is illustrated, and the number and specific connection of the gate driving circuits 100 in the display panel are not limited. The gate driving circuits in the display panel are cascaded.

[0039] In the gate drive circuit provided by the present disclosure, one of the first output unit 21 and the second output unit 22 is turned on. When the first output unit 21 is turned on in response to the effective level signal of the first node N1, the signal of the first level end VGL is transmitted to the output end OUT of the gate drive circuit; when the second output unit 22 is turned on in response to the effective level signal of the second node N2, the signal of the second level end VGH is transmitted to the output end OUT of the gate drive circuit. The signal of the first level end VGL and the second level end VGH, one is a low level, and the other is a high level. The gate drive circuit of the present disclosure introduces an input unit 10, and the potential of the first node N1 can be controlled by the input signal of the input end IN and the clock signal of the clock signal end CK, and introduces an output control unit 30, which controls the potential of the second node N2 at least according to the output signal of the input unit 10. Therefore, by the cooperation of the input signal of the input end IN, the input unit 10, the output control unit 30 and the clock signal of the clock signal end IN, the first output unit 21 and the second output unit 22 can be controlled to be turned on in time division and output a high level signal or a low level signal, which is conducive to simplifying the structure of the gate drive circuit. When the gate drive circuit is applied to a display product, it is helpful to reduce the space occupied by the gate drive circuit in the display panel, which is helpful to improve the space utilization rate of the display product. When the gate drive circuit is located in the border area of ​​the display panel, it is helpful to reduce the border width of the display product, realize a narrow border or an extremely narrow border design, and improve the screen-to-body ratio.

[0040] Figure 3 FIG. 1 is another circuit diagram of the gate driving circuit provided by the embodiment of the present disclosure. Please refer to FIG. Figure 3 In an optional embodiment of the present disclosure, the output control unit 30 includes a first control unit 31 and a second control unit 32, the control end of the first control unit 31 is connected to the first node N1, the first electrode and the second electrode of the first control unit 31 are connected between the first level end VGL and the second node N2; the control end of the second control unit 32 is connected to the third node N3, the first electrode and the second electrode of the second control unit 32 are connected between the second level end VGH and the second node N2; wherein the third node N3 is connected to the output end of the input unit 10. Optionally, the third node N3 is coupled to the first node N1, that is, the two can be directly connected, or they can be connected through other components such as switches.

[0041] In this embodiment, the output control unit 30 in the gate driving circuit is further refined, and includes a first control unit 31 connected to the first level terminal VGL and a second control unit 32 connected to the second level terminal VGH. Optionally, the signal of the first level terminal VGL is a low level signal, and the signal of the second level terminal VGH is a high level signal. When the first control unit 31 is turned on under the control of the first node N1, the signal of the first level terminal VGL can be transmitted to the second node N2. When the second control unit 32 is turned on under the control of the third node N3, the signal of the second level terminal VGH can be transmitted to the second node N2. Considering that one of the signals of the first level terminal VGL and the second level terminal VGH is a low level and the other is a high level, the second node N2 can be controlled to be in a low level or high level state by the first control unit 31 and the second control unit 32, respectively, so as to control whether the second output unit 22 is turned on. This design method simplifies the control of the second node N2, which is conducive to simplifying the overall control of the gate driving circuit.

[0042] Figure 4 FIG. 1 is a detailed structural diagram of the gate drive circuit provided in the embodiment of the present disclosure, please refer to FIG. Figure 4 In an optional embodiment of the present disclosure, the first control unit 31 includes a first transistor M1, and the gate, the first pole and the second pole of the first transistor M1 correspond to the control end, the first pole and the second pole of the first control unit 31 respectively; the second control unit 32 includes a second transistor M2, and the gate, the first pole and the second pole of the second transistor M2 correspond to the control end, the first pole and the second pole of the second control unit 32 respectively.

[0043] Please refer to Figure 4, this embodiment is described by taking the first control unit 31 and the second control unit 32 each including a transistor as an example, the gate of the first transistor M1 in the first control unit 31 is connected to the first node N1, the first electrode and the second electrode are respectively connected to the first level end VGL and the second node N2; the gate of the second transistor M2 in the second control unit 32 is connected to the third node N3, the first node N1 and the second electrode are respectively connected to the second level end VGH and the second node N2. Among them, the first transistor M1 and the second transistor M2 are transistors with opposite polarities. At the same time, only one of the first transistor M1 and the second transistor M2 is turned on. When the first transistor M1 is turned on, the low level signal of the first level end VGL will be transmitted to the second node N2; when the second transistor M2 is turned on, the high level signal of the second level end VGH will be transmitted to the second node N2. In this way, the potential of the second node N2 is controlled, and then the control of whether the second output unit 22 is turned on or not is realized. In the present embodiment, only one transistor needs to be introduced into the first control unit 31 and the second control unit 32 respectively to realize the control of the potential of the second node N2, thereby avoiding the introduction of complex circuit structures into the first control unit 31 and the second control unit 32 respectively. Therefore, it is beneficial to simplify the overall structure of the gate drive circuit and reduce the space occupied by the gate drive circuit as a whole in the display panel, thereby helping to improve the screen-to-body ratio of the display product.

[0044] Please continue to refer to Figure 4 In an optional embodiment of the present disclosure, the first transistor M1 is an N-type transistor, and the second transistor M2 is a P-type transistor; the control end of the N-type transistor is turned on in response to a high-level signal, and the control end of the P-type transistor is turned on in response to a low-level signal. In this embodiment, the first transistor M1 is set as an N-type transistor, and the second transistor M2 is set as a P-type transistor. In this way, at the same time, only one of the first transistor M1 and the second transistor M2 is turned on, thereby realizing the control of the potential of the second node N2.

[0045] Of course, in some other embodiments of the present disclosure, the types of the first transistor M1 and the second transistor M2 may be replaced. For example, the first transistor M1 may be set to a P-type transistor, and the second transistor M2 may be set to an N-type transistor. In this case, the control end of the first transistor M1 is turned on under the control of a low-level signal, and the control end of the second transistor M2 is turned on under the control of a high-level signal. It is also possible to achieve that only one of the first transistor M1 and the second transistor M2 is turned on at the same time to achieve control of the potential of the second node N2.

[0046] Please refer to Figure 4, Optionally, the gate drive circuit includes a first capacitor C1, and the two plates of the first capacitor C1 are respectively connected to the output terminal OUT of the gate drive circuit and the first node N1, and optionally, the first output unit 21 includes a P-type transistor. When the output terminal OUT of the gate drive circuit outputs a high level, under the coupling effect of the first capacitor C1, the potential of the first node N1 will be raised, and the high level of the first node N1 will control the first output unit 21 to remain turned off, ensuring that the output terminal OUT outputs a high level. When the output terminal OUT of the gate drive circuit outputs a low level, under the coupling effect of the first capacitor C1, the potential of the first node N1 will be coupled to reduce, and the low level of the first node N1 will maintain the first output unit 21 turned on, ensuring that the output terminal OUT outputs a low level. Therefore, the introduction of the first capacitor C1 is conducive to improving the stability of the output signal of the output terminal OUT of the gate drive circuit.

[0047] Figure 5 FIG. 1 is another circuit diagram of the gate driving circuit provided by the embodiment of the present disclosure. Please refer to FIG. Figure 5 In an optional embodiment of the present disclosure, the gate driving circuit further includes an isolation unit 40, which is connected in series between the third node N3 and the first node N1, and is configured to allow the signal to be transmitted from the third node N3 to the first node N1, and inhibit the signal from being transmitted from the first node N1 to the third node N3. Figure 4 Due to the coupling effect of the first capacitor C1, when the output terminal OUT of the gate driving circuit outputs a high-level signal, the potential of the first node N1 will be coupled to become higher. If the isolation unit 40 is not provided between the first node N1 and the third node N3, the high-level signal of the first node N1 will be transmitted to the third node N3, resulting in unnecessary biasing of the second transistor M2 in the second control unit 32 and the transistors in the input unit 10 connected to the third node N3, which will affect the performance of these transistors in the long term. Therefore, in this embodiment, an isolation unit 40 is introduced between the first node N1 and the third node N3. The isolation unit 40 can inhibit the transmission of the signal from the first node N1 to the third node N3, thereby facilitating the avoidance of the influence of the potential of the first node N1 on the transistors in the second control unit 32 and the input unit 10, thereby facilitating the improvement of the stability of the performance of these transistors.

[0048] Figure 6 FIG. 1 is another detailed structural diagram of the gate drive circuit provided in the embodiment of the present disclosure, please refer to FIG. Figure 6 In an optional embodiment of the present disclosure, the isolation unit 40 includes a third transistor M3, a first electrode of the third transistor M3 is connected to the third node N3, a second electrode is connected to the first node N1, and a gate of the third transistor M3 is connected to the first control signal terminal. This embodiment is described by taking the first control signal terminal multiplexing the first level terminal VGL as an example.

[0049] Please refer to Figure 6 The isolation unit 40 in the present disclosure may be embodied as a third transistor M3. This embodiment is described by taking the third transistor M3 as a P-type transistor as an example. The gate of the P-type transistor is connected to the first control signal terminal, such as a low-level signal terminal, so that the third transistor M3 is in an on state. Due to the characteristics of the transistor itself, the signal of the third node N3 can be transmitted to the first node N1 through the third transistor M3, while the signal of the first node N1 cannot be transmitted to the third node N3. In this way, the isolation function of the isolation unit 40 can be realized by introducing a transistor, which is conducive to simplifying the overall design structure of the gate drive circuit and reducing the space occupied by the gate drive circuit in the display product.

[0050] Of course, in some other embodiments of the present disclosure, the third transistor M3 can also be set as an N-type transistor, and its gate is connected to a high-level signal to keep the third transistor M3 in an on state, which can also play a role in suppressing the signal of the first node N1 from being transmitted to the third node N3. The present disclosure does not make specific limitations on this.

[0051] Figure 7 FIG. 1 is another circuit diagram of the gate driving circuit provided by the embodiment of the present disclosure. Please refer to FIG. Figure 7 In an optional embodiment of the present disclosure, the gate driving circuit 100 further includes a voltage stabilizing unit 50, the control end of the voltage stabilizing unit 50 is connected to the second node N2, the first electrode and the second electrode of the voltage stabilizing unit 50 are connected between the first level end VGL and the output end OUT of the gate driving circuit, and the voltage stabilizing unit 50 is configured to be turned on according to the invalid level signal outputted from the second node N2 to the second output unit 22. When the second node N2 outputs the invalid level signal to the second output unit 22, the second output unit 22 is turned off and the first output unit 21 is turned on. At this time, the signal of the first level end VGL is transmitted to the output end OUT of the gate driving circuit. Figure 7 For example, the signal at the first level end VGL is a low level signal, and the gate drive circuit outputs a low level signal. When the second output unit 22 is turned off, the voltage stabilizing unit 50 is turned on. At this time, the signal at the first level end VGL connected to the voltage stabilizing unit 50 is transmitted to the output end OUT of the gate drive circuit, which is conducive to ensuring the stability of the gate drive circuit when outputting the signal at the first level end VGL. When the signal at the second node N2 turns on the second output unit 22, the voltage stabilizing unit 50 is turned off, so as to avoid the voltage stabilizing unit 50 affecting the signal when the output end OUT of the gate drive circuit outputs the signal at the second level end VGH.

[0052] Figure 8 FIG. 1 is another detailed structural diagram of the gate drive circuit provided in the embodiment of the present disclosure, please refer to FIG. Figure 8 In an optional embodiment of the present disclosure, the voltage stabilizing unit 50 includes a fourth transistor M4, and the gate, the first electrode and the second electrode of the fourth transistor M4 correspond to the control terminal, the first electrode and the second electrode of the voltage stabilizing unit 50, respectively. This embodiment shows a solution in which the voltage stabilizing unit 50 adopts one transistor, which is conducive to simplifying the overall structure of the gate drive circuit and reducing the space occupied by the gate drive unit in the display product, thereby facilitating the improvement of the screen-to-body ratio of the display product. It should be noted that the fourth transistor M4 in the voltage stabilizing unit 50 and the transistor in the second output unit 22 have opposite polarities. This embodiment is described by taking the fourth transistor M4 as an N-type transistor and the sixth transistor M6 in the second output unit 22 as a P-type transistor as an example. At this time, the signal of the first level end VGL is a low-level signal, and the signal of the second level end VGH is a high-level signal, but the present disclosure does not specifically limit this. In some other embodiments of the present disclosure, the fourth transistor M4 can also be embodied as a P-type transistor and the sixth transistor M6 can be embodied as an N-type transistor.

[0053] Fig. 9 FIG. 1 is another detailed structural diagram of the gate drive circuit provided in the embodiment of the present disclosure, please refer to FIG. Fig. 9 In an optional embodiment of the present disclosure, the gate driving circuit further includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is connected between the first node N1 and the output terminal OUT of the gate driving circuit, and the second capacitor C2 is connected between the second node N2 and the second level terminal VGH.

[0054] The present disclosure introduces a first capacitor C1 in the gate drive circuit, and the two plates of the first capacitor C1 are respectively connected to the output terminal OUT of the gate drive circuit and the first node N1. Optionally, the first output unit 21 includes a P-type transistor. When the output terminal OUT of the gate drive circuit outputs a high level, under the coupling effect of the first capacitor C1, the potential of the first node N1 will be raised, and the high level of the first node N1 will control the first output unit 21 to be turned off, ensuring that the output terminal OUT outputs a high level. When the output terminal OUT of the gate drive circuit outputs a low level, under the coupling effect of the first capacitor C1, the potential of the first node N1 will be coupled to be reduced, and the low level of the first node N1 will maintain the first output unit 21 turned on, ensuring that the output terminal OUT outputs a low level. Therefore, the introduction of the first capacitor C1 is conducive to improving the stability of the output signal of the output terminal OUT of the gate drive circuit.

[0055] Since the signal of the second level terminal VGH is a constant level signal, when the second capacitor C2 is introduced between the second level terminal VGH and the second node N2, the second capacitor C2 can be used to stabilize the potential of the second node N2, which is beneficial to ensure the on-state of the second output unit 22 when the second output unit 22 is turned on, and is beneficial to ensure the off-state of the second output unit 22 when the second output unit 22 is turned off, thereby helping to improve the stability of the gate drive circuit.

[0056] Please continue to refer to Fig. 9 In an optional embodiment of the present disclosure, the first output unit 21 includes a fifth transistor M5, and the second output unit 22 includes a sixth transistor M6. The fifth transistor M5 and the sixth transistor M6 are both P-type transistors, or the fifth transistor M5 and the sixth transistor M6 are both N-type transistors. The present disclosure embodiment is described by taking the fifth transistor M5 and the sixth transistor M6 as P-type transistors as an example. The gate of the P-type transistor is turned on under the control of a low-level signal and turned off under the control of a high-level signal. In the gate drive circuit mentioned in the present disclosure, the fifth transistor M5 and the sixth transistor M6 are turned on in time-sharing mode, so that the gate drive circuit outputs a high-low level alternating signal. In some other embodiments of the present disclosure, the fifth transistor M5 in the first output unit 21 and the sixth transistor M6 in the second output unit 22 can also be N-type transistors. The gate of the N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal. The fifth transistor M5 and the sixth transistor M6 are turned on in time-sharing mode, which can also meet the output requirements of the gate drive circuit.

[0057] Optionally, the input unit 10 in the gate driving circuit provided by the present disclosure includes a seventh transistor M7, Fig. 9 The embodiment is described by taking the seventh transistor M7 as a P-type transistor as an example, but the present invention is not limited thereto. In some other embodiments of the present disclosure, the input unit 10 may also be an N-type transistor.

[0058] In the embodiment of the present disclosure, the function of the gate driving circuit can be realized by utilizing the structure of 7 transistors and two capacitors that cooperate with each other. Compared with the scheme in which the gate driving circuit in the related art includes 9 or more transistors, the structure of the gate driving circuit is greatly simplified, and the space occupied by the gate driving circuit in the display product is effectively reduced. When the gate driving circuit provided by the embodiment of the present disclosure is applied to the display product, it is beneficial to reduce the space occupied by the gate driving circuit in the border area of ​​the display panel, thereby facilitating the realization of a narrow border design of the display product and improving the screen-to-body ratio of the display product.

[0059] Based on the same inventive concept, the present disclosure further provides a driving method of a gate driving circuit, which is applied to the gate driving circuit in the aforementioned embodiment. Fig.10The following is a driving timing diagram of a single gate drive provided by the embodiment of the present disclosure. Figure 1 , Fig. 9 and Fig.10 , the driving method of the gate driving circuit provided in the embodiment of the present disclosure includes:

[0060] In the first stage t1, under the control of the clock signal, the input unit 10 is turned on, the signal of the input terminal IN is transmitted to the first node N1, the first output unit 21 is controlled to be turned on, the second output unit 22 is turned off, and the signal of the first level terminal VGL is transmitted to the output terminal OUT of the gate driving circuit;

[0061] In the second stage t2, under the control of the clock signal, the input unit 10 is turned off, the first node N1 maintains the level signal of the first stage, the first output unit 21 remains turned on, the second output unit 22 remains turned off, and the output terminal OUT of the gate driving circuit keeps outputting the signal of the first level terminal VGL;

[0062] In the third stage t3, under the control of the clock signal, the input unit 10 is turned on, the second level signal of the input terminal IN is transmitted to the first node N1, the first output unit 21 is controlled to be turned off, and the output control unit 30 is controlled to output a valid level signal to the second node N2, so that the second output unit 22 is turned on, and the signal of the second level terminal VGH is transmitted to the output terminal OUT of the gate driving circuit;

[0063] In the fourth stage t4, the signal at the input terminal IN becomes the first level signal, under the control of the clock signal, the input unit 10 is turned off, the first node N1 maintains the second level signal of the third stage, and the output terminal OUT of the gate driving circuit maintains the signal of the second level terminal VGH;

[0064] In the fifth stage t5, under the control of the clock signal, the input unit 10 is turned on, the first level signal of the input terminal IN is transmitted to the first node N1, the first output unit 21 is controlled to be turned on and the second output unit 22 is turned off, and the signal of the first level terminal VGL is transmitted to the output terminal OUT of the gate driving circuit.

[0065] The driving method mentioned in the embodiment of the present disclosure is applied to Fig. 9 In the embodiment shown, the specific driving process is:

[0066] In the first stage t1, the clock signal is a low-level signal, which controls the seventh transistor M7 to be turned on, and the third transistor M3 remains in the on state. The low-level signal of the input terminal IN is transmitted to the first node N1 through the seventh transistor M7 and the third transistor M3, so that the fifth transistor M5 is turned on. The low-level signal of the first level terminal VGL is transmitted to the output terminal OUT of the gate driving circuit, and the low-level signal of the third node N3 controls the second transistor M2 to be turned on. The high-level signal of the second level terminal VGH is transmitted to the sixth transistor M6, which controls the sixth transistor M6 to be turned off.

[0067] In the second stage t2, the clock signal jumps to a high level signal, controlling the seventh transistor M7 to turn off, the first node N1 maintains the low level signal of the first stage, the fifth transistor M5 remains turned on, the output terminal OUT of the gate drive circuit still outputs a low level signal, and the sixth transistor M6 remains turned off.

[0068] In the third stage t3, the clock signal jumps to a low level signal, controlling the seventh transistor M7 to turn on, and the high level signal of the input terminal IN is transmitted to the third node N3 and the first node N1, so that the fifth transistor M5 is turned off, and the first transistor M1 is turned on, and the low level signal of the first level terminal VGL is transmitted to the sixth transistor M6 through the first transistor M1, so that the sixth transistor M6 is turned on, and the high level signal of the second level terminal VGH is output to the output terminal OUT of the gate drive circuit.

[0069] In the fourth stage t4, the clock signal jumps to a high level signal, the seventh transistor M7 is turned off, the third node N3 and the first node N1 maintain the high level signal of the third stage, the fifth transistor M5 remains turned off, the sixth transistor M6 remains turned on, and the gate drive circuit output terminal OUT can still output a high level signal.

[0070] In the fifth stage t5, the clock signal jumps to a low level signal, the seventh transistor M7 is turned on, the low level signal of the input terminal IN is transmitted to the third node N3 and the first node N1, the fifth transistor M5 is turned on, the low level signal of the first level terminal VGL is transmitted to the output terminal OUT of the gate drive circuit, the second transistor M2 is turned on, and the high level signal of the second level terminal VGH is transmitted to the gate of the sixth transistor M6, controlling the sixth transistor M6 to turn off.

[0071] In this way, the output of the signal of the gate driving circuit is achieved.

[0072] Based on the same inventive concept, the present disclosure also provides a display panel 200, please refer to Figure 2, the display panel includes a pixel driving circuit and a gate driving circuit 100 provided in the above embodiment, the gate driving circuit 100 is configured to provide a control signal to the pixel driving circuit; the display panel 200 includes a display area AA and a non-display area NA, and the gate driving circuit 100 is located in the non-display area NA of the display panel. Since the number of transistors in the gate driving circuit provided in the embodiment of the present disclosure is relatively small, the number of transistors in the gate driving circuit is greatly reduced compared to the gate driving circuit in the related art, which is beneficial to reduce the space occupied by the gate driving circuit in the non-display area of ​​the display panel, thereby helping to reduce the border width of the display panel, and is beneficial to realize the narrow border design of the display panel and improve the screen-to-body ratio of the display panel. It should be noted that Figure 2 Only the scheme of setting the gate driving circuit 100 in the non-display area NA on one side of the display panel is shown. In some other embodiments of the present disclosure, the gate driving circuit 100 may also be set in the non-display area NA on both sides of the display panel, and the present disclosure does not specifically limit this. When the gate driving circuit 100 is introduced into the display panel, one scan line can be electrically connected to one gate driving circuit 100, or it can be electrically connected to two gate driving circuits 100 to realize bilateral driving, and the present disclosure does not specifically limit this.

[0073] It should be noted that Figure 2 The display panel 200 with a rectangular structure is only taken as an example for description, and the actual shape of the display panel is not limited. In some other embodiments of the present disclosure, the display panel may also be embodied in any other feasible shape such as a circle, a rounded rectangle, etc.

[0074] Optionally, the display panel provided in this embodiment may be a display panel using organic light-emitting diode display technology, i.e., an OLED (Organic Light-Emitting Diode) display panel. Of course, in some other embodiments of the present invention, the display panel may also be a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a Mini LED display panel, etc. The present disclosure is not limited to this.

[0075] Based on the same inventive concept, the present disclosure provides a display device, Fig.11The figure shows a schematic diagram of the structure of the display device provided in the embodiment of the present disclosure, and the display device 300 includes the display panel 200 provided in the above embodiment of the present disclosure. The display device 300 provided in the embodiment of the present disclosure can be any electronic device with display function, such as a tablet computer with touch and display functions, a display product in a display cabinet, a television or a car display device, and is particularly suitable for a display device with an extremely narrow frame. The display device 300 provided in the embodiment of the present disclosure has the beneficial effects of the display panel 200 provided in the embodiment of the present disclosure. For details, please refer to the specific description of the display panel 200 in the above embodiments, and this embodiment will not be repeated here.

[0076] Understandably, Fig.11 The display device is only illustrated in a rectangular structure. In some other embodiments of the present disclosure, the display device 300 may also be embodied as a rounded rectangle, a circle, an ellipse or any other feasible shape, and the present disclosure does not specifically limit this.

[0077] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0078] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A gate drive circuit, characterized in that: It includes an input unit, a first output unit, a second output unit and an output control unit; wherein, The control end of the first output unit is connected to the first node, and the first output unit is configured to transmit the signal of the first level end to the output end of the gate driving circuit according to the effective level signal of the first node; The control end of the second output unit is connected to the second node, and the second output unit is configured to transmit the signal of the second level end to the output end of the gate driving circuit according to the effective level signal of the second node; The input unit is connected to the input end, and is configured to control the potential of the first node according to the input signal of the input end and the control signal of the clock signal end, and the output control unit is configured to control the potential of the second node according to the output signal of the input unit.

2. The gate driving circuit according to claim 1, characterized in that: The output control unit comprises a first control unit and a second control unit, the control end of the first control unit is connected to the first node, and the first pole and the second pole of the first control unit are connected between the first level end and the second node; The control end of the second control unit is connected to a third node, and the first pole and the second pole of the second control unit are connected between the second level end and the second node; wherein the third node is connected to the output end of the input unit.

3. The gate driving circuit according to claim 2, characterized in that: The first control unit includes a first transistor, the gate, the first pole and the second pole of the first transistor correspond to the control end, the first pole and the second pole of the first control unit respectively; the second control unit includes a second transistor, the gate, the first pole and the second pole of the second transistor correspond to the control end, the first pole and the second pole of the second control unit respectively.

4. The gate driving circuit according to claim 3, characterized in that: The first transistor is an N-type transistor, and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

5. The gate driving circuit according to claim 2, characterized in that: The method further includes an isolation unit, which is connected in series between the third node and the first node, and is configured to allow a signal to be transmitted from the third node to the first node, and to inhibit a signal from being transmitted from the first node to the third node.

6. The gate driving circuit according to claim 5, characterized in that: The isolation unit includes a third transistor, a first electrode of the third transistor is connected to the third node, a second electrode of the third transistor is connected to the first node, and a gate of the third transistor is connected to the first control signal terminal.

7. The gate driving circuit according to claim 1, characterized in that: It also includes a voltage stabilizing unit, the control end of the voltage stabilizing unit is connected to the second node, the first pole and the second pole of the voltage stabilizing unit are connected between the first level end and the output end of the gate drive circuit, and the voltage stabilizing unit is configured to be turned on according to the invalid level signal output by the second node to the second output unit.

8. The gate driving circuit according to claim 7, characterized in that: The voltage stabilizing unit comprises a fourth transistor, and a gate, a first electrode and a second electrode of the fourth transistor correspond to the control terminal, the first electrode and the second electrode of the voltage stabilizing unit respectively.

9. The gate driving circuit according to claim 1, characterized in that: It also includes a first capacitor and a second capacitor, wherein the first capacitor is connected between the first node and the output end of the gate driving circuit, and the second capacitor is connected between the second node and the second level end.

10. The gate driving circuit according to claim 1, characterized in that: The first output unit includes a fifth transistor, the second output unit includes a sixth transistor, the fifth transistor and the sixth transistor are both P-type transistors, or the fifth transistor and the sixth transistor are both N-type transistors.

11. A driving method for a gate driving circuit, characterized in that: Applicable to the gate drive circuit according to any one of claims 1 to 10, the driving method comprising: In the first stage, under the control of the clock signal, the input unit is turned on, the first level signal at the input end is transmitted to the first node, the first output unit is controlled to be turned on and the second output unit is turned off, and the signal at the first level end is transmitted to the output end of the gate driving circuit; In the second stage, under the control of the clock signal, the input unit is turned off, the first node maintains the level signal of the first stage, the first output unit remains turned on, the second output unit remains turned off, and the output end of the gate driving circuit keeps outputting the signal of the first level end; In the third stage, under the control of the clock signal, the input unit is turned on, the second level signal at the input end is transmitted to the first node, the first output unit is controlled to be turned off, and the output control unit is controlled to output a valid level signal to the second node, so that the second output unit is turned on, and the signal at the second level end is transmitted to the output end of the gate driving circuit; In the fourth stage, the signal at the input end becomes a first level signal, under the control of the clock signal, the input unit is turned off, the first node maintains the second level signal of the third stage, and the output end of the gate driving circuit maintains outputting the signal at the second level end; In the fifth stage, under the control of the clock signal, the input unit is turned on, the first level signal at the input end is transmitted to the first node, the first output unit is controlled to be turned on and the second output unit is turned off, and the signal at the first level end is transmitted to the output end of the gate drive circuit.

12. A display panel, characterized in that: It comprises a pixel driving circuit and the gate driving circuit as claimed in any one of claims 1 to 10, wherein the gate driving circuit is configured to provide a control signal to the pixel driving circuit; and the gate driving circuit is located in a non-display area of ​​the display panel.

13. A display device, characterized in that: Includes the display panel as claimed in claim 12.

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