Liquid crystal panel time sequence driving circuit and display device

Abstract

The embodiment of the invention relates to a liquid crystal panel time sequence driving circuit and a display device. The circuit comprises a main control module, a power management module, a first level conversion module and a second level conversion module, the first level conversion module is used for receiving a first group of input clock control signals and a first initial scanning control signal from the main control module and outputting the first group of clock control signals and the first initial scanning control signal to the liquid crystal panel; the second level conversion module is used for receiving a second group of input clock control signals and a second initial scanning control signal from the main control module and outputting the second group of input clock control signals and the second initial scanning control signal to the liquid crystal panel; the power management module is used for outputting clock levels to the first level conversion module and the second level conversion module. According to the embodiment of the invention, the combined application of the first level conversion module and the second level conversion module is realized, and more clock signals and initial scanning signals are provided, so that the application scene of the panel driving circuit is expanded.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a liquid crystal panel timing drive circuit and a display device. Background Art

[0002] With the development of display panel technology, the timing of the row driver module (GOA, Gate on Array) of the panel changes greatly, which puts higher requirements on the level shifter IC (LSIC, Level shifter IC). For example, in order to display the H1 Line picture in the HSR mode, when the odd frame (or even frame) is required, all odd rows (or even rows) are turned on and charged with L0 grayscale (or L255 grayscale), when the even frame (or odd frame) is required, all even rows (or odd rows) are turned on and charged with L255 grayscale (or L0 grayscale). In this way, the H1 Line picture in the HSR mode can be turned on in a special driving method.

[0003] In order to adapt to the diverse scanning driving methods, it is not enough to have only one frame start scanning signal STV, but at least two STVs are required. For example, STV1A and STV1B are used to control the start scanning of odd frames and even frames respectively. Moreover, in order to improve the charging time, these panels often add GOA units, and the corresponding number of clocks is also large, for example, generally 12 CK (clocks) or more.

[0004] In short, in order to drive various special panels, LSIC (connected to the panel, providing the signals and timing required for the panel GOA unit scanning) is required to provide multiple STV channels and multiple CK channels, as well as LC, VSS, etc. The current single LSIC cannot provide more STV channels and CK channels, resulting in limited application scenarios of panel driving circuits. Summary of the invention

[0005] In view of this, in order to solve some or all of the above-mentioned technical problems, an embodiment of the present application provides a liquid crystal panel timing drive circuit and a display device.

[0006] In a first aspect, an embodiment of the present application provides a liquid crystal panel timing drive circuit, which includes: a main control module, a power management module, a first level conversion module, and a second level conversion module; the first level conversion module is connected to the main control module and the liquid crystal panel, and is used to receive a first group of clock control signals and a first start scan control signal input from the main control module, and output the first group of clock signals and the first start scan signal to the liquid crystal panel; the second level conversion module is connected to the main control module and the liquid crystal panel, and is used to receive a second group of clock control signals and a second start scan control signal input from the main control module, and output the second group of clock signals and the second start scan signal to the liquid crystal panel; the power management module is connected to the level conversion module, and is used to output clock levels to the first level conversion module and the second level conversion module.

[0007] In a possible implementation manner, the output end of the first group of clock signals and the output end of the second group of clock signals are sequentially and alternately connected to the clock input end of the liquid crystal panel.

[0008] In one possible embodiment, the first level conversion module is used to: at a first starting moment of the first group of clock control signals, sequentially output each clock signal in the first group of clock signals according to a preset clock output interval time; the second level conversion module is used to: at a second starting moment of the second group of clock control signals, sequentially output each clock signal in the second group of clock signals according to the clock output interval time, wherein the first starting moment is earlier than the second starting moment, and the interval time between the first starting moment and the second starting moment is half of the clock output interval time.

[0009] In a possible implementation manner, the clock output interval is one cycle of the first group of clock control signals and the second group of clock control signals.

[0010] In one possible embodiment, the first group of clock control signals includes a first clock control signal and a second clock control signal, and the second group of clock control signals includes a third clock control signal and a fourth clock control signal; the first level conversion module is used to: when the level of the first clock control signal reaches a first preset state, sequentially output the first level of each clock signal in the first group of clock signals; when the level of the second clock control signal reaches a second preset state, sequentially output the second level of each clock signal in the first group of clock signals; the second level conversion module is used to: when the level of the third clock control signal reaches the first preset state, sequentially output the first level of each clock signal in the second group of clock signals; when the level of the fourth clock control signal reaches the second preset state, sequentially output the second level of each clock signal in the second group of clock signals.

[0011] In a possible implementation manner, the first level conversion module or the second level conversion module is further configured to receive a reset control signal input from the main control module and output a reset signal to the liquid crystal panel.

[0012] In one possible implementation, the first level conversion module and the second level conversion module both include a row drive enable signal output terminal and a low potential voltage output terminal; any row drive enable signal output terminal and any low potential voltage output terminal included in the first level conversion module and the second level conversion module are connected to the liquid crystal panel to output the row drive enable signal and the low potential voltage to the liquid crystal panel.

[0013] In a possible implementation manner, the first level conversion module and the second level conversion module are integrated in the same level conversion chip; the level conversion chip is connected to the main control module and the power management module.

[0014] In a possible implementation manner, the first level conversion module, the second level conversion module and the power management module are integrated in the same power management chip, and the power management chip is connected to the main control module.

[0015] In the second aspect, an embodiment of the present application provides a display device, including: a main board, a control board and a liquid crystal panel, the main board is connected to the control board, and the control board is connected to the liquid crystal panel; the main board is provided with a main control module included in the liquid crystal panel timing drive circuit described in the first aspect above, and the control board is provided with a power management module, a first level conversion module, and a second level conversion module included in the liquid crystal panel timing drive circuit.

[0016] The liquid crystal panel timing drive circuit and display device provided in the embodiments of the present application are configured with a main control module, a power management module, a level conversion module, a first level conversion module, and a second level conversion module. The main control module controls the timing of the first level conversion module and the second level conversion module, and the power management module provides the power required by the first level conversion module and the second level conversion module. The first level conversion module and the second level conversion module are applied in combination, and more clock signals and start scanning signals are provided, thereby expanding the application scenarios of the panel drive circuit and improving the flexibility of providing timing signals to the panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0020] Figure 1 A schematic diagram of the structure of a liquid crystal panel timing drive circuit provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of signal flow of two level conversion modules provided in an embodiment of the present application;

[0022] Figure 3 A timing diagram of clock signals output by two level conversion modules provided in an embodiment of the present application;

[0023] Figure 4 A signal flow diagram of integrating two level conversion modules into a level conversion chip provided in an embodiment of the present application;

[0024] Figure 5A A schematic diagram of the delay of the start scanning signal when two level conversion modules provided in an embodiment of the present application are separated;

[0025] Figure 5B A schematic diagram of the delay of the start scanning signal when two level conversion modules provided in an embodiment of the present application are integrated into the same chip;

[0026] Figure 6 A signal flow diagram of integrating two level conversion modules and a power management module into a power management chip provided in an embodiment of the present application;

[0027] Figure 7 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0028] Reference numerals:

[0029] 100-LCD panel timing drive circuit; 101-main control module; 102-power management module; 103-first level conversion module; 104-second level conversion module; 105-level conversion chip; 106-power management chip; 700-display device; 701-mainboard; 702-control board; 703-LCD panel. DETAILED DESCRIPTION

[0030] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the numerical expressions and the numerical values ​​described in these embodiments do not limit the scope of the present application.

[0031] Those skilled in the art will understand that the terms "first" and "second" in the embodiments of the present application are only used to distinguish between different steps, devices, modules and other objects, and do not represent any specific technical meanings, nor do they indicate the logical order between them.

[0032] It should also be understood that in this embodiment, “plurality” may refer to two or more than two, and “at least one” may refer to one, two or more than two.

[0033] It should also be understood that any component, data or structure mentioned in the embodiments of the present application can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0034] In addition, the term "and / or" in this application is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0035] It should also be understood that the description of the various embodiments in this application focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0036] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present application, its application, or uses.

[0037] Technologies, circuits, and devices known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the above-mentioned technologies, circuits, and devices should be considered as part of the specification.

[0038] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0039] It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. To facilitate the understanding of the embodiments of the present application, the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0040] In order to meet the driving requirements of existing special panels such as HSR and solve the problem that the existing panel driving circuit lacks sufficient STV channels and CK channels, the embodiment of the present application provides a liquid crystal panel timing driving circuit, which can realize joint control of two level conversion modules and improve the scene adaptability of the driving circuit.

[0041] Figure 1 This is a structural schematic diagram of a liquid crystal panel timing drive circuit provided in an embodiment of the present application. The circuit specifically includes: a main control module 101, a power management module 102, a first level conversion module 103, and a second level conversion module 104.

[0042] The main control module 101 can be any type of electronic device with logic operation capability. For example, the main control module 101 can be a SOC chip, or a chip such as an MCU. Optionally, the main control module 101 can be integrated with a timing control function (TCON), that is, the circuit can be applied to a TCON-less architecture (i.e., a separate TCON IC is not used, and the function of the TCON IC is integrated into the SOC).

[0043] The power management module 102, the first level conversion module 103, and the second level conversion module 104 may be separate chips, or a circuit board composed of multiple discrete components. Any two or all of the three modules may also be integrated into the same chip.

[0044] In this embodiment, if Figure 1 As shown, the first level conversion module 103 is connected to the main control module 101 and the liquid crystal panel, and is used to receive the first group of clock control signals and the first start scanning control signal input from the main control module 101, and output the first group of clock signals and the first start scanning signal to the liquid crystal panel. The second level conversion module 104 is connected to the main control module 101 and the liquid crystal panel, and is used to receive the second group of clock control signals and the second start scanning control signal input from the main control module 101, and output the second group of clock signals and the second start scanning signal to the liquid crystal panel.

[0045] Among them, the main control module 101 can generate a clock control signal according to a certain logic, and output the clock control signal to the first level conversion module 103 and the second level conversion module 104. The signal input end of the first level conversion module 103 and the second level conversion module 104 receives the clock control signal and converts its level. For example, the high level DVDD3V3 is pulled up from 3.3V to VGH (different panel voltages are different, such as 36V, etc.), and the low level 0V input therein is reduced to VGL (different panel voltages are different, such as -10V, etc.). The main control module 101 usually inputs a square wave with a high level of 3.3V and a low level of 0V to the first level conversion module 103 and the second level conversion module 104, and is pulled up by the first level conversion module 103 and the second level conversion module 104 to a square wave with a high level of VGH and a low level of VGL.

[0046] The first group of clock control signals and the second group of clock control signals are output by the main control module 101 to the first level conversion module 103 and the second level conversion module 104. The two groups of signals are used to control the timing of the clock signals. For example, for a 2-input 6-output level conversion module, it can receive a group of clock control signals composed of input CPV1 and CPV2.

[0047] The first group of clock signals and the second group of clock signals are used to provide clocks to the row scanning driving module (such as GOA) on the liquid crystal panel, so that the liquid crystal panel can drive each row of pixels to display the corresponding color according to the clocks.

[0048] The first group of clock signals and the second group of clock signals can be respectively input into the row scanning driving module included in the liquid crystal panel according to the set order. For example, the first group of clock signals are output through the six ports CK1-CK6 included in the first level conversion module 103, and the second group of clock signals are output through the six ports CK1-CK6 included in the second level conversion module 104, and the two groups of ports can be respectively connected to the CLK1-CLK6 ports and CLK7-CLK12 ports on the liquid crystal panel.

[0049] The first start scanning control signal and the first start scanning signal, as well as the second start scanning control signal and the second start scanning signal, may be in a one-to-one relationship, such as Figure 2As shown, the main control module 101 inputs the first start scanning control signal STV1A_IN and the second start scanning control signal STV1B_IN to the first level conversion module 103 and the second level conversion module 104, respectively, and outputs the first start scanning signal STV1A and the second start scanning signal STV1B. The start scanning signal is used to control the start scanning moment of a frame of image. When odd frames and even frames need to be controlled separately, two start scanning signals STV1A and STV1B can be output.

[0050] In this embodiment, the power management module 102 is connected to the level conversion module, and is used to output clock levels to the first level conversion module 103 and the second level conversion module 104 .

[0051] The clock level is the size of the high and low levels of the clock signal output by the level conversion module, such as the above-mentioned VGH and VGL. The power management module 102 can work normally when the external power supply voltage is input and the necessary registers are written, and output various voltages for other modules to work. That is, the level conversion module provides DVDD3V3 signals and VGL, VGH signals, etc.

[0052] Usually, in addition to providing DVDD3V3 signals and VGL, VGH signals, the level conversion module can also provide AVDD (Analog Voltage Driver), HAVDD (High-Voltage Analog Voltage Driver), DVDD1V8 (1.8V digital power supply voltage), DVDD1V9 (1.9V digital power supply voltage) and other voltages to the LCD panel, and provide GM1 / GM2 / GM3......GM13 / GM14 (assuming that 14 GM nodes are required) Gamma voltage and reference voltage VCOM (VCOM1 / VCOM2) and other voltages to the data driver module (source driver) on the LCD panel. That is, the level conversion module integrates the functions of two chips, PMIC (Power Management IC) and GMIC (Gamma Management IC).

[0053] The liquid crystal panel timing drive circuit provided in the embodiment of the present application is provided with a main control module, a power management module, a level conversion module, a first level conversion module, and a second level conversion module. The main control module 101 controls the timing of the first level conversion module and the second level conversion module, and the power management module provides the power required by the first level conversion module and the second level conversion module. The first level conversion module and the second level conversion module are applied in combination, and more clock signals and start scanning signals are provided, thereby expanding the application scenarios of the panel drive circuit and improving the flexibility of providing timing signals to the panel.

[0054] In some optional implementations of this embodiment, the output ends of the first group of clock signals and the output ends of the second group of clock signals are sequentially and alternately connected to the clock input ends of the liquid crystal panel.

[0055] The staggered connection means that the first clock signal output terminal of the first level conversion module 103, the first clock signal output terminal of the second level conversion module 104, the second clock signal output terminal of the first level conversion module 103, the second clock signal output terminal of the second level conversion module 104, etc. are sequentially connected according to the arrangement order of the clock input terminals of the liquid crystal panel. Figure 2 As shown, the first level conversion module 103 and the second level conversion module 104 both include CK1-CK6 ports, which are alternately connected to 12 clock input ports of the liquid crystal panel, and output 12 clock signals CLK1-CLK12 in sequence according to a preset timing.

[0056] like Figure 3 As shown, it shows the timing diagram of the first group of clock signals (CK1, CK3, CK5, CK7, CK9, CK11) and the second group of clock signals (CK2, CK4, CK6, CK8, CK10, CK12), CKn_LS1 is the clock signal output terminal of the first level conversion module 103, and CKn_LS2 is the clock signal output terminal of the second level conversion module 104.

[0057] In this embodiment, by alternately connecting the output ends of the two groups of clock signals to the clock input ends of the liquid crystal panel in sequence, the first level conversion module and the second level conversion module can continuously output clock signals according to the same signal period. It is only necessary to adjust the starting output time of the first group of clock signals and the second group of clock signals, which helps to stably output a large number of clock signals to the liquid crystal panel.

[0058] In some optional implementations of this embodiment, the first level conversion module 103 is used to:

[0059] At a first starting moment of the first group of clock control signals, each clock signal in the first group of clock signals is output in sequence according to a preset clock output interval time.

[0060] The second level conversion module 104 is used for:

[0061] At the second starting moment of the second group of clock control signals, each clock signal in the second group of clock signals is output in sequence according to the clock output interval time.

[0062] The first starting time is earlier than the second starting time, and the interval between the first starting time and the second starting time is half of the clock output interval.

[0063] As an example, Figure 3 As shown, CPV1 and CPV2 are the first group of clock control signals, and CPV3 and CPV4 are the second group of clock control signals. Time t1 is the first starting time. After the first starting time, the CK port of the first level conversion module 103 outputs CLK1, CLK3, CLK5, CLK7, CLK9, and CLK11 in sequence. The interval time between each two adjacent CLK signals is the same. Time t2 is the second starting time. After the second starting time, the CK port of the second level conversion module 104 outputs CLK2, CLK4, CLK6, CLK8, CLK10, and CLK12 in sequence.

[0064] The timing of the first group of clock signals and the second group of clock signals provided in this embodiment realizes the combination of two level conversion modules, and outputs multiple clock signals to the liquid crystal panel alternately in sequence, so that the circuit can accurately control the scanning timing of various liquid crystal panels.

[0065] In some optional implementations of this embodiment, the clock output interval time is one cycle of the first group of clock control signals and the second group of clock control signals.

[0066] like Figure 3 As shown, the clock output interval is one cycle of CPV1, CPV2, CPV3, and CPV4. The interval between time t1 and time t2 is half a cycle of CPV1 and CPV2.

[0067] By setting the output interval of the clock signal based on the period of the clock control signal, the scanning timing of the liquid crystal panel can be controlled more accurately.

[0068] In some optional implementations of this embodiment, the first group of clock control signals includes a first clock control signal and a second clock control signal, and the second group of clock control signals includes a third clock control signal and a fourth clock control signal. Figure 2 and Figure 3 As shown, CPV1 and CPV2 are the first clock control signal and the second clock control signal, and CPV3 and CPV4 are the third clock control signal and the fourth clock control signal.

[0069] The first level conversion module 103 is used for:

[0070] When the level of the first clock control signal reaches a first preset state, the first level of each clock signal in the first group of clock signals is output in sequence; when the level of the second clock control signal reaches a second preset state, the second level of each clock signal in the first group of clock signals is output in sequence.

[0071] Specifically, the first preset state, the second preset state, the first level, and the second level can be set as required. Figure 3 As shown, the first preset state can be a state from a low level to a high level, that is, a rising edge, and the second preset state is also a rising edge. The first level is a high level and the second level is a low level. That is, at the rising edge of CPV1, the high level of each CLK signal is output, and then, when reaching the rising edge of CPV2, the low level of each CLK signal is output. Thus, the output of the CLK signal is controlled according to the CPV1 and CPV2 signals.

[0072] The second level conversion module 104 is used for:

[0073] When the level of the third clock control signal reaches the first preset state, the first level of each clock signal in the second group of clock signals is output in sequence; when the level of the fourth clock control signal reaches the second preset state, the second level of each clock signal in the second group of clock signals is output in sequence.

[0074] The timing sequence of the clock signal output by the second level conversion module 104 is as follows: Figure 3 As shown, at the rising edge of CPV3, the high level of each CLK signal is output, and then, when reaching the rising edge of CPV4, the low level of each CLK signal is output, thereby completing the control of the output of the CLK signal according to the CPV3 and CPV4 signals.

[0075] It should be noted that Figure 3 The timing diagram shown is only an example. The first preset state and the second preset state can also be set to a falling edge, and the first level and the second level can be Figure 3 The levels shown are opposite.

[0076] This embodiment achieves accurate control of the output timing of the clock signals of the two level conversion units by setting the triggering timing of the output clock signal and setting the duration of the high and low levels of the clock signal.

[0077] Optionally, the number of clock signal output terminals included in the first level conversion module 103 and the second level conversion module 104 may be greater than the number of clock signal input terminals of the liquid crystal panel, that is, some clock signal output terminals may not be connected to the liquid crystal panel. For example, the first level conversion module 103 and the second level conversion module 104 may respectively include 10 clock signal output terminals, namely CK1-CK10. When in use, CK1-CK6 included in each level conversion module can be connected to the liquid crystal panel to output clock signals of 12 channels. In addition, the required clock signal timing can be output in conjunction with the register setting of the level conversion module (for example, set to 6-phase output). When the level conversion module is set to 6-phase clock output, the other 4 CK channels output VGL low level. Since these CK channels are not connected to the panel, they do not affect the waveform given to the panel. Unused CK ports can be used as reserved ports to improve the scalability of the circuit.

[0078] In some optional implementations of this embodiment, the first level conversion module 103 or the second level conversion module 104 is further configured to receive a reset control signal input from the main control module 101 and output a reset signal to the liquid crystal panel.

[0079] The reset signal is used to reset various signals of the input panel at the end of the display phase of a frame of image, so as to wait for the input of the next frame of data. In this embodiment, the STV0 input port in the first level conversion module 103 or the second level conversion module 104 can be used to receive the reset control signal STV0_IN input by the main control module 101 and output the reset signal STV0. Figure 2 As shown, the STV0_IN signal can be input into the first level conversion module 103 , and the first level conversion module 103 can output the STV0 signal.

[0080] In some types of panels, at least three STV signals are usually required to control the scanning timing of a frame of image. For example, in order to light up the special screen H1Line in HSR mode, STV1A and STV1B are required to control the start scanning of odd frames and even frames respectively. In addition, a reset signal at the end of the frame, namely the STV0 signal, is also required. Therefore, this embodiment combines the above-mentioned first start scanning signal and the second start scanning signal to provide three STV signals to the liquid crystal panel to support the driving timing of special types of panels, thereby expanding the application range of the liquid crystal drive circuit.

[0081] In some optional implementations of this embodiment, the first level conversion module 103 and the second level conversion module 104 both include a row drive enable signal output terminal and a low potential voltage output terminal. The row drive enable signal output terminal can output a row drive enable signal LC, and the low potential voltage output terminal is used to output a low potential voltage VSS required by the liquid crystal panel.

[0082] Any row drive enable signal output terminal and any low potential voltage output terminal included in the first level conversion module 103 and the second level conversion module 104 are connected to the liquid crystal panel to output the row drive enable signal and the low potential voltage to the liquid crystal panel.

[0083] like Figure 2 As shown, the row drive enable control signal LC_IN output by the main control module 101 can be input to the first level conversion module 103, and the first level conversion module 103 outputs the row drive enable signal LC1 / LC2. Also, the first level conversion module 103 outputs the low potential voltage VSS1 / VSS2.

[0084] This embodiment outputs a row drive enable signal and a low potential voltage through any row drive enable signal output terminal and any low potential voltage output terminal included in the first level conversion module and the second level conversion module, so that the circuit can provide more row drive enable signal output terminals and low potential voltage output terminals, thereby improving the convenience of use and scalability of the circuit.

[0085] In some optional implementations of this embodiment, the first level conversion module 103 and the second level conversion module 104 are integrated in the same level conversion chip 105 ; the level conversion chip is connected to the main control module 101 and the power management module 102 .

[0086] like Figure 4 As shown, the first level conversion module 103 and the second level conversion module 104 are integrated in the level conversion chip 105. The level conversion chip 105 receives CPV1, CPV2, CPV3, CPV4, STV1A_IN, STV1B_IN, LC_IN, and STV0_IN input by the main control module 101. The level conversion chip 105 outputs clock signals CK1-CK12, start scanning control signals STV1A and STV1B, reset control signal STV0, row drive enable signal LC1 / LC2, and low potential voltage VSS1 / VSS2. In addition, the main control module 101 and the level conversion chip 105 and the power management module 102 can also be connected to each other through a bus to realize communication between the main control module 101 and the level conversion chip 105 and the power management module 102. Figure 4As shown, the bus may be an IIC (Inter-Integrated Circuit) bus, including two communication lines, SDA (data line) and SCL (clock line).

[0087] The power management module 102 can receive an external power supply voltage (12V) and output voltages such as DVDD1V8, DVDD1V9, AVDD, GM1-GM14, VCOM1 / VCOM2, etc.

[0088] This embodiment integrates the first level conversion module and the second level conversion module into the same level conversion chip, which can make the circuit structure more concise, thereby helping to simplify the design and manufacturing process of the circuit and reduce costs. When transmitting signals, longer wires may produce equivalent capacitance and other problems that cause signal transmission delays, and this embodiment can simplify the wiring of discrete component layouts. Since the level conversion chip is small in size, the signal delay between the two start scan control signals caused by the wire connection can be reduced. Figure 5A and Figure 5B As shown, when discrete components are used, there is a delay (T_gap) of about 1 microsecond between STV1A and STV1B. After the first level conversion module and the second level conversion module are integrated into the level conversion chip, the delay between STV1A and STV1B is reduced to 0.

[0089] In some optional implementations of this embodiment, the first level conversion module 103 , the second level conversion module 104 and the power management module 102 are integrated in the same power management chip 106 , and the power management chip 106 is connected to the main control module 101 .

[0090] like Figure 6 As shown, the power management chip 106 includes a first level conversion module 103, a second level conversion module 104 and a power management module 102. The power management chip 106 is externally connected to the main control module 101 and the liquid crystal panel. The internal connection method can refer to Figure 1 , Figure 2 Corresponding embodiment. The power management chip 106 receives CPV1, CPV2, CPV3, CPV4, STV1A_IN, STV1B_IN, LC_IN, and STV0_IN input by the main control module 101, and outputs clock signals CK1-CK12, start scanning control signals STV1A and STV1B, reset control signal STV0, row drive enable signal LC1 / LC2, low potential voltage VSS1 / VSS2, and voltages such as DVDD1V8, DVDD1V9, AVDD, GM1-GM14, and VCOM1 / VCOM2.

[0091] This embodiment integrates the first level conversion module, the second level conversion module and the power management module into the same power management chip, which can further simplify the wiring of the discrete component layout and reduce the signal transmission delay caused by the wiring. It also makes the circuit structure more concise, which helps to simplify the design and manufacturing process of the circuit and reduce costs.

[0092] Figure 7 A schematic diagram of the structure of a display device 700 provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the display device 700 includes: a main board 701, a control board 702 and a liquid crystal panel 703, wherein the main board is connected to the control board, and the control board is connected to the liquid crystal panel. The main board and the control board can be connected by a flat wire containing a plurality of pins. The control board and the liquid crystal panel can be connected by an FFC wire. Usually, the control board is connected to an X-PCB board (such as a LCD panel) on the liquid crystal panel via the FFC wire. Figure 7 XLL, XLR, XRL, XRR) connections in the .

[0093] The main board is provided with a main control module 101 included in the above-mentioned LCD panel timing drive circuit, and the control board is provided with a power management module 102, a first level conversion module 103, and a second level conversion module 104 included in the above-mentioned LCD panel timing drive circuit.

[0094] In this embodiment, the main control module 101 may be a SOC or a chip such as an MCU having functions such as logic operations. The main control module 101 is used to provide timing signals and control signals to the power management module 102, the first level conversion module 103, and the second level conversion module 104. The liquid crystal panel is used to display according to the signal output by the control board.

[0095] The signals output by the power management module 102 , the first level conversion module 103 , and the second level conversion module 104 may be output to the liquid crystal panel through the interface between the control board and the liquid crystal panel.

[0096] Optionally, the first level conversion module 103 and the second level conversion module 104 may be integrated in the same level conversion chip 105, and the level conversion chip 105 and the power management module 102 are arranged on the control board. In addition, the first level conversion module 103, the second level conversion module 104 and the power management module 102 may all be integrated in the same power management chip 106, and the level conversion chip 105 and the power management module 102 are arranged on the control board.

[0097] The display device provided in the embodiment of the present application realizes the joint application of the first level conversion module and the second level conversion module by applying the above-mentioned liquid crystal panel timing drive circuit, provides more clock signals and start scanning signals, thereby expanding the application scenarios of the display device and improving the flexibility of the application of the display device.

[0098] The professionals should further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different circuits to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0099] The steps of the circuits or algorithms described in conjunction with the embodiments disclosed herein may be implemented using hardware, software modules executed by a processor, or a combination of the two. The software modules may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0100] It should be understood that the terms used in the text are only for the purpose of describing specific example embodiments, and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used in the text may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The steps, processes, and operations described in the text are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0101] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A liquid crystal panel timing drive circuit, characterized in that: The circuit comprises: a main control module, a power management module, a first level conversion module, and a second level conversion module; The first level conversion module is connected to the main control module and the liquid crystal panel, and is used to receive a first group of clock control signals and a first start scanning control signal input from the main control module, and output a first group of clock signals and a first start scanning signal to the liquid crystal panel; The second level conversion module is connected to the main control module and the liquid crystal panel, and is used to receive a second group of clock control signals and a second start scanning control signal input from the main control module, and output a second group of clock signals and a second start scanning signal to the liquid crystal panel; The power management module is connected to the level conversion module, and is used to output a clock level to the first level conversion module and the second level conversion module.

2. The circuit according to claim 1, characterized in that The output end of the first group of clock signals and the output end of the second group of clock signals are connected to the clock input end of the liquid crystal panel in sequence and in an alternating manner.

3. The circuit according to claim 2, characterized in that The first level conversion module is used for: At a first starting moment of the first group of clock control signals, outputting each clock signal in the first group of clock signals in sequence according to a preset clock output interval time; The second level conversion module is used for: At the second starting moment of the second group of clock control signals, each clock signal in the second group of clock signals is output in sequence according to the clock output interval time, wherein the first starting moment is earlier than the second starting moment, and the interval time between the first starting moment and the second starting moment is half of the clock output interval time.

4. The circuit according to claim 3, characterized in that The clock output interval time is one cycle of the first group of clock control signals and the second group of clock control signals.

5. The circuit according to claim 3, characterized in that The first group of clock control signals includes a first clock control signal and a second clock control signal, and the second group of clock control signals includes a third clock control signal and a fourth clock control signal; The first level conversion module is used for: When the level of the first clock control signal reaches a first preset state, the first level of each clock signal in the first group of clock signals is output in sequence; when the level of the second clock control signal reaches a second preset state, the second level of each clock signal in the first group of clock signals is output in sequence; The second level conversion module is used for: When the level of the third clock control signal reaches the first preset state, the first level of each clock signal in the second group of clock signals is output in sequence; when the level of the fourth clock control signal reaches the second preset state, the second level of each clock signal in the second group of clock signals is output in sequence.

6. The circuit according to claim 1, characterized in that The first level conversion module or the second level conversion module is further used to receive a reset control signal input from the main control module and output a reset signal to the liquid crystal panel.

7. The circuit according to claim 6, characterized in that The first level conversion module and the second level conversion module both include a row drive enable signal output terminal and a low potential voltage output terminal; Any row drive enable signal output terminal and any low potential voltage output terminal included in the first level conversion module and the second level conversion module are connected to the liquid crystal panel to output the row drive enable signal and the low potential voltage to the liquid crystal panel.

8. The circuit according to claim 1, characterized in that The first level conversion module and the second level conversion module are integrated in the same level conversion chip; the level conversion chip is connected to the main control module and the power management module.

9. The circuit according to claim 1, characterized in that The first level conversion module, the second level conversion module and the power management module are integrated in the same power management chip, and the power management chip is connected to the main control module.

10. A display device, characterized in that: include: A main board, a control board and a liquid crystal panel, wherein the main board is connected to the control board, and the control board is connected to the liquid crystal panel; The main board is provided with a main control module included in the liquid crystal panel timing drive circuit according to any one of claims 1 to 9, and the control board is provided with a power management module, a first level conversion module, and a second level conversion module included in the liquid crystal panel timing drive circuit.

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