Sampling and holding reference circuit applied to multi-channel analog-to-digital converter

Abstract

The invention discloses a sampling and holding reference circuit applied to a multi-channel analog-to-digital converter. The sampling and holding reference circuit comprises an amplifier, a first P-type MOS (Metal Oxide Semiconductor) tube, a second P-type MOS tube, a third P-type MOS tube, a first sampling and holding circuit and a second sampling and holding circuit, in the working interval of the two analog-to-digital converters, the reference voltage of the branch circuit can sample the grid voltage of the main loop circuit and keep the voltage, the voltage is loaded on the grid of the branch circuit through the capacitor, at the moment, the grid of the branch circuit obtains the reference voltage irrelevant to the main loop circuit, and mutual interference between channels is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a sampling and holding reference circuit applied to a multi-channel analog-to-digital converter. Background Art

[0002] In order to increase the speed of analog-to-digital converters, multi-channel interleaved analog-to-digital converters are a common solution. Interleaving N channels is equivalent to increasing the speed of an analog-to-digital converter by N times, and can significantly increase the information processing speed without upgrading the process. However, there are some problems with multi-channel interleaved analog-to-digital converters, the most obvious of which is the crosstalk between channels, especially the interference with the reference voltage. Figure 1 As shown, when two analog-to-digital converters work interleaved, there will be moments when they work simultaneously, such as Figure 1 The yellow area on the clock waveform indicates that the two ADCs are working in overlapped mode. At this time, due to the influence of the capacitor flipping, current will be continuously drawn from the reference voltage, causing interference between the reference voltages of the two channels. Figure 1 As shown in the voltage waveform in , this is equivalent to introducing a mismatch in the reference voltage between channels, which will eventually reduce the accuracy of the interleaved analog-to-digital converter.

[0003] It can be seen that the analog-to-digital converter in the prior art still cannot solve the problem of reference voltage mismatch between multi-channel analog-to-digital converters. To this end, the present application provides a sample-and-hold reference circuit applied to a multi-channel analog-to-digital converter to solve this problem. Summary of the invention

[0004] Therefore, the purpose of the present invention is to provide a sampling and holding reference circuit for a multi-channel analog-to-digital converter, which innovatively introduces a sampling and holding switch into the reference voltage. During the intermittent period of the multi-channel analog-to-digital converter, the gate voltage of the output stage in the reference voltage is sampled and then held, thereby cutting off the path for the reference voltages to influence each other, thereby avoiding the influence of working interference between channels on the reference voltage, reducing the mismatch of reference voltages between channels, and facilitating the realization of higher multi-channel accuracy.

[0005] In order to achieve the above object, the present invention provides a sampling and holding reference circuit applied to a multi-channel analog-to-digital converter, comprising: an amplifier, a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a first sampling and holding circuit and a second sampling and holding circuit;

[0006] The signal output end of the amplifier is connected to the gate of the first P-type MOS tube, the input end of the first sampling and holding circuit, and the input end of the second sampling and holding circuit; the source of the first P-type MOS tube is connected to the first load resistor, the output end of the first sampling and holding circuit is connected to the gate of the second P-type MOS tube, and the output end of the second sampling and holding circuit is connected to the gate of the third P-type MOS tube; the source of the second P-type MOS tube is connected to the first analog-to-digital converter ADC1 and the second load resistor; the source of the third P-type MOS tube is connected to the second analog-to-digital converter ADC2 and the third load resistor.

[0007] Further preferably, the first sample-and-hold circuit and the second sample-and-hold circuit are both connected to energy storage capacitors using transmission gates.

[0008] Further preferably, the first sample-and-hold circuit and the second sample-and-hold circuit both include the following circuit structure:

[0009] An inverter, a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first energy storage capacitor and a second energy storage capacitor;

[0010] The output end of the inverter is connected to the gate of the second PMOS tube and the drain of the third NMOS tube, the gate of the third NMOS tube is connected to the gates of the fifth NMOS tube and the sixth NMOS tube; the source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube and the input signal; the source of the sixth NMOS tube serves as the output end and is grounded by connecting to the second energy storage capacitor;

[0011] The drain of the second PMOS tube is connected to one end of the first energy storage capacitor and the drain of the first PMOS tube, the gate of the first PMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is connected to the drain of the second NMOS tube; the source of the first PMOS tube and the gate of the first NMOS tube are both connected to the high level VDD, and the gate of the second NMOS tube is connected to the clock signal; the other end of the first energy storage capacitor is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the clock signal, and the source is grounded.

[0012] Further preferably, the first sample-and-hold circuit and the second sample-and-hold circuit both use PMOS switches to connect energy storage capacitors.

[0013] Further preferably, the first sample-and-hold circuit and the second sample-and-hold circuit both use NMOS switches to connect energy storage capacitors.

[0014] The sample-and-hold reference circuit for a multi-channel analog-to-digital converter disclosed in the present application has at least the following advantages over the prior art:

[0015] 1. The use of a sample-and-hold reference circuit is equivalent to cutting off the crosstalk between channels on the reference voltage. The stability of the reference voltage will be improved and the mismatch of the multi-channel analog-to-digital converter will be reduced.

[0016] 2. The structure is simple and does not require the design of a new circuit. It only requires the reuse of the sampling and holding circuit, which has strong practicality and economic value. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The reference mutual interference phenomenon of a multi-channel analog-to-digital converter in the background technology is disclosed.

[0018] Figure 2 It is a reference circuit for traditional multi-channel analog-to-digital converter.

[0019] Figure 3 It is a schematic diagram of the structure of the multi-channel analog-to-digital converter of the present invention.

[0020] Figure 4 It is a circuit structure diagram of the sample-and-hold reference circuit in this application.

[0021] Figure 5 It is a waveform comparison diagram of the reference voltage of the two channels in this application. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below through the accompanying drawings and specific embodiments.

[0023] like Figure 3 As shown, a sampling and holding reference circuit for a multi-channel analog-to-digital converter provided by an embodiment of one aspect of the present invention includes: an amplifier, a first P-type MOS transistor P1, a second P-type MOS transistor P2, a third P-type MOS transistor P3, a first sampling and holding circuit and a second sampling and holding circuit;

[0024] The signal output end of the amplifier is connected to the gate of the first P-type MOS transistor MP1, the input end of the first sampling and holding circuit, and the input end of the second sampling and holding circuit; the source of the first P-type MOS transistor P1 is connected to the first load resistor R1, the output end of the first sampling and holding circuit is connected to the gate of the second P-type MOS transistor P2, and the output end of the second sampling and holding circuit is connected to the gate of the third P-type MOS transistor P3; the source of the second P-type MOS transistor P2 is connected to the first analog-to-digital converter ADC1 and the second load resistor R2; the source of the third P-type MOS transistor is connected to the second analog-to-digital converter ADC2 and the third load resistor R3. The first load resistor R1, the second load resistor R2, and the third load resistor R3 are grounded.

[0025] CLK1 is the working clock of ADC1, CLK2 is the working clock of ADC2, and CLK3 is the working clock of the sampling switch in the reference circuit. The sampling switch samples the gate voltage when CLK3 is at a high level, and disconnects the sampling switch when CLK3 is at a low level to maintain the reference voltage and load it on the gate of the branch reference voltage tube, thereby successfully cutting off the path of mutual interference.

[0026] Embodiment 2, as Figure 4 As shown, the first sampling and holding circuit and the second sampling and holding circuit both include the following circuit structure: an inverter NOT, a first PMOS tube MP1, a second PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first energy storage capacitor and a second energy storage capacitor; the output end of the inverter NOT is connected to the gate of the second PMOS tube MP2 and the drain of the third NMOS tube MN3, the gate of the third NMOS tube MN3 is connected to the gates of the fifth NMOS tube MN5 and the sixth NMOS tube MN6; the source of the fifth NMOS tube MN5 is connected to the drain of the sixth NMOS tube MN6 and the input signal; the source of the sixth NMOS tube MN6 serves as an output end and is grounded by connecting to the second energy storage capacitor Chold.

[0027] The drain of the second PMOS tube MP2 is connected to one end of the first energy storage capacitor CAP and the drain of the first PMOS tube MP1, the gate of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN1, and the source of the first NMOS tube MN1 is connected to the drain of the second NMOS tube MN2; the source of the first PMOS tube MP1 and the gate of the first NMOS tube MN1 are both connected to the high level VDD, and the gate of the second NMOS tube MN2 is connected to the clock signal; the other end of the first energy storage capacitor CAP is connected to the drain of the fourth NMOS tube MN4, the gate of the fourth NMOS tube MN4 is connected to the clock signal, and the source is grounded.

[0028] When CK is low, CKB is high, MN4 is turned on, and since the gate of MN2 is also high, MP1 is turned on, and charge is stored in the capacitor CAP. When CK is high, MP1 and MN4 are turned off, and the upper plate of the capacitor is loaded to the gate of the switch tube through the MP2 tube, and the lower plate of the capacitor is loaded at the Vi end. Therefore, VP = Vi + VDD, so that the VGS of the switch tube remains at VDD, and the switch tube has better linearity.

[0029] like Figure 5As shown in the figure, the reference voltage is exactly the same after using the sample and hold circuit. When CK is high, Vi and Vo will be turned on, and the gate voltage will be transmitted to the gate on the reference voltage branch in real time. When CLK3 is low, the sampling switch will be closed, and the voltage signal will be stored in the capacitor Chold. Finally, the voltage of the capacitor will be loaded on the gate of the reference voltage branch.

[0030] like Figure 5 This is the waveform of the two-channel reference voltage after using this patent. Since the interference path is cut off, the two reference voltages are almost the same, thus avoiding the reference voltage mismatch and improving the accuracy of the overall multi-channel analog-to-digital converter.

[0031] Embodiment 2: This embodiment is another form of a sample-and-hold circuit; the first sample-and-hold circuit and the second sample-and-hold circuit both use transmission gates to connect energy storage capacitors.

[0032] The first sample-and-hold circuit and the second sample-and-hold circuit both use PMOS switches to connect energy storage capacitors.

[0033] The first sample-and-hold circuit and the second sample-and-hold circuit both use NMOS switches to connect energy storage capacitors.

[0034] Obviously, the above embodiments are only examples for clear explanation, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from them are still within the protection scope of the invention.

Claims

1. A sample-and-hold reference circuit for a multi-channel analog-to-digital converter, characterized in that: include An amplifier, a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a first sample-and-hold circuit, and a second sample-and-hold circuit; The signal output end of the amplifier is connected to the gate of the first P-type MOS tube, the input end of the first sampling and holding circuit, and the input end of the second sampling and holding circuit; the source of the first P-type MOS tube is connected to the first load resistor, the output end of the first sampling and holding circuit is connected to the gate of the second P-type MOS tube, and the output end of the second sampling and holding circuit is connected to the gate of the third P-type MOS tube; the source of the second P-type MOS tube is connected to the first analog-to-digital converter ADC1 and the second load resistor; the source of the third P-type MOS tube is connected to the second analog-to-digital converter ADC2 and the third load resistor.

2. The sampling and holding reference circuit for a multi-channel analog-to-digital converter according to claim 1, characterized in that: The first sample-and-hold circuit and the second sample-and-hold circuit both use transmission gates to connect energy storage capacitors.

3. The sampling and holding reference circuit for a multi-channel analog-to-digital converter according to claim 1, characterized in that: The first sample-and-hold circuit and the second sample-and-hold circuit both include the following circuit structure: An inverter, a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first energy storage capacitor and a second energy storage capacitor; The output end of the inverter is connected to the gate of the second PMOS tube and the drain of the third NMOS tube, the gate of the third NMOS tube is connected to the gates of the fifth NMOS tube and the sixth NMOS tube; the source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube and the input signal; the source of the sixth NMOS tube serves as the output end and is grounded by connecting to the second energy storage capacitor; The drain of the second PMOS tube is connected to one end of the first energy storage capacitor and the drain of the first PMOS tube, the gate of the first PMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is connected to the drain of the second NMOS tube; the source of the first PMOS tube and the gate of the first NMOS tube are both connected to the high level VDD, and the gate of the second NMOS tube is connected to the clock signal; the other end of the first energy storage capacitor is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the clock signal, and the source is grounded.

4. The sampling and holding reference circuit for a multi-channel analog-to-digital converter according to claim 1, characterized in that: The first sample-and-hold circuit and the second sample-and-hold circuit both use PMOS switches to connect energy storage capacitors.

5. The sampling and holding reference circuit for a multi-channel analog-to-digital converter according to claim 1, characterized in that: The first sample-and-hold circuit and the second sample-and-hold circuit both use NMOS switches to connect energy storage capacitors.

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