Stable zero-delay signal processing system and method, game television and medium

Abstract

The invention provides a stable zero-delay signal processing system and method, a game television and a medium, and particularly relates to the technical field of television systems and signal processing, the system comprises an SOC chip, an FPGA chip, a display and a signal acquisition module; in the game mode, the SOC chip is used for sending a mode switching signal to the FPGA chip, and the SOC chip is also used for receiving and processing a target signal acquired by the signal acquisition module and outputting a first processing signal; the FPGA chip is used for receiving the target signal and the mode switching signal, processing the target signal and outputting a second processing signal; and the display is used for displaying a result corresponding to the first processing signal and / or the second processing signal. According to the system, the architecture of combining the television SOC chip and the FPGA chip is adopted, the hardware circuit structure is simple, the delay can be remarkably reduced, and the system stability can be improved.

Description

Technical Field

[0001] The present invention relates to the field of television systems and signal processing technology, and in particular to a stable zero-delay signal processing system, method, gaming television and medium. Background Art

[0002] At a time when television technology is developing rapidly, gaming TVs, as a new type of television product that combines movie-watching and gaming functions, have been favored by more and more consumers.

[0003] Most current gaming TVs use TV chips based on the Android system. HDMI signals need to go through multiple processing modules from input to display, such as decoding, rendering, scaler processing, image quality processing, MEMC, etc. These processing processes will produce a certain delay. Due to differences in SOC processing performance among different chip manufacturers, the delay from HDMI signal input to screen display ranges from a few milliseconds to tens of milliseconds, and the stability is poor. In addition, in order to improve the viewing experience, traditional TVs optimize image quality processing through motion estimation and motion compensation. However, these image quality processing functions may increase delays in game mode and affect the gaming experience. Therefore, machine manufacturers usually turn off some image quality processing functions in game mode, but even so, it is still difficult to completely eliminate the delay problem.

[0004] It can be seen that the gaming TV in the prior art has the problem of long chip processing delay and poor stability. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a stable zero-delay signal processing system, method, gaming TV and medium, aiming to solve the problem of long chip processing delay and poor stability in gaming TVs in the prior art.

[0006] In order to achieve the above-mentioned object, the first aspect of the present invention provides a stable zero-delay signal processing system, comprising: a SOC chip, an FPGA chip, a display and a signal acquisition module, wherein the signal acquisition module, the SOC chip, the FPGA chip and the display are connected in sequence;

[0007] In the game mode, the SOC chip is used to send a mode switching signal to the FPGA chip, and the SOC chip is also used to receive and process the target signal collected by the signal acquisition module, and output a first processed signal;

[0008] The FPGA chip is used to receive the target signal and the mode switching signal, process the target signal, and output a second processed signal;

[0009] The display is used to display results corresponding to the first processed signal and / or the second processed signal.

[0010] Optionally, the SOC chip is used to send a mode switching signal to the FPGA chip, including:

[0011] The SOC chip is used to connect to the FPGA chip via a communication bus according to a preset extended display identification data timing, and send a mode switching signal to the FPGA chip.

[0012] Optionally, the SOC chip is further used to receive and process the target signal collected by the signal collection module, and output a first processed signal, including:

[0013] Acquire an audio signal from the target signal input by the signal acquisition module;

[0014] In response to receiving the audio signal, the SOC chip processes the audio signal and outputs a first processed signal.

[0015] Optionally, the FPGA chip is used to receive the target signal and the mode switching signal, process the target signal, and output a second processed signal, including:

[0016] Acquire a video signal from the target signal input by a signal acquisition module;

[0017] The FPGA chip switches to the target mode in response to receiving the mode switching signal;

[0018] In the target mode, the FPGA chip processes the video signal in response to receiving the video signal and outputs a second processed signal.

[0019] Optionally, the system further includes a non-gaming mode, wherein:

[0020] In the non-gaming mode, the SOC chip is used to process the target signal and output a VBO signal;

[0021] The FPGA chip is used to receive the VBO signal and perform BYPASS processing, output a third processed signal, and send the third processed signal to the display for display.

[0022] Optionally, when the system switches between the gaming mode and the non-gaming mode, the FPGA chip is used to cache several frames of the VBO signal or the target signal.

[0023] A second aspect of the present invention provides a stable zero-delay signal processing method, which is applied to realize the function of the stable zero-delay signal processing system as described in any one of the above items, and the method comprises:

[0024] In the game mode, the SOC chip sends a mode switching signal to the FPGA chip, inputs the target signal into the SOC chip for processing, and outputs a first processed signal;

[0025] Inputting the target signal and the mode switching signal into the FPGA chip for processing, and outputting a second processed signal;

[0026] The results corresponding to the first processed signal and / or the second processed signal are displayed on a display.

[0027] Furthermore, the method further comprises:

[0028] In non-gaming mode, the target signal is input into the SOC chip for processing and the VBO signal is output;

[0029] The FPGA chip receives the VBO signal and performs BYPASS processing, outputs a third processed signal, and sends the third processed signal to the display for display.

[0030] A third aspect of the present invention provides a gaming TV, comprising a memory, a processor, and a stable zero-delay signal processing program stored in the memory and executable on the processor, wherein the stable zero-delay signal processing program implements any one of the steps of the above-mentioned stable zero-delay signal processing method when executed by the processor.

[0031] A fourth aspect of the present invention provides a computer-readable storage medium, on which a stable zero-delay signal processing program is stored. When the stable zero-delay signal processing program is executed by a processor, the step of any one of the above-mentioned stable zero-delay signal processing methods is implemented.

[0032] Compared with the prior art, the beneficial effects of this solution are as follows:

[0033] The system adopts an architecture that combines the TV SOC chip and the FPGA chip. In the game mode, the SOC chip is used to send a mode switching signal to the FPGA chip, process the audio signal in the target signal, and output the first processing signal; the FPGA chip is used to receive the target signal and the mode switching signal, process the video signal in the target signal, output the second processing signal, and finally display the processing result on the display. In the non-game mode, the SOC chip is used to process the target signal and output the VBO signal; the FPGA chip is used to receive the VBO signal and perform BYPASS processing, output the third processing signal and display it on the display. The system has a simple hardware circuit structure, can reduce the playback delay of audio and video signals to the microsecond level, and can significantly improve the system stability; at the same time, it can significantly improve the flexibility of switching between different modes, and can effectively solve the conflict between image quality processing and game mode, thereby greatly improving the user's viewing and gaming experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0035] Figure 1 It is a block diagram of a stable zero-delay signal processing system of the present invention;

[0036] Figure 2 A signal flow diagram of a stable zero-delay signal processing system of the present invention;

[0037] Figure 3 A flow chart of a stable zero-delay signal processing method of the present invention;

[0038] Figure 4 This is a flow chart of another stable zero-delay signal processing method of the present invention;

[0039] Figure 5 It is a schematic diagram of the structure of the gaming television of the present invention. DETAILED DESCRIPTION

[0040] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0041] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0042] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0043] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0044] As used in this specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0045] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0047] The existing gaming TV has the problem of long chip processing delay and poor stability, as well as conflicts between image quality processing and game mode. A stable zero-delay signal processing system and method are proposed, which mainly adopts an architecture combining a TV SOC chip and an FPGA chip. The system includes an SOC chip, an FPGA chip, a display and a signal acquisition module. The signal acquisition module, the SOC chip, the FPGA chip and the display are connected in sequence; in the game mode, the SOC chip is used to send a mode switching signal to the FPGA chip, and the SOC chip is also used to receive and process the target signal collected by the signal acquisition module and output a first processing signal; the FPGA chip is used to receive the target signal and the mode switching signal, and process the target signal and output a second processing signal; the display is used to display the results corresponding to the first processing signal and / or the second processing signal. In the non-game mode, the SOC chip is used to process the target signal and output a VBO signal; the FPGA chip is used to receive the VBO signal and perform BYPASS processing, output a third processing signal, and send the third processing signal to the display for display. The system has a simple hardware circuit structure, can reduce the playback delay of audio and video signals to microseconds, and can significantly improve system stability. At the same time, it can significantly improve the flexibility of switching between different modes, effectively solve the conflict between image quality processing and game mode, and can greatly improve the user's viewing and gaming experience.

[0048] The embodiment of the present invention provides a stable zero-delay signal processing system, which is deployed on electronic devices such as computers and servers and is applied to scenarios where a gaming TV can be used to flexibly switch between watching movies and playing games. Specifically, the architecture of the system in this embodiment is as follows Figure 1As shown, it mainly includes a TV system-level SOC chip, an FPGA chip, a display and a signal acquisition module. The signal acquisition module, the SOC (System on a Chip) chip, the FPGA chip and the display are connected in sequence through data lines and interfaces, and the signal acquisition module is also connected to the FPGA chip, and the SOC chip is also connected to the display. Among them, the SoC chip refers to a system-level chip or a system on a chip, which integrates all the contents and embedded software of the entire TV system such as the processor, memory, input and output interface, system software, etc. on a silicon chip to form a single, complete integrated circuit. Since the screen panel of the TV determines the lower limit of the TV picture quality, and the TV chip determines the upper limit of the TV picture quality, in fact, the TV SoC chip is equivalent to the brain of the TV and the core of the TV. The SoC chip of the TV will be responsible for three types of work: maintaining the operation of the system and applications, video decoding, and picture processing. Therefore, the resolution of the TV display can be improved by selecting a TV SoC chip with good performance to enhance the user's visual experience. FPGA (Field-Programmable Gate Array) is a field programmable gate array, which is a programmable logic device. Users can program it through hardware description languages ​​(such as VHDL or Verilog) to implement various digital circuit functions, such as digital signal processing, microprocessor design and other complex digital logic applications. In this embodiment, multiple circuit function modules are integrated on the FPGA chip to assist the circuit function modules corresponding to the SOC chip to realize their corresponding functions. That is, the SOC chip and FPGA chip selected in this embodiment have a mutually dependent and complementary relationship in terms of function.

[0049] The system of this embodiment includes a game mode and a non-game mode, which can enable the game TV to switch between the game mode and the non-game mode quickly, flexibly and stably. The non-game mode is not limited to the movie watching mode, and can also be any other mode that is different from the game mode that can be realized by other game TVs. Figure 2 Detailed description of the detailed process of the system achieving stable zero-delay signal processing in both gaming and non-gaming modes:

[0050] After the TV is turned on, the SOC chip is initialized, and then the SOC chip initializes the FPGA chip. The FPGA chip uses the VBO (Video Back Out) signal BYPASS mode by default to display the normal display screen of the game TV. In the default BYPASS mode, the FPGA chip can provide a simple and fast signal path, saving the resources inside the chip for processing VBO signals, so that the video signal can be transmitted with lower latency, which is conducive to improving the real-time performance of video display. The VBO signal refers to a video output signal emitted by the system-level SOC chip of the game TV. It is used to transmit the video signal processed by the SOC chip to an external device, that is, to send the processed video picture information to the display for display. The video picture information includes image brightness, color (such as RGB information), resolution and other information.

[0051] When the video TV is working in the game mode, the SOC chip is used to send a mode switching signal to the FPGA chip to control the FPGA chip to switch from the default VBO signal BYPASS mode to the signal channel mode matching the target signal collected by the acquisition module. For example, if the target signal is an HDMI signal, the FPGA chip is switched to the HDMI channel mode. The SOC chip is also used to receive and process the target signal collected by the signal acquisition module and output a first processed signal; the FPGA chip is used to receive the target signal and the mode switching signal, perform mode switching according to the mode switching signal, and output a second processed signal after processing the target signal; the display is used to display the result corresponding to the first processed signal and / or the second processed signal, that is, the display output is the picture display and sound combination effect after being processed by the SOC chip and the FPGA chip. The target signal refers to the audio and video source signal transmitted to the SOC chip through one or more signal channels of the television system. The type of the signal channel can be various types of channels that can be used for signal transmission, such as HDMI channel, TYPE C interface channel or DP (DisplayPort) interface channel. The embodiments of the present invention mainly use HDMI signals as research objects to exemplarily introduce signal transmission and processing processes, but the protection scope of the present invention is not limited to using HDMI channels to input target signals to SOC signals.

[0052] It should be stated that in order to ensure the real-time transmission of the target signal in this embodiment, the FPGA chip is used to assist the SOC chip in processing part of the processing tasks of the target signal, that is, the SOC chip implements part of the processing tasks in the processing steps of decoding, rendering, scaling (scaler), color correction, motion estimation and motion compensation (MEMC) of the audio and video signals in the target signal, and the rest is transmitted to the FPGA chip to complete. This not only saves the resource usage of the SOC chip in processing the target signal, but also improves the real-time display of the picture and the playback of the sound on the display.

[0053] In this embodiment, when the video TV is working in the game mode, the SOC chip is used to control the FPGA chip to switch the corresponding signal channel mode according to the type of the target signal, and the FPGA chip is used to assist the SOC chip in performing the target signal processing task, which effectively improves the processing efficiency and timeliness of the target signal and can significantly improve the smoothness of the audio and video data displayed on the display.

[0054] In a preferred embodiment, the SOC chip is used to send a mode switching signal to the FPGA chip, including:

[0055] The SOC chip is used to connect to the FPGA chip via a communication bus according to a preset extended display identification data timing, and send a mode switching signal to the FPGA chip.

[0056] Specifically, the SOC chip selects the appropriate Extended Display Identification Data (EDID) timing and transmits it to the FPGA chip through the Inter-Integrated Circuit (I2C or IIC) interface, and sends a mode switching signal and communication information such as resolution setting to the FPGA chip through the General Purpose Input / Output (GPIO) interface, wherein the mode switching signal refers to a target mode that enables the FPGA chip to receive and process the target signal according to the communication mode of the target signal. For example, assuming that the target signal is an HDMI signal, the SOC chip sends an HDMI channel mode switching signal to the FPGA chip.

[0057] Furthermore, a signal distributor chip is provided in the signal acquisition module, and the signal distributor chip is used to divide the target signal into two paths when the system is in the game mode, one path enters the SOC chip, and the other path enters the FPGA chip. Then, the SOC chip is also used to receive and process the target signal collected by the signal acquisition module, and output a first processed signal, including:

[0058] Acquire an audio signal from the target signal input by the signal acquisition module;

[0059] In response to receiving the audio signal, the SOC chip processes the audio signal and outputs a first processed signal.

[0060] Specifically, the SOC chip responds to the audio signal in a target signal transmitted by the signal distributor chip in the signal acquisition module, and after pre-processing such as enhancement, echo cancellation, and noise suppression on the audio signal, decodes and scales the audio signal to restore the compressed audio data to an optimized digital audio signal, i.e., a first processed signal, which is then converted into an analog signal through a digital-to-analog converter and played through an audio output device such as a speaker to ensure the playback sound effect of the audio signal.

[0061] Further, the FPGA chip is used to receive the target signal and the mode switching signal, and process the target signal to output a second processed signal, including:

[0062] The FPGA chip switches to the target mode in response to receiving the mode switching signal;

[0063] Acquire a video signal from the target signal input by a signal acquisition module;

[0064] In the target mode, the FPGA chip processes the video signal in response to receiving the video signal and outputs a second processed signal.

[0065] Specifically, the FPGA chip switches to the target mode in response to receiving a mode switching signal, and then receives the video signal in another target signal transmitted by the signal distributor chip in the signal acquisition module, and decodes, renders, scales (scaler), performs color correction, MEMC and other image quality optimization processing on the video signal, and then outputs an optimized video signal, i.e., the second processed signal, to ensure the resolution and frame rate of the video signal, thereby ensuring the picture display effect of the video signal.

[0066] Furthermore, a low-voltage differential signaling (LVDS) interface is used to connect the SOC chip and the FPGA chip to the display respectively, and the first processed signal and the second processed signal are output to the display, so that the signal processing result received by the display has the characteristics of low power consumption, low bit error rate, low crosstalk and low radiation.

[0067] In this embodiment, a parallel processing strategy of using a SOC chip to process audio signals and using an FPGA chip to process video signals can significantly improve the system's processing efficiency for target signals, and with the assistance of the FPGA chip, each functional module of the SOC chip can be maximized, thereby improving resource utilization and system stability.

[0068] In a preferred embodiment, when the video TV operates in non-gaming mode, the SOC chip is used to process the target signal and output a VBO signal; the FPGA chip is used to receive the VBO signal and perform BYPASS processing, output a third processed signal, and send the third processed signal to the display for display.

[0069] Specifically, when the video TV is working in non-gaming mode, the target signal is input to the SOC chip, and the audio and video signals in the target signal are processed by the SOC chip to generate a VBO signal. The mode switching signal is then transmitted to the FPGA chip through the I2C communication bus or the GPIO interface, and the VBO signal is transmitted to the FPGA chip; after receiving the mode switching signal, the FPGA chip switches to the VBO input mode, and performs BYPASS processing on the received VBO signal, that is, the VBO signal is directly transmitted to the subsequent logic operation or data processing unit without any intermediate processing or conversion, and a third processed signal is output, and the third processed signal is sent to the display for display.

[0070] The signal processing strategy implemented in the video TV working in non-gaming mode can reduce the transmission delay of the signal inside the FPGA chip and improve the real-time performance of signal processing; avoid the possibility of introducing additional noise or distortion by excessive processing or conversion of the signal to maintain the original integrity and accuracy of the signal; at the same time, when the internal resources of the FPGA chip are limited, BYPASS processing can avoid the occupation of unnecessary processing units or circuits, thereby saving resources for other more important tasks.

[0071] Furthermore, when the system switches between the game mode and the non-game mode, the FPGA chip is used to cache several frames of the VBO signal or the target signal.

[0072] Specifically, the selection of the working mode of the game TV can be achieved by the user controlling the remote control and displaying the menu. During the switching process between different modes, ensure that the FPGA chip caches several frames of the VBO signal or the target signal. Specifically, when the video TV works in the game mode, control the FPGA chip to cache at least one frame of the video signal; when the video TV works in the non-game mode, control the FPGA chip to cache at least one frame of the VBO signal to ensure that there is no screen distortion or flickering during the mode switching process.

[0073] In summary, the stable zero-delay signal processing system for gaming TV designed by the present invention adopts a combined architecture of SOC chip and FPGA chip, and has a simple hardware circuit structure. When switching modes, it is only necessary to adjust the signal path, which can reduce the playback delay of audio and video signals to a few microseconds, close to zero delay, and significantly improve the stability of the system. At the same time, the system achieves flexible switching of different modes by adjusting the signal path, effectively solving the conflict between image quality processing and game mode, and by caching signal frames in the FPGA chip, the display interface smoothly transitions during the switching process of different modes, thereby greatly improving the user's game viewing experience.

[0074] like Figure 3 As shown, corresponding to the function of realizing the above-mentioned stable zero-delay signal processing system, the embodiment of the present invention further provides a stable zero-delay signal processing method, and the above-mentioned stable zero-delay signal processing method includes:

[0075] Step S100: In the game mode, the SOC chip sends a mode switching signal to the FPGA chip, inputs the target signal into the SOC chip for processing, and outputs a first processed signal;

[0076] Step S200: inputting the target signal and the mode switching signal into the FPGA chip for processing, and outputting a second processed signal;

[0077] Step S300: Displaying the result corresponding to the first processed signal and / or the second processed signal on a display.

[0078] In one embodiment, Figure 4 As shown, the method also includes:

[0079] Step S400: In non-gaming mode, the target signal is input into the SOC chip for processing and a VBO signal is output;

[0080] Step S500: The FPGA chip receives the VBO signal and performs BYPASS processing, outputs a third processed signal, and sends the third processed signal to the display for display.

[0081] Specifically, in this embodiment, the specific functions of the above-mentioned stable zero-delay signal processing method can also refer to the corresponding description in the above-mentioned stable zero-delay signal processing system, which will not be repeated here.

[0082] Based on the above embodiments, the present invention further provides a gaming television, whose principle block diagram can be shown as follows: Figure 5 As shown. The above-mentioned game TV includes a processor, a memory, a network interface and a display connected through a system bus. Among them, the processor of the game TV is used to provide computing and control capabilities. The memory of the game TV includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a stable zero-delay signal processing program. The internal memory provides an environment for the operating system in the non-volatile storage medium and the operation based on the stable zero-delay signal processing program. The network interface of the game TV is used to communicate with an external terminal through a network connection. When the stable zero-delay signal processing program is executed by the processor, the steps of any one of the above-mentioned stable zero-delay signal processing methods are implemented. The display of the game TV can be a liquid crystal display or an electronic ink display.

[0083] Those skilled in the art will understand that Figure 5 The principle block diagram shown in the figure is only a block diagram of a partial structure related to the scheme of the present invention, and does not constitute a limitation on the game TV to which the scheme of the present invention is applied. A specific game TV may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0084] In one embodiment, a gaming TV is provided, comprising a memory, a processor, and a stable zero-delay signal processing program stored in the memory and executable on the processor, wherein the stable zero-delay signal processing program, when executed by the processor, implements the steps of any one of the stable zero-delay signal processing methods provided in the embodiments of the present invention.

[0085] An embodiment of the present invention also provides a computer-readable storage medium, on which a stable zero-delay signal processing program is stored. When the stable zero-delay signal processing program is executed by a processor, the steps of any stable zero-delay signal processing method provided by the embodiment of the present invention are implemented.

[0086] It should be understood that the serial numbers of the steps in the above embodiments do not imply a sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0087] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the above-mentioned device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0088] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0089] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0090] In the embodiments provided by the present invention, it should be understood that the disclosed apparatus / terminal equipment and method can be implemented in other ways. For example, the apparatus / terminal equipment embodiments described above are only illustrative, for example, the division of the above modules or units is only a logical function division, and in actual implementation, other division methods can be used, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0091] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, it should be understood by those skilled in the art that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features therein may be replaced by equivalents. However, these modifications or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A stable zero-delay signal processing system, characterized in that: The system comprises: a SOC chip, an FPGA chip, a display and a signal acquisition module, wherein the signal acquisition module, the SOC chip, the FPGA chip and the display are connected in sequence; In the game mode, the SOC chip is used to send a mode switching signal to the FPGA chip, and the SOC chip is also used to receive and process the target signal collected by the signal acquisition module, and output a first processed signal; The FPGA chip is used to receive the target signal and the mode switching signal, process the target signal, and output a second processed signal; The display is used to display results corresponding to the first processed signal and / or the second processed signal.

2. The stable zero-delay signal processing system according to claim 1, characterized in that: The SOC chip is used to send a mode switching signal to the FPGA chip, including: The SOC chip is used to connect to the FPGA chip via a communication bus according to a preset extended display identification data timing, and send a mode switching signal to the FPGA chip.

3. The stable zero-delay signal processing system according to claim 2, characterized in that: The SOC chip is also used to receive and process the target signal collected by the signal collection module, and output a first processed signal, including: Acquire an audio signal from the target signal input by the signal acquisition module; In response to receiving the audio signal, the SOC chip processes the audio signal and outputs a first processed signal.

4. The stable zero-delay signal processing system according to claim 2, characterized in that: The FPGA chip is used to receive the target signal and the mode switching signal, process the target signal, and output a second processed signal, including: Acquire a video signal from the target signal input by a signal acquisition module; The FPGA chip switches to the target mode in response to receiving the mode switching signal; In the target mode, the FPGA chip processes the video signal in response to receiving the video signal and outputs a second processed signal.

5. The stable zero-delay signal processing system according to claim 1, characterized in that: The system also includes a non-gaming mode, wherein: In the non-gaming mode, the SOC chip is used to process the target signal and output a VBO signal; The FPGA chip is used to receive the VBO signal and perform BYPASS processing, output a third processed signal, and send the third processed signal to the display for display.

6. The stable zero-delay signal processing system according to claim 5, characterized in that: When the system switches between the game mode and the non-game mode, the FPGA chip is used to cache several frames of the VBO signal or the target signal.

7. A stable zero-delay signal processing method, characterized in that: Applied to realize the function of the stable zero-delay signal processing system according to any one of claims 1 to 6, the method comprising: In the game mode, the SOC chip sends a mode switching signal to the FPGA chip, inputs the target signal into the SOC chip for processing, and outputs a first processed signal; Inputting the target signal and the mode switching signal into the FPGA chip for processing, and outputting a second processed signal; The results corresponding to the first processed signal and / or the second processed signal are displayed on a display.

8. The stable zero-delay signal processing method according to claim 7, characterized in that: The method further comprises: In non-gaming mode, the target signal is input into the SOC chip for processing and the VBO signal is output; The FPGA chip receives the VBO signal and performs BYPASS processing, outputs a third processed signal, and sends the third processed signal to the display for display.

9. A gaming television, characterized in that: The gaming TV comprises a memory, a processor, and a stable zero-delay signal processing program stored in the memory and executable on the processor. When the stable zero-delay signal processing program is executed by the processor, the function of the stable zero-delay signal processing system as described in any one of claims 1 to 6 is realized, or the steps of the stable zero-delay signal processing method as described in any one of claims 7 to 8 are realized.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a stable zero-delay signal processing program, which, when executed by a processor, implements the functions of a stable zero-delay signal processing system as described in any one of claims 1 to 6, or implements the steps of a stable zero-delay signal processing method as described in any one of claims 7 to 8.

Images