SiC device for reducing short-circuit current and preparation method
By forming a P zone at the bottom of the SiC Drift layer of the SiC MOSFET device, the problem of poor short-circuit capability of the device during short-circuit is solved, lower temperature rise and higher short-circuit capability are achieved, while maintaining the outflow of the device's linear region ability.
Patent Information
- Application Number
- CN202411544390.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-11
AI Technical Summary
The short circuit capability of SiC MOSFET devices during short circuits is poor, resulting in rapid increase in temperature rise and easy burnout. Therefore, it is necessary to reduce the short circuit current of the device in the saturation zone to improve short circuit capability and safety stability.
The P region is formed at the bottom of the JFET of the SiC Drift layer. When the device is operating in the saturation region, the P region is connected to the depletion layer formed by the Pwell region and the SiC Drift layer to better shield the short circuit current.
It effectively reduces the temperature rise of SiC MOSFET devices during short circuit, improves the short circuit capability and safety stability of the device, and does not affect the outflow capability of the device in the linear region.
Smart Images
Figure CN119421440A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC device for reducing short-circuit current and a preparation method thereof. Background Art
[0002] As a typical representative of the third generation wide bandgap semiconductor materials, SiC has many significant physical property advantages, such as large bandgap width, high critical breakdown electric field, small intrinsic carrier concentration, fast saturation drift velocity, high melting point, high thermal conductivity, etc. These material properties enable power devices made of SiC to achieve performance advantages such as large breakdown voltage, low conduction loss, and high switching frequency with small size and thin thickness, and have great advantages in high voltage, high temperature, high frequency, high radiation and other application fields. At present, SiC MOSFET has been widely used in the market to replace Si IGBT and other devices.
[0003] When the gate of SiC MOSFET device is open and working normally, it is divided into two intervals: linear region and saturation region. When the device is short-circuited, it is working in the saturation region. Compared with SiIGBT, the short-circuit capability of SiC MOSFET device is very poor, and its short-circuit tolerance time is only about 3us. When short-circuited, the temperature rise of the device will increase rapidly, and it is very easy to burn the device. Therefore, the short-circuit characteristics of SiC MOSFET have always been fully considered in the early stage of design to avoid failures on the system side. Therefore, it is a technical problem that urgently needs to be solved to develop a device that reduces the short-circuit current of SiC MOSFET devices in the saturation region, achieves higher short-circuit capability of the device, and improves the safe and stable use of the device. Summary of the invention
[0004] In view of the above problems, the present invention provides a SiC device and a preparation method for reducing short-circuit current, which can reduce the temperature rise of the device when it is short-circuited and avoid excessively affecting the current discharge capacity of the device when it works in the linear region.
[0005] The technical solution of the present invention is: A method for preparing a SiC device for reducing short-circuit current comprises the following steps: S100, depositing a SiC Drift layer on the top surface of the SiC Sub layer, and implanting a P region on the top surface of the SiC Drift layer; S200, depositing a SiC Epi layer on the top surface of the SiC Drift layer, and sequentially injecting into the SiC Epi layer to form a Pwell region, a NP region, and a PP region; S300, forming a gate oxide layer, a Poly layer and an isolation dielectric layer in sequence on the top surface of the SiC Epi layer; S400, forming an ohmic contact alloy layer on the top surfaces of the NP region and the PP region; S500, sputtering metal above the device to form a front electrode metal layer.
[0006] Specifically, in step S100, the thickness of the SiC Drift layer is 5um-20um, and the doping concentration is 1E15-5E16cm -2 .
[0007] Specifically, in step S100, the depth from the bottom surface of the P region to the top surface of the SiC Drift layer is 0.3um-0.5um, and the doping concentration is 1E17-3E18cm -2 .
[0008] Specifically, in step S200, the thickness of the SiC Epi layer is 1.5um-3um, and the doping concentration is 1E15-1E17cm -2 .
[0009] Specifically, in step S200, the depth of the bottom surface of the Pwell region from the top surface of the SiC Epi layer is 0.4um-1.5um, and the doping concentration is 1E17-3E18cm -2 .
[0010] Specifically, in step S200, the depth of the bottom surface of the NP region from the top surface of the SiC Epi layer is 0.2um-1um, and the doping concentration is 1E18-1E19cm -2 .
[0011] Specifically, in step S200, the depth from the bottom surface of the PP region to the top surface of the SiC Epi layer is 0.2um-1.2um, and the doping concentration is 5E18-1E19cm -2 .
[0012] Specifically, in step S700 , the thickness of the gate oxide layer is 30 nm-70 nm.
[0013] A SiC device for reducing short-circuit current, comprising a SiC Sub layer, a SiC Drift layer, a SiC Epi layer, a gate oxide layer, a Poly layer, an isolation dielectric layer and a front electrode metal layer arranged in sequence from bottom to top; The top surface of the SiC Drift layer is provided with a P region extending downward; The SiC Epi layer includes: A pair of Pwell regions are provided, each extending downward from the top surface of the SiC Epi layer; the pair of Pwell regions are spaced apart and have a spacing from the bottom surface of the SiC Epi layer; A pair of NP regions are provided, each extending downward from the top surface of the Pwell region; a gap is provided between the bottom surface of the NP region and the Pwell region; a gap is provided between the side of the NP region and the side of the Pwell region; A pair of PP zones are provided, each extending downward from the top surface of the Pwell zone and located at the side of the NP zone; The bottom surface of the gate oxide layer is respectively connected to the top surfaces of the NP region, the Pwell region and the SiC Epi layer; The isolation dielectric layer is wrapped on the gate oxide layer and the Poly layer, and the side portion extends downward to be connected to the NP region; The side of the isolation dielectric layer is provided with an ohmic contact alloy layer respectively connected to the PP region and the NP region.
[0014] Specifically, the bottom surface of the front electrode metal layer is connected to the isolation dielectric layer and the ohmic contact alloy layer respectively.
[0015] In the present invention, a P region is formed at the bottom of the JFET of the SiC Drift layer in the SiC MOSFET device. When the device works in the saturation region, the P region and the depletion layer formed by the Pwell region and the SiC Drift layer are connected to each other, thereby better shielding the short-circuit current and reducing the temperature rise of the device when short-circuited. At the same time, when the device works in the linear region, because the drain voltage is small, the depletion layer formed by the P region and the SiC Drift layer will not be connected to the depletion layer formed by the Pwell region, thereby not excessively affecting the outflow capacity of the device when working in the linear region. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 Schematic diagram of SiC MOSFET of the present invention working in the linear region; Figure 2 is a schematic diagram of the SiC MOSFET of the present invention operating in the saturation region; Figure 3 is a structural schematic diagram of step S100 of the present invention; Figure 4 is a schematic structural diagram of step S200 of the present invention; Figure 5 is a schematic structural diagram of step S300 of the present invention; Figure 6 is a schematic structural diagram of step S400 of the present invention; Figure 7 is a schematic structural diagram of step S500 of the present invention; Figure 8 is a schematic diagram of the structure of step S600 of the present invention; Fig. 9 is a schematic diagram of the structure of step S700 of the present invention; Fig.10 is a structural schematic diagram of step S800 of the present invention; Fig.11 is a structural schematic diagram of step S900 of the present invention; Fig.12 is a structural schematic diagram of step S1000 of the present invention; Fig.13 is a schematic diagram of the structure of step S1100 of the present invention; In the figure, 1 is SiC Sub layer, 2 is SiCDrift layer, 3 is P region, 4 is SiC Epi layer, 5 is Pwell region, 6 is NP region, 7 is PP region, 8 is gate oxide layer, 9 is Poly layer, 10 is isolation dielectric layer, 11 is ohmic contact alloy layer, and 12 is front electrode metal layer. DETAILED DESCRIPTION
[0017] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.
[0018] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0019] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0020] A SiC device for reducing short-circuit current comprises the following steps: S100, forming a SiC Drift layer 2 on the top surface of the SiC Sub layer 1 by epitaxial deposition; In step S100, the thickness of SiC Sub layer 1 is 100um-400um, and the doping concentration is 1E19-3E19cm -2 ; SiCDrift layer 2 thickness is 5um-20um, doping concentration is 1E15-5E16cm -2 .
[0021] S200, forming a P region 3 on the top surface of the SiC Drift layer 2 by Al ion implantation; The depth of the bottom surface of the P region 3 from the top surface of the SiC Drift layer 2 in step S200 is 0.3um-0.5um, and the doping concentration is 1E17-3E18cm -2 .
[0022] S300, forming a SiC Epi layer 4 on the top surface of the SiC Drift layer 2 again by epitaxial deposition; The thickness of the SiC Epi layer 4 in step S300 is 1.5um-3um, and the doping concentration is 1E15-1E17cm -2 .
[0023] S400, forming a pair of spaced Pwell regions 5 on the top surface of the SiC Epi layer 4 by Al ion implantation; The depth of the bottom surface of the Pwell region 5 from the top surface of the SiC Epi layer 4 in step S400 is 0.4um-1.5um, and the doping concentration is 1E17-3E18cm -2 .
[0024] S500, forming an NP region 6 on the top surface of the Pwell region 5 by N ion implantation; The depth of the bottom surface of the NP region 6 from the top surface of the SiC Epi layer 4 in step S500 is 0.2um-1um, and the doping concentration is 1E18-1E19cm -2 .
[0025] S600, forming a PP region 7 on the top surface of the Pwell region 5 by Al ion implantation, and then activating all implanted regions by high temperature ion annealing; The depth of the bottom surface of the PP region 7 from the top surface of the SiC Epi layer 4 in step S600 is 0.2um-1.2um, and the doping concentration is 5E18-1E19cm -2 .
[0026] S700, forming a gate oxide layer 8 by introducing oxygen into the top surface of the SiC Epi layer 4 for high temperature dry oxygen oxidation; The thickness of the gate oxide layer 8 in step S700 is 30 nm-70 nm.
[0027] S800, forming a Poly layer 9 on the top surface of the gate oxide layer 8 by polysilicon deposition; S900, forming an isolation dielectric layer 10 on the top surfaces of the NP region 6 and the Poly layer 9 by oxide deposition; S1000, forming an ohmic contact alloy layer 11 on the top surfaces of the NP region 6 and the PP region 7 by sputtering Ni metal followed by thermal annealing; The Ni metal thickness in step S1000 is 0.3um-1um.
[0028] S1100, forming a front electrode metal layer 12 on the top of the device by sputtering Ti and AlCu metals; In step S1100 , the thickness of the Ti metal is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.
[0029] A SiC device for reducing short-circuit current comprises a SiC Sub layer 1, a SiC Drift layer 2, a SiC Epi layer 4, a gate oxide layer 8, a Poly layer 9, an isolation dielectric layer 10 and a front electrode metal layer 12 which are arranged in sequence from bottom to top; The top surface of the SiC Drift layer 2 is provided with a P region 3 extending downward; The SiC Epi layer 4 is provided with: A pair of Pwell regions 5 are provided, each extending downward from the top surface of the SiC Epi layer 4; the pair of Pwell regions 5 are spaced apart and have a spacing from the bottom surface of the SiC Epi layer 4; A pair of NP regions 6 are provided, each extending downward from the top surface of the Pwell region 5; a gap is provided between the NP region 6 and the bottom surface of the Pwell region 5; a gap is provided between the side of the NP region 6 and the side of the Pwell region 5; A pair of PP zones 7 are provided, each extending downward from the top surface of the Pwell zone 5 and located at the side of the NP zone 6; The bottom surface of the gate oxide layer 8 is connected to the top surfaces of the NP region 6, the Pwell region 5 and the SiC Epi layer 4 respectively; The isolation dielectric layer 10 is wrapped on the gate oxide layer 8 and the Poly layer 9, and the side portion extends downward to be connected to the NP region 6; The side of the isolation dielectric layer 10 is provided with an ohmic contact alloy layer 11 connected to the PP region 7 and the NP region 6 respectively.
[0030] The bottom surface of the front electrode metal layer 12 is connected to the isolation dielectric layer 10 and the ohmic contact alloy layer 11 respectively.
[0031] When the gate of SiC MOSFET is open and working normally, it is divided into two intervals: linear region and saturation region. When the device is short-circuited, it is working in the saturation region. Compared with SiIGBT, the short-circuit capability of SiC MOSFET devices is very poor, and its short-circuit tolerance time is only about 3us. When short-circuited, the temperature rise of the device will increase rapidly, and the device is very easy to burn out. Therefore, if the short-circuit current of SiC MOSFET devices in the saturation region can be reduced, a higher short-circuit capability of the device can be achieved, and the safe and stable use of the device can be improved. In the present invention, in the SiC MOSFET device, a P region 3 is formed at the bottom of the JFET of the SiC Drift layer. When the device is working in the saturation region (such as Figure 2 As shown in the figure, the depletion layer formed by the P region 3, the Pwell region 5 and the SiC Drift layer 2 will be connected to each other, thereby better shielding the short-circuit current and reducing the temperature rise of the device during short circuit. At the same time, when the device works in the linear region (such as Figure 1 As shown in the figure), because the drain voltage is small, the depletion layer formed by the P region 3 and the SiC Drift layer 2 will not be connected to the depletion layer formed by the Pwell region 5, thereby not excessively affecting the outflow capacity of the ID current when the device works in the linear region.
Claims
1. A method for preparing a SiC device for reducing short-circuit current, characterized in that: The steps include: S100, depositing a SiC Drift layer (2) on the top surface of the SiC Sub layer (1), and implanting a P region (3) on the top surface of the SiC Drift layer (2); S200, depositing a SiC Epi layer (4) on the top surface of the SiC Drift layer (2), and sequentially injecting into the SiC Epi layer (4) to form a Pwell region (5), an NP region (6), and a PP region (7); S300, forming a gate oxide layer (8), a Poly layer (9) and an isolation dielectric layer (10) in sequence on the top surface of the SiC Epi layer (4); S400, forming an ohmic contact alloy layer (11) on the top surfaces of the NP region (6) and the PP region (7); S500, metal is sputtered above the device to form a front electrode metal layer (12).
2. A method for preparing a SiC device for reducing short-circuit current according to claim 1, characterized in that: In step S100, the thickness of the SiC Drift layer (2) is 5um-20um, and the doping concentration is 1E15-5E16cm -2 .
3. The method for preparing a SiC device for reducing short-circuit current according to claim 1, characterized in that: In step S100, the depth of the bottom surface of the P region (3) from the top surface of the SiC Drift layer (2) is 0.3um-0.5um, and the doping concentration is 1E17-3E18cm -2 .
4. The method for preparing a SiC device for reducing short-circuit current according to claim 1, characterized in that: In step S200, the thickness of the SiC Epi layer (4) is 1.5um-3um, and the doping concentration is 1E15-1E17cm -2 .
5. The method for preparing a SiC device for reducing short-circuit current according to claim 1, characterized in that: In step S200, the depth of the bottom surface of the Pwell region (5) from the top surface of the SiC Epi layer (4) is 0.4um-1.5um, and the doping concentration is 1E17-3E18cm -2 .
6. The method for preparing a SiC device for reducing short-circuit current according to claim 1, characterized in that: In step S200, the depth of the bottom surface of the NP region (6) from the top surface of the SiC Epi layer (4) is 0.2um-1um, and the doping concentration is 1E18-1E19cm -2 .
7. The method for preparing a SiC device for reducing short-circuit current according to claim 1, characterized in that: In step S200, the depth of the bottom surface of the PP region (6) from the top surface of the SiC Epi layer (4) is 0.2um-1.2um, and the doping concentration is 5E18-1E19cm -2 .
8. The method for preparing a SiC device for reducing short-circuit current according to claim 1, characterized in that: In step S700, the thickness of the gate oxide layer (8) is 30nm-70nm.
9. A SiC device for reducing short-circuit current, prepared by the method for preparing a SiC device for reducing short-circuit current according to any one of claims 1 to 8, characterized in that: It comprises a SiC Sub layer (1), a SiC Drift layer (2), a SiC Epi layer (4), a gate oxide layer (8), a Poly layer (9), an isolation dielectric layer (10) and a front electrode metal layer (12) which are arranged in sequence from bottom to top; The top surface of the SiC Drift layer (2) is provided with a P region (3) extending downward; The SiC Epi layer (4) is provided with: A pair of Pwell regions (5) are provided, each extending downward from the top surface of the SiC Epi layer (4); the pair of Pwell regions (5) are arranged at intervals and have a spacing from the bottom surface of the SiC Epi layer (4); A pair of NP regions (6) are provided, each extending downward from the top surface of the Pwell region (5); a gap is provided between the NP region (6) and the bottom surface of the Pwell region (5); a gap is provided between the side of the NP region (6) and the side of the Pwell region (5); A pair of PP zones (7) are provided, each extending downward from the top surface of the Pwell zone (5) and located at the side of the NP zone (6); The bottom surface of the gate oxide layer (8) is respectively connected to the top surfaces of the NP region (6), the Pwell region (5) and the SiC Epi layer (4); The isolation dielectric layer (10) is wrapped on the gate oxide layer (8) and the Poly layer (9), with the side portion extending downward and connected to the NP region (6); The side of the isolation dielectric layer (10) is provided with an ohmic contact alloy layer (11) connected to the PP region (7) and the NP region (6) respectively.
10. The SiC device for reducing short-circuit current according to claim 9, characterized in that: The bottom surface of the front electrode metal layer (12) is respectively connected to the isolation dielectric layer (10) and the ohmic contact alloy layer (11).