Semiconductor structure for high electron mobility transistor

Abstract

A semiconductor structure for a high electron mobility transistor includes a substrate, a nucleating layer, a superlattice layer, a first gradient layer, a second gradient layer, a voltage-withstanding layer, a channel layer, and a barrier layer. The nucleating layer is located on the substrate, the superlattice layer is located on the nucleating layer, the superlattice layer is composed of high-aluminum layers and low-aluminum layers in an alternating mode, and the high-aluminum layers and the low-aluminum layers are arranged repeatedly. The superlattice layer has an average aluminum content of 70% to 90%. The first gradient layer is located on the lattice layer, wherein the average aluminum content of the first gradient layer is 40%-70%. The second gradient layer is located on the first gradient layer, wherein the average aluminum content of the second gradient layer is 30%-40%. The second gradient layer is located on the nucleating layer, the pressure-resistant layer is located on the second gradient layer, the channel layer is located on the pressure-resistant layer, the barrier layer is located on the channel layer, and the thickness range from the nucleating layer to the barrier layer is 700 nm to 3000 nm.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure for a high electron mobility transistor. Background Art

[0002] For high electron mobility transistors (HEMTs), vertical withstand voltage and structural stability are very important. However, since the semiconductor structure used for high electron mobility transistors is a very densely stacked layer-by-layer structure, there are many methods for improving the vertical withstand voltage in the prior art, such as Taiwan Patent Publication No. I678723B, US Patent Publication No. US9233844, US11942521B2, US8592823B2, US9245991, etc. However, the aforementioned cases do not mention how to improve the vertical withstand voltage of the semiconductor structure of the high electron mobility transistor (HEMT) working at medium voltage (100V to 250V), and these cases do not mention how to reduce the dynamic resistance of the semiconductor structure of the high electron mobility transistor used for medium voltage (100V to 250V). Therefore, how to improve the vertical withstand voltage, dynamic resistance and structural stability of the semiconductor structure of the high electron mobility transistor with a withstand voltage below 250V is indeed a topic worth studying. Summary of the invention

[0003] The main purpose of the present invention is to provide a semiconductor structure having a single alternating superlattice layer and multiple gradient layers so that a high electron mobility transistor has a higher vertical withstand voltage and a smaller dynamic resistance.

[0004] To achieve the above-mentioned purpose, the semiconductor structure for high electron mobility transistor of the present invention includes a substrate, a nucleation layer, a superlattice layer, a first gradient layer, a second gradient layer, a voltage-resistant layer, a channel layer, and a barrier layer. The nucleation layer is located on the substrate, and the superlattice layer is located on the nucleation layer, wherein the superlattice layer is composed of high aluminum layers and low aluminum layers alternately, and the alternating composition is repeated for many times. The average aluminum composition of the superlattice layer is 70% to 90%. The first gradient layer is located on the lattice layer, wherein the average aluminum composition of the first gradient layer is 40% to 70%. The second gradient layer is located on the first gradient layer, wherein the average aluminum composition of the second gradient layer is 30% to 40%. The voltage-resistant layer is located on the second gradient layer, the channel layer is located on the voltage-resistant layer, and the barrier layer is located on the channel layer, wherein the thickness range from the nucleation layer to the barrier layer is between 700nm and 3000nm.

[0005] According to an embodiment of the present invention, a high electron mobility transistor using the semiconductor structure of the present invention is a high electron mobility transistor with a withstand voltage of less than 250V.

[0006] The present invention uses a single alternating superlattice layer with a repeated arrangement to reduce the dynamic resistance of the semiconductor structure, and the present invention allows the average aluminum content of the gradient layer close to the voltage-resistant layer in the two gradient layers to be between 30% and 40% to improve the vertical voltage resistance of the semiconductor structure, thereby allowing the high electron mobility transistor using the semiconductor structure of the present invention to have a higher vertical voltage resistance, smaller dynamic resistance and better structural stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of an embodiment of a semiconductor structure for a high electron mobility transistor of the present invention;

[0008] Figure 2 is a comparison diagram of the breakdown voltages of the second graded layer of the semiconductor structure of the present invention when the average aluminum content is greater than 30% and less than 30%;

[0009] Figure 3A is a schematic diagram of a reference sample for testing dynamic resistance and a schematic diagram of a semiconductor structure for a high electron mobility transistor of the present invention for testing dynamic resistance;

[0010] Figure 3B It is a dynamic resistance measurement comparison diagram of the semiconductor structure for high electron mobility transistor of the present invention and a reference sample which does not use the superlattice structure of the present invention.

[0011]

Explanation of symbols

[0012] Semiconductor structure 1, 1a

[0013] Substrate 10, 91

[0014] Nucleation layer 20, 92

[0015] Superlattice layer 30

[0016] High aluminum layer 31

[0017] Low aluminum layer 32

[0018] First gradient layer 41, 94

[0019] Second gradient layer 42, 95

[0020] Pressure-resistant layer 50, 96

[0021] Channel layer 60, 94

[0022] Barrier layer 70

[0023] Reference sample 90

[0024] Gradient layer 93

[0025] Thickness H, h1, h2, h3 DETAILED DESCRIPTION

[0026] For a better understanding of the present invention, please refer to Figure 1 and Figure 2 A schematic diagram of an embodiment of a semiconductor structure for a high electron mobility transistor of the present invention and a comparison diagram of the breakdown voltage of the second graded layer of the semiconductor structure for a high electron mobility transistor of the present invention with an average aluminum content greater than 30% and less than 30%.

[0027] like Figure 1 As shown, in this embodiment, the semiconductor structure 1 for a high electron mobility transistor of the present invention includes a substrate 10, a nucleation layer 20, a superlattice layer 30, a first graded layer 41, a second graded layer 42, a voltage-resistant layer 50, a channel layer 60, and a barrier layer 70.

[0028] The nucleation layer 20 is located on the substrate 10, and the superlattice layer 30 is located on the nucleation layer 20, wherein the superlattice layer 30 is composed of high aluminum layers 31 and low aluminum layers 32 alternately, and the alternating composition is repeated for multiple times, wherein the average aluminum content of the superlattice layer 30 is 70% to 90%. The first gradient layer 41 is located on the superlattice layer 30, wherein the average aluminum content of the first gradient layer 41 is 40% to 70%. The second gradient layer 42 is located on the first gradient layer 41, wherein the average aluminum content of the second gradient layer 42 is 30% to 40%. The voltage-resistant layer 50 is located on the second gradient layer 42, the channel layer 60 is located on the voltage-resistant layer 50, and the barrier layer 70 is located on the channel layer 60, wherein the thickness from the nucleation layer 20 to the barrier layer 70 is H, and the range of H is between 700nm and 3000nm.

[0029] In addition, if Figure 2 As shown, the average aluminum content of the second gradient layer 42 of this embodiment is greater than 30%, for example, 34% or 35%, which can make the breakdown voltage (vertical withstand voltage) of the HEMT transistor using the conductor structure 1 of the present invention reach 250V, which is significantly better than the breakdown voltage (200V) that can be achieved when the average aluminum content of the second gradient layer 42 is less than 30%. Therefore, by setting the average aluminum content of the second gradient layer 42 to between 30% and 40%, the breakdown voltage (vertical withstand voltage) of the semiconductor structure using the present invention can be increased.

[0030] like Figure 1As shown, in this embodiment, the semiconductor structure 1 of the present invention is suitable for a high electron mobility transistor with a withstand voltage of less than 250V (medium voltage), the substrate 10 is a P-type silicon substrate (p-type Silicon), the nucleation layer 20 is an aluminum nitride (AlN) layer, the superlattice layer 30 is composed of a high aluminum layer 31 and a low aluminum layer 32, and the low aluminum layer 32 contacts the nucleation layer 20, and the high aluminum layer 31 is stacked on the low aluminum layer 32. The high aluminum layer 31 of this embodiment is an aluminum nitride (AlN) layer, and the low aluminum layer 32 is an aluminum gallium nitride (AlGaN) layer, but the present invention is not limited to this embodiment, as long as it is composed of high aluminum layers 31 and low aluminum layers 32 alternately, and the average aluminum content of the superlattice layer 30 is between 70% and 90%, the present invention is applicable.

[0031] According to a specific embodiment of the present invention, the thickness of the nucleation layer 20 is 150nm, the thickness of the high aluminum layer 31 is 5nm, the thickness of the low aluminum layer 32 is 20nm, and the superlattice layer 30 is iron-doped, and its doping concentration is between 5E16 and 5E18, and the high aluminum layer 31 and the low aluminum layer 32 are alternately stacked and repeated 6 times, so that the thickness of the superlattice layer 30 becomes 150nm.

[0032] like Figure 1 As shown, in this embodiment, the first gradient layer 41 is Al x Ga 1-x N layer, the second graded layer 42 is Al y Ga 1-y N layers, wherein x is, for example, 0.55, so that the average aluminum content of the first gradient layer 41 is 40% to 70%, and y is, for example, 0.34, so that the average aluminum content of the second gradient layer 41 is 30% to 40%. At the same time, in this embodiment, the thickness h2 of the first gradient layer 41 is less than the thickness h1 of the second gradient layer 42, and the thickness h1 of the second gradient layer 42 is greater than the thickness h3 of the superlattice layer 30. According to a specific embodiment of the present invention, the relationship among the thickness h1 of the second gradient layer 42, the thickness h2 of the first gradient layer 41 and the thickness h3 of the superlattice layer 30 is h1>h2>h3. It should be noted here that, because the average aluminum content of the first gradient layer 41 is 40% to 70% and the average aluminum content of the second gradient layer 42 is 30% to 40%, in general, X>Y, but the present invention is not limited thereto, and X and Y are independent variables.

[0033] According to a specific embodiment of the present invention, the first gradient layer 41 and the second gradient layer 42 are iron-doped, and the iron doping concentration of the first gradient layer 41 is between 5E16 and 5E18, and the second gradient layer 42 is iron-and carbon-doped, wherein the iron doping concentration of the second gradient layer is between 5E16 and 5E18, and the carbon doping concentration of the second gradient layer is between 1E17 and 1E20. In this embodiment, the voltage-resistant layer 50 is a gallium nitride (GaN) layer, and the thickness of the voltage-resistant layer 50 is greater than the thickness of the second gradient layer 42. The voltage-resistant layer 50 of this embodiment has a thickness of 500nm and is carbon-doped, and the carbon doping concentration is between 1E17 and 1E20. The channel layer 60 of this embodiment is a gallium nitride (GaN) layer with a thickness of 300nm to increase the vertical voltage resistance of the semiconductor structure 1 of the present invention. The barrier layer 70 of this embodiment is an aluminum gallium nitride (AlGaN) layer.

[0034] Please refer to the following Figure 3A , Figure 3B With the following table 1, Figure 3A is a schematic diagram of a reference sample for testing dynamic resistance and a schematic diagram of a semiconductor structure for a high electron mobility transistor of the present invention for testing dynamic resistance, Figure 3B 1 is a comparison diagram of dynamic resistance measurements of the semiconductor structure for a high electron mobility transistor according to an embodiment of the present invention and a reference sample 90 that does not use the superlattice layer 30 structure of the present invention.

[0035] like Figure 3A As shown, the structure of the reference sample 90 used for testing includes a substrate 91, a nucleation layer 92, a gradient layer 93, a first gradient layer 94, a second gradient layer 95, a voltage-resistant layer 96 and a channel layer 97, wherein the substrate 91 is a P-type silicon substrate. The nucleation layer 92 is an aluminum nitride (AlN) layer with a thickness of 150nm. The gradient layer 93 is an AlGaN layer with a thickness of 300nm and iron doping, and the aluminum content in the gradient layer 93 is 70.2%. The first gradient layer 94 is an AlGaN layer with a thickness of 300nm and an aluminum content of 55.6%, and the second gradient layer 95 is an AlGaN layer with a thickness of 400nm and an aluminum content of 34.2%. The voltage-resistant layer 96 is a gallium nitride (GaN) layer with a thickness of 500nm and carbon doping; the channel layer 97 is a gallium nitride (GaN) layer with a thickness of 300nm.

[0036] like Figure 3AAs shown, the structure and composition of the substrate 10, nucleation layer 20, voltage-resistant layer 50, and channel layer 60 of the semiconductor structure 1a of the present invention used for testing are exactly the same as the substrate 91, nucleation layer 92, voltage-resistant layer 96, and channel layer 97 of the reference sample 90. The superlattice layer 30 of the semiconductor structure 1a used for testing is 150nm thick, with an aluminum content of 71.1% and iron doping. The first gradient layer 41 is an AlGaN layer with a thickness of 300nm and an aluminum content of 55.3%, and the second gradient layer 42 is an AlGaN layer with a thickness of 400nm and an aluminum content of 34.2%.

[0037] Depend on Figure 3B As can be seen from Table 1, the semiconductor structure 1a of the high electron mobility transistor of the present invention is compared with the reference sample 90 which does not use the superlattice layer 30 of the present invention, and the dynamic resistance of the semiconductor structure 1a of the high electron mobility transistor of the present invention is significantly lower than that of the reference sample 90. It can be seen that the superlattice layer 30 of the present invention can indeed reduce the dynamic resistance of the semiconductor structure 1a, thereby making the high electron mobility transistor using the semiconductor structure 1a of the present invention have better device characteristics, making the device of the high electron mobility transistor using the semiconductor structure element 1a of the present invention stable and electrically stable, and at the same time, the superlattice layer 30 of the present invention can also enhance the structural strength of the semiconductor structure 1a.

[0038]

[0039] Table 1. Comparison of dynamic resistance between reference sample and the present invention

[0040] The present invention uses a single alternating composition repeatedly arranged superlattice layer 30 and the average aluminum content contained in the superlattice layer 30 is between 70% and 90% to reduce the dynamic resistance of the semiconductor structure 1, 1a. The present invention allows the average aluminum content of the second gradient layer 42 close to the voltage-resistant layer in the two gradient layers to be between 30% and 40% to improve the vertical voltage resistance of the semiconductor structure 1, thereby allowing the high electron mobility transistor using the semiconductor structure 1, 1a of the present invention to have higher vertical voltage resistance and smaller dynamic resistance and structural stability, thereby improving the deficiencies of the previous technology.

[0041] It should be noted that the above embodiments are merely examples for the purpose of illustration, and the scope of rights claimed by the present invention should be based on the claims, rather than being limited to the above embodiments.

Claims

1. A semiconductor structure for a high electron mobility transistor, characterized in that: The semiconductor structure comprises: a substrate; a nucleation layer located on the substrate; a superlattice layer located on the nucleation layer, wherein the superlattice layer is composed of a high aluminum layer and a low aluminum layer alternately, and the alternating composition is repeated multiple times, wherein the average aluminum content of the superlattice layer is 70% to 90%; a first graded layer located on the superlattice layer, wherein the average aluminum content of the first graded layer is 40% to 70%; a second gradient layer, located on the first gradient layer, wherein the average aluminum content of the second gradient layer is 30% to 40%; a pressure-resistant layer, located on the second graded layer; a channel layer, located on the pressure-resistant layer; and A barrier layer is located on the channel layer, wherein the thickness of the nucleation layer to the barrier layer ranges from 700 nm to 3000 nm.

2. The semiconductor structure according to claim 1, wherein: The high electron mobility transistor is a high electron mobility transistor with a withstand voltage of 250V or less.

3. The semiconductor structure according to claim 1, wherein: The thickness of the first gradient layer is less than the thickness of the second gradient layer.

4. The semiconductor structure according to claim 3, characterized in that The first graded layer is Al x Ga 1-x N layer, the second gradient layer 42 is Al y Ga 1-y N layer, and the first gradient layer and the second gradient layer are doped with iron.

5. The semiconductor structure according to claim 1, wherein: The thickness of the second graded layer is greater than the thickness of the superlattice layer.

6. The semiconductor structure according to claim 1, wherein: The high aluminum layer is an AlN layer, and the low aluminum layer is an AlGaN layer.

7. The semiconductor structure according to claim 1, wherein: The voltage-resistant layer is carbon-doped.

8. The semiconductor structure according to claim 1, wherein: The superlattice layer has iron doping.

9. The semiconductor structure according to claim 1, wherein: The second graded layer is doped with carbon and iron.

10. The semiconductor structure according to claim 1, wherein: The first graded layer is doped with iron.

11. The semiconductor structure according to claim 1, wherein: The substrate is a P-type silicon substrate.

12. The semiconductor structure according to claim 1, wherein: The low aluminum layer contacts the nucleation layer.

13. The semiconductor structure according to claim 1, wherein: The thickness of the voltage-resistant layer is greater than the thickness of the second gradient layer.

14. The semiconductor structure according to claim 1, wherein: The thickness of the channel layer is smaller than the thickness of the pressure-resistant layer.

15. The semiconductor structure according to claim 1, wherein: The carbon doping concentration of the voltage-resistant layer and the second gradient layer is between 1E17 and 1E20.

16. The semiconductor structure according to claim 1, wherein: The iron doping concentrations of the first graded layer, the second graded layer and the superlattice layer are respectively between 5E16 and 5E18.

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