Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel. The array substrate comprises a substrate, a thin film transistor and an adjusting layer. The thin film transistor is located on the substrate and comprises an active layer, and the active layer comprises a channel region. The adjusting layer is located between the substrate and the active layer, the adjusting layer is provided with a plurality of concave-convex structures, and the orthographic projection of at least one concave-convex structure on the substrate falls in the orthographic projection of the channel region on the substrate. In the array substrate with the structure, the problem of a Mura phenomenon caused by non-uniformity of TFT (Thin Film Transistor) performance parameters is favorably improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to an array substrate and a display panel. Background Art

[0002] Organic Light Emitting Display (OLED) can be divided into two categories according to the driving mode: Passive Matrix OLED (PMOLED) and Active Matrix OLED (AMOLED), namely direct addressing and thin film transistor (TFT) matrix addressing. AMOLED is usually used as a large-size display device with high definition due to its high luminous efficiency.

[0003] AMOLED display devices are current-driven. However, due to the limitations of the crystallization process, the manufacturing process of the backplane TFT is uneven, which will make the performance parameters of TFTs at different positions non-uniform. This non-uniformity will be converted into brightness differences and perceived by the human eye, namely the Mura phenomenon, which affects the display effect and user experience. Summary of the invention

[0004] The present disclosure provides an array substrate and a display panel. By arranging a concave-convex structure corresponding to a channel region of a thin film transistor on the array substrate, defects are introduced into the TFT, thereby improving the sensitivity of the TFT driving voltage, thereby reducing the brightness difference between TFTs in different regions, and further improving the Mura phenomenon caused by the non-uniformity of TFT performance parameters.

[0005] In a first aspect, the present disclosure provides an array substrate, which includes a substrate, a thin film transistor and an adjustment layer located on the substrate. The thin film transistor includes an active layer, the active layer includes a channel region, the adjustment layer is located between the substrate and the active layer, the adjustment layer has a plurality of concave-convex structures, and the orthographic projection of at least one concave-convex structure on the substrate falls within the orthographic projection of the channel region on the substrate.

[0006] In the above scheme, the concave-convex structure in the adjustment layer corresponding to the channel region affects the crystallization effect of the channel region, introduces defects in the thin film transistor, reduces the sensitivity of the thin film transistor to driving voltage fluctuations, thereby reducing the display brightness difference at different positions and improving the Mura phenomenon.

[0007] In a specific embodiment of the first aspect of the present disclosure, the adjustment layer is provided with a plurality of grooves, and the concavo-convex structure includes the grooves.

[0008] In the above solution, by configuring the concavo-convex structure to be a groove, the Mura phenomenon can be improved while reducing the influence on the thickness of the array substrate in a direction perpendicular to the substrate.

[0009] In a specific embodiment of the first aspect of the present disclosure, at least one groove is located on a surface of the adjustment layer facing away from the substrate, or at least one groove penetrates the adjustment layer.

[0010] In the above scheme, by adjusting the depth of the groove in the adjustment layer (in the height perpendicular to the substrate direction), the characteristics of the corresponding thin film transistor can be adjusted, and the characteristics of the thin film transistors at different positions can be adjusted to different degrees to achieve uniform display brightness.

[0011] In a specific embodiment of the first aspect of the present disclosure, the orthographic projection of the groove on the substrate is linear, and the grooves are spaced apart from each other. For example, further, the active layer further includes a source region and a drain region, the channel region is located between the source region and the drain region, the orthographic projections of the source region and the drain region on the substrate are linear, respectively, and the angle between the orthographic projection of the groove on the substrate and the orthographic projection of the source region on the substrate is an acute angle or a right angle.

[0012] In the above scheme, the groove is arranged in a linear shape, which facilitates the processing of the groove and reduces the processing cost.

[0013] In a specific embodiment of the first aspect of the present disclosure, the plurality of grooves include a plurality of first-type grooves and a plurality of second-type grooves, and the plurality of first-type grooves and the second-type grooves intersect each other to form a grid-like structure. For example, further, the active layer further includes a source region and a drain region, the channel region is located between the source region and the drain region, the orthographic projections of the source region and the drain region on the substrate are respectively straight-line-shaped, and the angle between the orthographic projection of the first-type groove on the substrate and the orthographic projection of the source region on the substrate is a right angle. For example, further, the angle between the orthographic projection of the second-type groove on the substrate and the orthographic projection of the source region on the substrate is a right angle.

[0014] In the above scheme, the grooves that finally present a grid-like structure can evenly adjust the characteristics of thin film transistors at different positions, which is beneficial to improving the Mura phenomenon.

[0015] In a specific embodiment of the first aspect of the present disclosure, the orthographic projection of the channel region on the substrate is in the shape of a straight line.

[0016] In the above solution, the linear channel region is easy to process, thereby reducing the processing cost of the array substrate.

[0017] In a specific embodiment of the first aspect of the present disclosure, at least part of the orthographic projection of the channel region on the substrate is in a curved shape. For example, further, the orthographic projection of the channel region on the substrate is an arc curve, a wavy curve, or an X-shaped curve.

[0018] In the above solution, at least part of the channel region is in a curved shape, which improves the driving capability of the corresponding thin film transistor, thereby reducing the risk of delay problems.

[0019] In a specific embodiment of the first aspect of the present disclosure, the adjustment layer is a light shielding layer, and the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the thin film transistor on the substrate.

[0020] In the above solution, the adjustment layer can adjust the characteristics of the thin film transistors in the array substrate and reduce the influence of light on the characteristics of the thin film transistors, thereby reducing the probability of leakage current in the channel region.

[0021] In a specific embodiment of the first aspect of the present disclosure, the adjustment layer is a conductive layer, the conductive layer includes a plurality of spaced-apart light shielding portions and at least one circuit structure portion, the orthographic projection of the light shielding portion on the substrate covers the orthographic projection of the thin film transistor on the substrate, and the circuit structure portion is insulated from the light shielding portion. For example, further, the circuit structure portion includes an electrostatic lead-out line.

[0022] In the above scheme, by setting the adjustment layer to have the functions of shading, introducing defects into the channel region and other functions such as electrostatic discharge, one adjustment layer plays at least three roles, which optimizes the structural design of the array substrate.

[0023] In a specific embodiment of the first aspect of the present disclosure, the thin film transistor includes a gate layer, a gate insulating layer and a source-drain electrode layer. The gate layer is located on the substrate, the gate layer includes at least one gate electrode, and the orthographic projection of the channel region on the substrate is located within the orthographic projection of the gate electrode on the substrate. The gate insulating layer is located between the gate layer and the active layer. The source-drain electrode layer is connected to the active layer, the active layer includes a source region and a drain region, the channel region is located between the source region and the drain region, the source-drain electrode layer includes a source and a drain, the source is connected to the source region, and the drain is connected to the drain region.

[0024] A second aspect of the present disclosure provides a display panel, which includes the array substrate in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a planar structure of an array substrate provided in one embodiment of the present disclosure.

[0026] Figure 2 A cross-sectional schematic diagram of an array substrate provided in one embodiment of the present disclosure.

[0027] Figure 3 A cross-sectional schematic diagram of an array substrate provided in one embodiment of the present disclosure.

[0028] Figure 4 A cross-sectional schematic diagram of an array substrate provided in one embodiment of the present disclosure.

[0029] Figure 5 for Figure 1 An enlarged view of the array substrate A is shown.

[0030] Figure 6 for Figure 1 An enlarged view of the array substrate A is shown.

[0031] Figure 7 for Figure 1 An enlarged view of the array substrate A is shown.

[0032] Figure 8 for Figure 1 An enlarged view of the array substrate A is shown.

[0033] Fig. 9 for Figure 1 An enlarged view of the array substrate A is shown.

[0034] Fig.10 A cross-sectional schematic diagram of an array substrate provided in one embodiment of the present disclosure.

[0035] Fig.11 A cross-sectional schematic diagram of a display panel provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0037] The embodiments of the present disclosure provide an array substrate and a display panel. By providing an adjustment layer having a concave-convex structure corresponding to a channel region of a thin film transistor, the sensitivity of the thin film transistor to a change in a driving voltage is changed, so that under the same driving voltage change, the fluctuation of the drain current change becomes smaller, thereby reducing the fluctuation of the display brightness of the display panel having the array substrate, thereby improving the Mura phenomenon.

[0038] At least one embodiment of the present disclosure provides an array substrate. The array substrate includes a substrate, a thin film transistor and an adjustment layer. The thin film transistor is located on the substrate and includes an active layer, and the active layer includes a channel region. The adjustment layer is located between the substrate and the active layer, and the adjustment layer has a plurality of concave-convex structures, and the orthographic projection of at least one concave-convex structure on the substrate falls within the orthographic projection of the channel region on the substrate. In this way, by setting the concave-convex structure, the channel region of the thin film transistor corresponding to the concave-convex structure is affected during the preparation process due to the interface height difference generated by the concave-convex structure, which affects the crystallization effect of the channel region, thereby reducing the carrier mobility of the thin film transistor, increasing the subthreshold swing, and thereby reducing the driving sensitivity of the thin film transistor, so that under the same driving voltage change, the drain current change fluctuation of the thin film transistor at different positions is small, so that the brightness difference at different positions is reduced, and the Mura phenomenon is improved.

[0039] It should be noted that the subthreshold swing is a performance indicator that measures the conversion rate between the on and off states of a thin film transistor. It represents the change in gate voltage (driving voltage) required for a tenfold change in source-drain current, also known as the S factor. The smaller the S, the faster the ON / OFF rate. S is numerically equal to the gate voltage increment ΔV required to change the drain current Ids by one order of magnitude. g The S value is related to the device structure and temperature. The reverse bias of the substrate will reduce the surface depletion layer capacitance CD, and the S value will decrease. The presence of interface traps will increase a trap capacitance in parallel with CD, and increase the S value. When the temperature rises, the S value will also increase.

[0040] The array substrate and the display panel in at least one embodiment of the present disclosure are described below in conjunction with the accompanying drawings. In addition, as shown in the accompanying drawings, in at least one embodiment of the present disclosure, a spatial rectangular coordinate system is established with the surface where the array substrate is located as a reference to define the positions of the various film layers in the array substrate. In the spatial rectangular coordinate system, the X-axis and the Y-axis are parallel to the surface where the array substrate is located, and the Z-axis is perpendicular to the surface where the array substrate is located.

[0041] In at least one embodiment of the present disclosure, Figure 1 and Figure 2As shown, the array substrate includes a substrate 110, a thin film transistor TFT located on one side of the substrate 110, and an adjustment layer 130 located between the thin film transistor TFT and the substrate 110. The thin film transistor TFT includes an active layer 120, a gate layer 124, a gate insulating layer 126 between the active layer 120 and the gate layer 124, a first insulating layer 128 and a second insulating layer 129, and a source-drain electrode layer 127. The gate layer 124 is located on the substrate 110, and the gate layer 124 includes at least one gate electrode 125, and the orthographic projection of the channel region 121 on the substrate 110 is located within the orthographic projection of the gate electrode 125 on the substrate 110. The active layer 120 includes a source region 122, a drain region 123, and a channel region 121 located between the source region 122 and the drain region 123. The channel region 121 refers to the region where the active layer 120 and the gate layer 124 overlap. The first insulating layer 128 is located on the side of the active layer 120 away from the substrate 110, and the second insulating layer 129 is located on the side of the first insulating layer 128 away from the substrate 110. The source-drain electrode layer 127 is connected to the active layer 120, and the source-drain electrode layer 127 includes a source 127a and a drain 127b, the source 127a is connected to the source region 122, and the drain 127b is connected to the drain region 123. The adjustment layer 130 is located between the substrate 110 and the active layer 120, and the adjustment layer 130 has a plurality of concave-convex structures 131, such as a plurality of protrusions, and the orthographic projection of at least one concave-convex structure 131 on the substrate 110 falls within the orthographic projection of the channel region 121 on the substrate 110.

[0042] In the preparation process of the array substrate disclosed in the present invention, after the adjustment layer 130 is formed on one side of the substrate 110, an amorphous silicon layer is deposited on the side of the adjustment layer 130 away from the substrate 110. Then, the amorphous silicon layer is patterned to form an active layer 120 including a source region 122, a drain region 123 and a channel region 121. After impurities are doped into the source region 122 and the drain region 123 by ion implantation, the doped active layer 120 is heat treated to activate the impurities and cause the active layer 120 to undergo metal-induced crystallization and metal-induced lateral crystallization in sequence. Specifically, metal-induced crystallization occurs in the source region 122 and the drain region 123, and metal-induced lateral crystallization occurs in the channel region 121, and finally the active layer 120 is transformed from amorphous silicon to polycrystalline silicon. However, due to the concave-convex structure 131 on the adjustment layer 130, there is a height difference in the film layer formed in the channel region 121 corresponding to the concave-convex structure 131, which will affect the crystallization effect of the channel region 121 during metal-induced lateral crystallization. By introducing defects (interface traps) in the channel region 121, the subthreshold swing of the thin-film transistor TFT having the channel region 121 is increased, thereby reducing the volatility of the drain 127b current of the thin-film transistor TFT as the driving voltage (gate voltage) changes, improving the uniformity of the drain 127b current of the thin-film transistor TFT at different positions, thereby improving the uniformity of the display brightness and improving the user experience.

[0043] It should be noted that the structure of the array substrate is not limited to the above embodiments and the illustrated structures. For example, the active layer 120 also includes a region where the source electrode 127a or the drain electrode 127b contacts the active layer 120 through a via hole. The arrangement of the thin film transistors TFT in the array substrate is also not limited to Figure 1 In the structure shown, a plurality of thin film transistors TFT and other structures such as capacitors form a pixel driving circuit, for example, forming a plurality of forms such as 2T1C (i.e., two thin film transistors TFT and one capacitor (C)), 3T1C or 7T1C, Figure 1 The thin film transistors TFT in a plurality of pixel driving circuits are shown. The specific structure of the array substrate can be designed based on the above embodiments according to actual requirements, and will not be described in detail here.

[0044] Based on the above embodiments, the embodiments of the present disclosure introduce the specific structure of the concave-convex structure 131 on the adjustment layer 130 , and the specific contents are as follows.

[0045] In the array substrate provided by at least one embodiment of the present disclosure, the adjustment layer 130 is provided with a plurality of grooves 132 , and the concavo-convex structure 131 includes a plurality of grooves 132 .

[0046] For example, Figure 2 As shown, a plurality of grooves 132 are provided on the adjustment layer 130, and the plurality of grooves 132 form a plurality of concave-convex structures 131 on the adjustment layer 130. The orthographic projection of at least one groove 132, for example, two grooves 132, on the substrate 110 falls within the orthographic projection of the channel region 121 on the substrate 110, and the orthographic projection of the remaining grooves 132 on the active layer 120 falls on the source region 122 or the drain region 123. In this way, by providing a plurality of grooves 132 on the adjustment layer 130, the film surface of the channel region 121 corresponding to the grooves 132 has a height difference, and defects are introduced in the channel region 121, thereby reducing the influence on the thickness of the array substrate in the direction perpendicular to the substrate 110, and improving the Mura phenomenon.

[0047] It should be noted that the structure of the groove 132 in the specific adjustment layer 130 of the array substrate is not limited to the above embodiments. For example, the concave-convex structure 131 of the adjustment layer 130 includes a plurality of protrusions, and the orthographic projection of at least one protrusion on the active layer 120 falls on the channel region 121, or the concave-convex structure 131 of the adjustment layer 130 includes a plurality of protrusions and a plurality of grooves 132, and the orthographic projection of at least one groove 132 and / or at least one protrusion on the active layer 120 falls on the channel region 121. For example, in the case where a plurality of grooves 132 and a plurality of protrusions are provided on the adjustment layer 130, the plurality of grooves 132 and the plurality of protrusions can be arranged at intervals, or can be arranged in other ways. All of the above can be designed according to actual needs, and will not be described in detail here.

[0048] In the case where the concavo-convex structure 131 on the adjustment layer 130 includes a plurality of grooves 132 , the embodiment of the present disclosure further defines the depth of the grooves 132 on the adjustment layer 130 in a direction perpendicular to the substrate 110 .

[0049] In the array substrate provided by at least one embodiment of the present disclosure, at least one groove 132 is located on a surface of the adjustment layer 130 facing away from the substrate 110 , and / or at least one groove 132 penetrates the adjustment layer 130 .

[0050] For example, Figure 2 As shown, in a thin film transistor TFT, a plurality of grooves 132 are arranged on the adjustment layer 130, and there are two grooves 132 corresponding to the channel region 121 of the thin film transistor TFT, namely a first groove 132a and a second groove 132b, and the first groove 132a and the second groove 132b are located on the surface of the adjustment layer 130 away from the substrate 110.

[0051] For example, Figure 3 As shown, in a thin film transistor TFT, in the first groove 132 a and the second groove 132 b corresponding to the channel region 121 of the thin film transistor TFT, the first groove 132 a and the second groove 132 b penetrate the adjustment layer 130 .

[0052] For example, Figure 4 As shown, in a thin film transistor TFT, in the first groove 132a and the second groove 132b corresponding to the channel region 121 of the thin film transistor TFT, the first groove 132a is located on the surface of the adjustment layer 130 away from the substrate 110, and the second groove 132b penetrates the adjustment layer 130.

[0053] In the embodiments of the present disclosure, by adjusting the depth of the groove 132 in the layer 130 corresponding to the channel region 121 in the thin film transistor TFT in the direction perpendicular to the substrate 110, the degree of change in the characteristics of the thin film transistor TFT can be controlled, so as to modify the thin film transistor TFT at different positions. In this way, by adjusting at least one of the parameters of the groove 132 corresponding to the channel region 121 in the thin film transistor TFT at different positions, such as depth, size, density, etc., the problem of display brightness difference caused by parameter differences in the manufacturing process of different thin film transistors TFT can be improved, and even the problem of display brightness difference caused by signal attenuation can be improved by making the parameters of the groove 132 corresponding to the channel region 121 of the thin film transistor TFT at different positions different. All of the above can be designed according to actual process requirements and will not be described in detail here.

[0054] In addition to describing the depth of the groove 132 in the direction perpendicular to the substrate 110 , the embodiment of the present disclosure further describes the horizontal distribution of the groove 132 on the adjustment layer 130 .

[0055] In the array substrate provided by one embodiment of the present disclosure, the orthographic projection of the groove 132 on the substrate 110 is linear, and the grooves 132 are spaced apart from each other. In the array substrate provided by at least one embodiment of the present disclosure, the orthographic projections of the source region 122 and the drain region 123 on the substrate 110 are linear, respectively, and the angle between the orthographic projection of the groove 132 on the substrate 110 and the orthographic projection of the source region 122 on the substrate 110 is an acute angle or a right angle.

[0056] For example, Figure 5 As shown, the plurality of grooves 132 on the adjustment layer 130 are linear grooves 132, and the orthographic projections of the plurality of linear grooves 132 on the substrate 110 are linear figures such as rectangles, and the linear figures are perpendicular to the orthographic projections of the source region 122 or the drain region 123 on the substrate 110. In a direction parallel to the orthographic projection of the active region on the substrate 110, the plurality of linear grooves 132 are arranged at intervals.

[0057] For example, Figure 6 As shown, the plurality of grooves 132 on the adjustment layer 130 are linear grooves 132, and the angle between the orthographic projection of the linear groove 132 on the substrate 110 and the orthographic projection of the source region 122 on the substrate 110 is an acute angle, and the plurality of grooves 132 are arranged obliquely relative to the horizontal plane of the substrate 110. In this way, the characteristics of the thin film transistor TFT can be uniformly changed, thereby effectively improving the problem of uneven display brightness.

[0058] It should be noted that, in the array substrate in the embodiment of the present disclosure, the linear figure of the orthographic projection of the linear groove 132 on the substrate 110 is not limited to a rectangle, and can also be other shapes such as a hexagon or octagon with non-right angles. In addition, the embodiment of the present disclosure does not limit the specific angle between the orthographic projection of the linear groove 132 on the substrate 110 and the orthographic projection of the source region 122 on the substrate 110, which can be greater than 0° and less than 90°, and does not limit the spacing between the grooves 132 arranged at intervals, the specific size of the grooves 132, etc. All of the above can be designed according to actual process requirements and will not be elaborated here.

[0059] Different from the above-mentioned embodiment, the groove 132 is a linear groove 132 design scheme. In another embodiment of the array substrate provided by the present disclosure, the plurality of grooves 132 include a plurality of first-type grooves 135 and a plurality of second-type grooves 136, and the plurality of first-type grooves 135 and the second-type grooves 136 intersect with each other to form a grid-like structure. In the array substrate provided by at least one embodiment of the present disclosure, the orthographic projections of the source region 122 and the drain region 123 on the substrate 110 are respectively in the shape of straight lines, and the angle between the orthographic projection of the first-type groove 135 on the substrate 110 and the orthographic projection of the source region 122 on the substrate 110 is a right angle. In the array substrate provided by at least one embodiment of the present disclosure, the angle between the orthographic projection of the second-type groove 136 on the substrate 110 and the orthographic projection of the source region 122 on the substrate 110 is a right angle.

[0060] For example, Figure 7 As shown, the orthographic projections of the source region 122 and the drain region 123 in the active layer 120 on the substrate 110 are respectively in the shape of a straight line. The orthographic projections of the plurality of grooves 132 on the substrate 110 are respectively in the shape of a straight line, and according to the extending direction of the grooves 132, the grooves 132 can be divided into first-type grooves 135 extending in a direction parallel to the orthographic projection direction of the straight line of the source region 122 on the substrate 110, and second-type grooves 136 extending in a direction perpendicular to the orthographic projection direction of the straight line of the source region 122 on the substrate 110. The first-type grooves 135 and the second-type grooves 136 intersect with each other to form a grid-like structure.

[0061] For example, Figure 8 As shown, based on the above exemplary embodiment, in the array substrate in this example, the first type of groove 135 is not parallel to the straight line orthographic projection of the source region 122 on the substrate 110, and the angle between the first type of groove 135 and the straight line orthographic projection of the source region 122 is an acute angle. The second type of groove 136 is not perpendicular to the straight line orthographic projection of the source region 122 on the substrate 110, and the angle between the second type of groove 136 and the straight line orthographic projection of the source region 122 is an obtuse angle.

[0062] It should be noted that, in the array substrate in the above example, the angle between the first type of groove 135 and the straight line projection of the source region 122 can be an obtuse angle, and the angle between the second type of groove 136 and the straight line projection of the source region 122 can be an acute angle, and the embodiment of the present disclosure does not limit the specific angles of the angle between the first type of groove 135 and the straight line projection of the source region 122 and the angle between the second type of groove 136 and the straight line projection of the source region 122, and can be designed according to actual needs.

[0063] The present disclosure does not limit the shape of the cross section of the groove 132 in the array substrate in the direction perpendicular to the substrate 110. It is not limited to the rectangle shown in the figure, and can also be set to a rectangular, trapezoidal and other structures. It can be designed according to actual needs and will not be elaborated here.

[0064] In an array substrate provided in an embodiment of the present disclosure, Fig.10 As shown, the orthographic projection of the channel region 121 on the substrate 110 is in a straight line shape. In this way, the processing difficulty of the channel region 121 is reduced, and the production cost is saved.

[0065] In another embodiment of the present disclosure, at least part of the orthographic projection of the channel region 121 on the substrate 110 is curved. In at least one embodiment of the present disclosure, the orthographic projection of the channel region 121 on the substrate 110 is an arc curve, a wavy curve or an X-shape.

[0066] For example, Figure 5-Figure 9 As shown, the positive projection of the channel region 121 on the substrate 110 is an arc curve. In this way, the channel region 121 is set to an arc shape, which can increase the width of the channel region 121 without increasing the size of the corresponding thin film transistor TFT. The width of the channel region 121 is increased, so that the probability of carriers in the thin film transistor TFT being captured by the interface state during the migration process becomes smaller, thereby causing the threshold voltage to become smaller, and the saturation mobility of the thin film transistor TFT decreases with the increase of the channel width, ultimately improving the driving ability of the thin film transistor TFT and reducing the risk of delay. However, the shape of the channel region 121 is not limited to an arc curve, but can also be a wavy curve or a cross shape or other curves such as a meandering curve.

[0067] Taking into account that due to the photoconductivity effect, the electrical performance of the thin film transistor TFT in the array substrate is offset under light conditions. For example, the active area is exposed to backlight to generate leakage current, which affects the performance of the array substrate. The embodiment of the present disclosure also further designs the adjustment layer 130. The specific solution is as follows.

[0068] In an array substrate provided in an embodiment of the present disclosure, Fig.10As shown, the adjustment layer 130 is a light shielding layer, and the orthographic projection of the light shielding layer on the substrate 110 covers the orthographic projection of the thin film transistor TFT on the substrate 110, that is, the light shielding layer covers the active layer 120 of the thin film transistor TFT. The light shielding layer is made of a non-conductive material, and the non-conductive material is a material that can block light, including but not limited to a black color resist material. In this way, the light shielding layer can effectively block light and effectively reduce the influence of light on the active layer 120 (semiconductor material) of the thin film transistor TFT in the array substrate, thereby avoiding the influence of light on the electrical performance of the thin film transistor TFT.

[0069] In another embodiment of the present disclosure, in an array substrate provided, Fig.10 As shown, the adjustment layer 130 is a conductive layer, and the conductive layer includes a plurality of spaced shading portions 137 and at least one circuit structure portion. The orthographic projection of the shading portion 137 on the substrate 110 covers the orthographic projection of the thin film transistor TFT on the substrate 110, and the circuit structure portion is insulated from the shading portion 137. The adjustment layer 130 is made of a conductive material that can block light, and the material of the adjustment layer 130 includes but is not limited to metal materials such as MO, Al, Ti, A-Si, CU and the like. When the adjustment layer 130 is made of a metal material, the adjustment layer 130 can also be referred to as a BSM (bottom shield metal, bottom shielding metal) layer. In this way, by setting the adjustment layer 130 as a conductive layer, while reducing the influence of light on the characteristics of the thin film transistor TFT, it can also be set as other functional film layers, thereby optimizing the structure of the array substrate.

[0070] In addition, the embodiments of the present disclosure do not limit other structures of the array substrate. For example, an inorganic layer, such as a film layer formed by an amorphous silicon material, may be provided between the adjustment layer and the active layer of the thin film transistor. The inorganic layer serves as an insulator, and the thickness and material of the inorganic layer can be designed according to actual needs and will not be elaborated here.

[0071] In the array substrate provided in at least one embodiment, the circuit structure portion includes a static electricity lead-out line 138. At this time, the adjustment layer 130 can function as both a light shielding layer and a static electricity shielding layer.

[0072] It should be noted that the present disclosure does not limit how the adjustment layer 130 achieves the electrostatic shielding effect, and there may be multiple implementations. For example, the thin film transistor TFT in the array substrate includes a plurality of first switch transistors and a plurality of second switch transistors. The first switch transistor is connected to the driver chip via a signal line. The plurality of second switch transistors are connected to the electrostatic shielding layer (adjusting layer 130) via an electrostatic lead-out line 138, and the driver chip controls the first switch transistor to turn off and controls the second switch transistor to turn on to control the shielding layer to switch to an electrostatic shielding state.

[0073] Considering that impurities in the substrate 110 may diffuse into the active layer 120 through the grooves 132 in the adjustment layer 130 and affect the characteristics of the thin film transistor TFT, the embodiment of the present disclosure further provides a buffer layer 140, and the specific solution is as follows.

[0074] In at least one embodiment of the array substrate provided, Fig.10 As shown, the array substrate further includes a buffer layer 140 located between the adjustment layer 130 and the active layer 120. The buffer layer 140 may be a single layer of silicon oxide, silicon nitride, or a stack of the two. Thus, the buffer layer 140 blocks the impurities contained in the substrate 110 from diffusing into the active layer 120, thereby preventing the threshold voltage and leakage current of the thin film transistor TFT from being affected, thereby improving the reliability of the array substrate.

[0075] An embodiment of the present disclosure provides a display panel, which includes the array substrate of any one of the above embodiments.

[0076] In at least one embodiment, Fig.11 As shown, the display panel includes an array substrate, a flat layer 150, a display layer 160 and an encapsulation layer 170. The structure of the array substrate can refer to the above embodiment and will not be described here. The flat layer 150 is located on the side of the source and drain electrode layer 127 away from the substrate 110, and the display layer 160 is provided on the side of the flat layer 150 away from the substrate 110. The display layer 160 includes a pixel defining layer 161 located on one side of the flat layer 150 substrate 110, and the pixel defining layer 161 defines a pixel opening corresponding to the light-emitting unit, and each pixel opening is correspondingly formed with a first electrode 162, a light-emitting functional layer 163 and a second electrode 164 stacked in sequence.

[0077] Exemplarily, one of the first electrode 162 and the second electrode 164 is an anode, and the other is a cathode. For example, the first electrode 162 is an anode, and the second electrode 164 is a cathode.

[0078] For example, the encapsulation layer 170 includes a first encapsulation layer 171, a second encapsulation layer 172, and a third encapsulation layer 173 stacked in sequence on the side of the display layer 160 facing away from the substrate 110, the first encapsulation layer 171 covers the surface of the display layer 160 facing away from the substrate 110, the second encapsulation layer 172 covers the surface of the first encapsulation layer 171 facing away from the substrate 110, and the third encapsulation layer 173 covers the surface of the second encapsulation layer 172 facing away from the substrate 110. The first encapsulation layer 171 and the third encapsulation layer 173 are inorganic encapsulation layers 170, and the second encapsulation layer 172 is an organic encapsulation layer 170. The specific structure of the encapsulation layer 170 can refer to the encapsulation method in the current display panel, which will not be repeated here.

[0079] It should be noted that the light-emitting functional layer 163 in the above-mentioned display panel may include a light-emitting functional layer 163 and a carrier layer, and the carrier layer is located between the first electrode 162 and the light-emitting functional layer 163, and / or between the light-emitting functional layer 163 and the second electrode 164. The carrier layer may be a light-transmitting layer. The carrier layer refers to a carrier-related film layer used to realize the functions of injection, transmission, and blocking of carriers (holes or electrons). In some embodiments, the carrier layer between the first electrode 162 and the light-emitting functional layer 163 may include at least one of a hole injection layer (Hole Inject Layer, HIL), a hole transport layer (Hole Transport Layer, HTL), and an electron blocking layer (Electron Blocking Layer, EBL). In some embodiments, the carrier layer between the light-emitting functional layer 163 and the second electrode 164 may include at least one of an electron injection layer (Electron Inject Layer, EIL), an electron transport layer (Electron Transport Layer, ETL), and a hole blocking layer (Hole Blocking Layer, HBL).

[0080] The structure of the display panel in the present disclosure is not limited to the above embodiments and the examples in the figures. For example, the structure of the thin film transistor in the display panel is not limited to the above embodiments. For example, the display panel can also be set to other structures such as a touch structure, a fingerprint structure, etc. The above can be designed according to the needs and will not be repeated here.

[0081] In the embodiment of the present disclosure, the display panel may be the above-mentioned Fig.11 The organic light emitting diode display panel mentioned in the relevant embodiments may also be a liquid crystal display panel, an electronic paper display panel, etc. including the array substrate mentioned in the above embodiments.

[0082] For example, the display panel in the embodiments of the present disclosure may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, or the like.

[0083] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. An array substrate, characterized in that: include: substrate; A thin film transistor, located on the substrate and comprising an active layer, wherein the active layer comprises a channel region; as well as The adjustment layer is located between the substrate and the active layer, and has a plurality of concave-convex structures, and an orthographic projection of at least one of the concave-convex structures on the substrate falls within an orthographic projection of the channel region on the substrate.

2. The array substrate according to claim 1, characterized in that: The adjustment layer is provided with a plurality of grooves, and the concavo-convex structure includes the grooves.

3. The array substrate according to claim 2, characterized in that: At least one of the grooves is located on a surface of the regulating layer facing away from the substrate; or, At least one of the grooves penetrates the adjustment layer.

4. The array substrate according to claim 2, characterized in that: The orthographic projection of the grooves on the substrate is linear, and the grooves are spaced apart from each other; Preferably, the active layer also includes a source region and a drain region, the channel region is located between the source region and the drain region, the orthographic projections of the source region and the drain region on the substrate are respectively straight lines, and the angle between the orthographic projection of the groove on the substrate and the orthographic projection of the source region on the substrate is an acute angle or a right angle.

5. The array substrate according to claim 2, characterized in that: The plurality of grooves include a plurality of first-type grooves and a plurality of second-type grooves, and the plurality of first-type grooves and the plurality of second-type grooves intersect each other to form a grid-like structure; Preferably, the active layer further comprises a source region and a drain region, the channel region is located between the source region and the drain region, the orthographic projections of the source region and the drain region on the substrate are respectively in the shape of straight lines, and the angle between the orthographic projection of the first type of groove on the substrate and the orthographic projection of the source region on the substrate is a right angle; Preferably, the angle between the orthographic projection of the second-type groove on the substrate and the orthographic projection of the source region on the substrate is a right angle.

6. The array substrate according to any one of claims 1 to 5, characterized in that: The orthographic projection of the channel region on the substrate is in the shape of a straight line; or At least part of the orthographic projection of the channel region on the substrate is curved, Preferably, the orthographic projection of the channel region on the substrate is an arc curve, a wavy curve, or an X-shape.

7. The array substrate according to claim 1, characterized in that: The regulating layer is a light shielding layer, and the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the thin film transistor on the substrate.

8. The array substrate according to claim 1, characterized in that: The adjustment layer is a conductive layer, the conductive layer includes a plurality of light shielding portions arranged at intervals and at least one circuit structure portion, the orthographic projection of the light shielding portion on the substrate covers the orthographic projection of the thin film transistor on the substrate, and the circuit structure portion is insulated from the light shielding portion; Preferably, the circuit structure includes an electrostatic lead-out line.

9. The array substrate according to claim 1, characterized in that: The thin film transistor comprises: A gate layer, located on the substrate, the gate layer includes at least one gate electrode, and the orthographic projection of the channel region on the substrate is located within the orthographic projection of the gate electrode on the substrate; a gate insulating layer, located between the gate layer and the active layer; and A source-drain electrode layer is connected to the active layer, wherein the active layer includes a source region and a drain region, the channel region is located between the source region and the drain region, the source-drain electrode layer includes a source and a drain, the source is connected to the source region, and the drain is connected to the drain region.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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