Solder material, layer structure and forming method thereof, chip package and forming method thereof, chip arrangement and forming method thereof

Abstract

Solder materials, layer structures and methods of forming the same, chip packages and methods of forming the same, chip arrangements and methods of forming the same. A solder material is provided. The solder material may include nickel and tin, where the nickel may include a first amount of particles and a second amount of particles, where the sum of the first amount of particles and the second amount of particles is the total amount of nickel or less, where the first amount of particles is between 5 at% and 60 at% of the total amount of nickel, where the second amount of particles is between 10 at% and 95 at% of the total amount of nickel, and where the sum of the first amount of particles and the second amount of particles is between 10 at% and 95 at% of the total amount of nickel. Wherein the particles of the first amount of particles have a first size distribution, and wherein the particles of the second amount of particles have a second size distribution, and wherein 30% to 70% of the particles of the first amount have a particle size in the range of about 5 [mu] m about the particle size of the highest number of particles according to the first size distribution, and wherein 30% to 70% of the second amount of particles have a particle size in the range of about 5 [mu] m about the particle size of which the highest number of particles have according to the second size distribution.

Description

Technical Field

[0001] Various embodiments generally relate to a solder material, to a layer structure, to a chip package, to a method of forming a layer structure, to a method of forming a chip package, to a chip arrangement and to a method of forming a chip arrangement. Background Art

[0002] For power applications, die and clips are soldered today with high lead (Pb) based soft solder pastes. However, as the EU-wide ban on lead is ongoing (e.g., see RoHS, ELV regulations), it may be necessary to develop alternative die and clip attachment systems to be at least as good as high lead content based solder paste systems.

[0003] Furthermore, currently, so-called second-level mounting, which may refer to the mounting of (e.g. power) chips onto printed circuit boards (PCBs), is accomplished using eutectic PbSn solders having a melting temperature of about 180° C. or SAC solders having a melting temperature of about 220° C. These solders have several disadvantages that may limit the resulting reliability of the overall system: board-level interconnects formed by the solders may remelt during application at a given melting temperature, and / or may be susceptible to fatigue, especially at elevated temperatures, due to the relatively soft material, and eutectic PbSn solders are not lead-free.

[0004] Currently, there are no general alternatives available for solders with high lead content. Potential alternative technology solutions are only designed to address a single application. They are not suitable for general purpose use.

[0005] For example, AuSn may not typically be used as a replacement for Pb solder due to significantly higher cost and tighter design rules / geometry restrictions.

[0006] Thin dies can be a challenge for several potential solutions, especially those without melting material. Other potential alternatives may have too low a melting point, which may be a problem during second level soldering (for which a minimum melting temperature of 270°C may be required).

[0007] Adhesives with fillers with high silver content as potential technical solutions may exhibit worse thermal and electrical properties than solders with high lead content.

[0008] Other high-performance technology options may not be cost-competitive. Summary of the invention

[0009] A solder material is provided. The solder material may include nickel and tin, wherein the nickel may include a first amount of particles and a second amount of particles, wherein the sum of the first amount of particles and the second amount of particles is the total amount of nickel or less, wherein the first amount of particles is between 5 at% and 60 at% of the total amount of nickel, wherein the second amount of particles is between 10 at% and 95 at% of the total amount of nickel, wherein particles of the first amount of particles have a first size distribution, wherein particles of the second amount of particles have a second size distribution, wherein 30% to 70% of the first amount of particles have a particle size in the range of about 5 μm around the particle size of the highest number of particles according to the first size distribution, and wherein 30% to 70% of the second amount of particles have a particle size in the range of about 5 μm around the particle size of the highest number of particles according to the second size distribution. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention.

[0011] In the following description, various embodiments of the present invention are described with reference to the following drawings, in which:

[0012] Figures 1A to 1C Each of shows a diagram of solder material according to various embodiments, and Figure 1D The sequence as schematic diagrams shows how solder material transforms during the soldering process according to various embodiments;

[0013] Figures 2A to 2J Each of which shows a schematic cross-sectional view of a layer structure according to various embodiments;

[0014] Figure 3A and Figure 3B Each of which shows a schematic cross-sectional view of a layer structure according to various embodiments;

[0015] Figure 4A and Figure 4B Each of them shows a schematic cross-sectional view of a chip package according to various embodiments;

[0016] Figure 5A and Figure 5B each showing a particle distribution of a first amount of particles and a second amount of particles in a solder material according to various embodiments;

[0017] Figure 6 A flow chart showing a method of forming a layer structure according to various embodiments; and

[0018] Figure 7 A flow chart showing a method of forming a chip package according to various embodiments is shown;

[0019] Figure 8 A flow chart showing a method of forming a chip arrangement;

[0020] Fig. 9 showing a microscope image of a surface of a vertically cut layer structure according to various embodiments; and

[0021] Fig. 10A and 10B Each of the Figures shows a schematic cross-sectional view of a chip arrangement according to various embodiments. DETAILED DESCRIPTION

[0022] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0023] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0024] The word "over" used in relation to a deposited material formed "over" a side or surface may be used herein to mean that the deposited material may be formed "directly on" an implied side or surface, such as in direct contact with the implied side or surface. The word "over" used in relation to a deposited material formed "over" a side or surface may be used herein to mean that the deposited material may be formed "indirectly on" an implied side or surface, with one or more additional layers disposed between the implied side or surface and the deposited material.

[0025] Various aspects of the present disclosure are provided for devices, and various aspects of the present disclosure are provided for methods. It should be understood that the basic properties of the devices also apply to the methods, and vice versa. Therefore, for the sake of brevity, repeated descriptions of such properties may have been omitted.

[0026] In various embodiments, a solder material is provided that can be used as a drop-in replacement for solder paste systems having high lead content (also referred to as "high-lead solder").

[0027] In various embodiments, the solder material may include or consist of tin and nickel. The high nickel content of a solder material such as solder paste may be achieved by a bimodal distribution of nickel particles. The bimodal distribution may include a first amount of nickel particles having a relatively small size, such as in a range from about 0.5 μm to about 20 μm, such as from about 1 μm to about 20 μm, and a second amount of nickel particles having a larger size, such as in a range from about 30 μm to about 50 μm. In other words, the first amount of particles may have a size within a first size distribution, and the second amount of particles may have a size within a second size distribution. Particles having a relatively small size may also be referred to as small size particles or as small particles, and particles having a relatively large size may also be referred to as large particles, large size particles, or large particles.

[0028] In various embodiments, 30% to 70% (optionally 40% to 60%) of the first amount of particles may have a particle size in the range of about 5 μm around the particle size of the highest number of particles according to the first size distribution. In other words, the majority or at least the majority of the small particles may have the most common size or a size close to the most common size, for example, about ±2,5 μm around the most common size.

[0029] In various embodiments, 30% to 70% (optionally 40% to 60%) of the second amount of particles may have a particle size in the range of about 5 μm around the particle size of the highest number of particles according to the second size distribution. In other words, the majority or at least the majority of large particles may have a size that is the most common (most frequent) size or a size close to the most common size, for example, about ± 2,5 μm around the most common size.

[0030] In various embodiments, the first size distribution and the second size distribution may have substantially no overlap.

[0031] During soldering, the small particles may be completely alloyed with the tin-rich solder-based material surrounding them, such as tin-based soft solder, without directly transforming into a high melting point intermetallic phase (IMC). Tin-rich materials, such as tin-rich solder-based materials, may be understood to be composed primarily of tin, in other words, more than 50% of the weight of the solder may be formed of tin. The tin-rich material may be free of lead.

[0032] Tin-rich materials, some of which are commonly used in the semiconductor industry, may, for example, include or consist of so-called SAC solders comprising 3-4% Ag, 0,5-0,7% Cu and the remainder may be Sn (all percentages in this paragraph may be weight percentages), SnSb solders comprising 5-25% Sb, SnAg solders comprising 0,5-10% Ag, SnCu solders comprising 0,3-5% Cu, in some cases with Ni doping, and the special cases of In-Sn (In52-Sn48) solders and Bi-Sn (Bi58-Sn42), where Sn forms a minority component but which may also be considered to be tin-rich in the present context.

[0033] In various embodiments, In96,5-Ag3,5 or In66-Bi34 solder may be used instead of the tin-rich material.

[0034] In various embodiments, in addition to the Ni—Sn phase, additional phases may be formed according to a lever rule depending on alloying elements in the tin-rich solder material.

[0035] Only after further reaction with nickel from larger particles and nickel-plated interfaces can the bulk of the interconnect material be converted to high-melting-point IMC.

[0036] The main component (>80at%) of the layer formed by the solder material after hardening may be a Ni3Sn4 intermetallic compound phase (which may be stable up to 800°C), or a Ni3Sn2 phase (which may be stable up to 1200°C), or a mixture of both phases, depending on the specific process flow. If the chip metallization 220B, 220F contains silver, a small portion of the Ag3Sn-phase may very likely appear close to the interface with the chip metallization 220B, 220F. However, this may be insignificant, since it may be high temperature stable up to 480°C. A phase consisting of silver and nickel may not be present. Experience with Ni / Sn diffusion solders shows that ternary phases may be negligible.

[0037] In other words, the bimodal distribution of nickel particles in the solder material can allow small nickel particles to melt first during the soldering process and allow for uniform distribution within the liquefied solder material and contact with the metal (e.g., nickel) surface to be joined, and allow for a high nickel content in the liquefied solder material that may be required for forming an intermetallic compound phase (and thereby hardening of the solder material) to be reached only after a portion of the nickel included in the large nickel particles has melted.

[0038] In various embodiments, the solder material and the connection formed using the solder material can meet the requirements of the above requests, such as regarding versatility, constants, etc. In particular, the melting temperature of the resulting interconnect can be higher than 270° C., so that the interconnect may be able to withstand second-level soldering. For second-level soldering, solder materials according to various embodiments can be used.

[0039] In various embodiments, the solder material may be used for mounting the die, for example for mounting the die to a conductive substrate, for example to a lead frame.

[0040] In various embodiments, solder material may be used to attach the conductive structure to the die, for example to attach a clip to the die.

[0041] In various embodiments, the solder material may be used to attach the chip package to a printed circuit board (PCB) or the like.

[0042] In various embodiments, the layer structure may be formed by mounting the chip or chip package to the metal layer using a solder material. The metal layer may have a top layer comprising or consisting of tin (optionally with a thin (e.g., a few nanometers thick) protective layer). Similarly, the chip contact surface may have a top layer comprising or consisting of tin (optionally with a thin (e.g., a few nanometers thick) protective layer).

[0043] As another way of expressing it, in a layer structure, a chip or a chip package can be mounted to a conductive substrate (which can have a tin layer containing nickel as one of the connection partners) using a solder material according to various embodiments and / or can be connected to a conductive structure (which can have a tin layer containing nickel as one of the connection partners).

[0044] In various embodiments, dedicated metallization may be provided on the chip contact surface to be soldered and / or on the conductive substrate and / or the conductive structure, respectively. The chip contact surface may, for example, comprise or consist of one or more layers on the front and / or back side of the die. The metallization on the conductive substrate may, for example, be one or more layers on a lead frame or the like. The metallization on the conductive structure may, for example, be one or more layers on a clip, a spacer, a substrate for direct copper bonding or the like.

[0045] In various embodiments, one or more layers in combination with a nickel (Ni) and tin (Sn) based paste with a high nickel content (e.g., between 35 at% and 90 at%) may be used to form the interconnect. This may allow a melting temperature Tmelt>270° C. to be reached. More specifically, a composition with a nickel content of 35 at% to 50 at% may be preferred.

[0046] Dedicated metallization (e.g., plating) can be configured in various embodiments to avoid strong intermetallic compound growth and Kirkendall voids between the metals of the conductive substrate or conductive structure, respectively, which can, for example, include or consist of copper (Cu) as one of the connection partners and tin (Sn) as the other of the connection partners. The plating can include a nickel layer, which can act as a diffusion barrier (resisting mixing of copper and tin) and as an alloying element.

[0047] In various embodiments, the composition of the metal layer forming part of the interconnect and the solder material may be configured in such a way that, after the soldering process, no pure tin may be left in the fillet area. Configurations that may be suitable for achieving this may include including the above-mentioned amounts of nickel and / or tin in the solder material, in particular the amounts of nickel provided as small particles and large particles, respectively.

[0048] In various embodiments, by forming the interconnect using solder material as described above, the interconnect layer as a whole can be close to thermodynamic equilibrium. Therefore, further alloying during subsequent thermal treatment (e.g., during reliability testing or in application) can be reduced, and mechanical stability can be increased. This can lead to greater flexibility with respect to overall design, since the thickness of plating and chip metallization, such as chip contact surfaces, contact surfaces of PCBs, etc., can be reduced.

[0049] The solder material according to various embodiments has been shown to work on bare Cu and NiP. Furthermore, according to various embodiments using the solder material, any other typical PCB-, chip- and / or leadframe metallization may be used to form the layer structure.

[0050] By nickel plating all surfaces in contact with the solder material, Kirkendall voids at the Sn-Cu reaction front can be avoided. In addition, volume shrinkage due to ongoing phase formation can be avoided. Therefore, the reliability of the solder joint can be increased.

[0051] In various embodiments, the proposed lead-free system may include a conductive Cu-based element (possibly including some doping) having a thickness from about 100 μm to about 5 mm. The conductive element may be partially or completely plated with a nickel layer having a thickness in the range from about 100 nm to about 5 μm. The lead-free system may further include a NiSn-based soft solder. The nickel portion of the solder may be in the range from about 35 at % to about 90 at %. In addition to tin, additional materials may be part of the solder, such as silver (Ag), gold (Au), platinum (Pt) and / or palladium (Pd).

[0052] Using the solder material according to various embodiments for attaching a chip to a substrate, an increased stability of the so-called die attach may be achieved due to the high temperature intermetallic phase.

[0053] In various embodiments, the solder material may be used for a so-called second level mounting process, e.g. for attaching the chip package to a conductive substrate (or, respectively, to a substrate having a conductive portion, e.g., at least one contact pad), e.g., to a printed circuit board (PCB). Due to the high temperature intermetallic phase, an increased stability of the interconnection between the chip package and the conductive substrate may be achieved.

[0054] Figures 1A to 1C Each of which shows a diagram of a solder material 100 according to various embodiments, Figure 1D shows as a schematic sequence how the solder material 100 according to various embodiments is transformed during the soldering process, resulting in a layer 101 which is then generally referred to as the second layer 101, Fig. 9 shows a microscope image of a surface of a vertically cut layer structure 200 according to various embodiments, which reveals structural details of the (second) layer 101, and Figure 5A and Figure 5B Each of shows a particle distribution of a first amount of particles and a second amount of particles in a solder material according to various embodiments.

[0055] The solder material 100 may include nickel and tin.

[0056] The nickel may include, for example, be provided as, a first amount of particles 104_1 and a second amount of particles 104_2 . The first amount of particles 104_1 and the second amount of particles 104_2 may be distributed in the solder-based material 102 .

[0057] The sum of the first amount of particles 104_1 and the second amount of particles 104_2 can be the total amount of nickel or less, wherein the first amount of particles 104_1 can be between 5at% and 60at% of the total amount of nickel, for example between 25at% and 60at%, and wherein the second amount of particles 104_2 can be between 10at% and 95at% of the total amount of nickel, for example between 10at% and 75at%.

[0058] The particles of the first amount of particles 104_1 may have a size in the range from about 1 μm to about 20 μm, for example between about 3 μm and 7 μm or between about 5 μm and 15 μm. The particles of the second amount of particles 104_2 may have a size in the range from about 30 μm to about 50 μm, for example between about 35 μm and about 40 μm.

[0059] The lower limit of the size of the first amount of particles 104_1 may be set to about 1 μm. Thus, it can be ensured that the first amount of particles 104_1 may not be affected by restrictive regulations regarding nanoparticles. In addition, a size of 1 μm or more may mean that the oxidative effect of small particles may be limited to a tolerable level.

[0060] The lower limit of the size of the second amount of particles 104_2 can be set to about 30 μm. This can ensure that, depending on what is desired, the core of the large nickel particles 104_2 can remain as a core of pure nickel after welding, or the second amount of particles 104_2 has a size that is also dissolved. The maximum size of the second amount of particles 104_1 can be determined by the thickness of the bonding wire to be arranged between the two metal surfaces to be connected by the solder material 100, where the bonding wire can set the separation between the two metal surfaces. The maximum size of each of the second amount of particles 104_2 can be less than about half the thickness of a normal bonding wire (the thickness of a normal bonding wire can be about 80 μm to 100 μm, so that the maximum size of the second amount of particles 104_2 can be between about 40 μm and about 50 μm).

[0061] Figure 5A and Figure 5B Each of them shows a particle distribution of a combination of a first amount of particles 104_1 and a second amount of particles 104_2 in the solder material 100 according to various embodiments.

[0062] In various embodiments, all nickel in the solder material 100 may be contributed by a first amount of particles 104_1 and by a second amount of particles 104_2 . Figure 5A Such an embodiment is shown in . The absolute or relative amounts at% contributed by the first amount of particles 104_1 and by the second amount of particles 104_2, respectively, may be difficult to estimate from this qualitative visualization because the volume (and therefore the number of atoms) of each of the larger particles 104_2 is much larger than the volume (and therefore the number of atoms) of each of the smaller particles 104_1.

[0063] In various embodiments, only a portion of the nickel in the solder material 100 may be contributed by the first amount of particles 104_1 and by the second amount of particles 104_2. In various embodiments, the solder material 100 may include additional particles 550 in addition to the first amount of particles 104_1 and the second amount of particles 104_2. Figure 1C and Figure 5B Shown in.

[0064] The first amount of particles 104_1 may have a size between about 5 μm and about 15 μm. The second amount of particles 104_2 may have a size between about 30 μm and about 50 μm. The size distribution of the second amount of particles 104_2 may be part of a larger size distribution ranging from a minimum size of the first amount of particles 104_1 to a maximum size of the second amount of particles 104_2, and in addition to some of the second amount of particles 104_2 and the first amount of particles 104_1, it may include an additional amount of particles 104_E (see Figure 1C ). A broad particle size distribution of large particles 104_2 can be obtained, for example, by precipitation with subsequent sifting or the like.

[0065] In various embodiments, the nickel may further include a third amount of particles 104_3, wherein the sum of the first amount of particles 104_1, the second amount of particles 104_2, and the third amount of particles 104_3 is the total amount of nickel or less. The third amount of particles 104_3 may contribute between 10 at% and 85 at% (e.g., between 10 at% and 65 at%) of the total amount of nickel. The particles of the third amount of particles 104_3 may have a size in the range of more than about 20 μm to less than about 30 μm. Figure 1B A corresponding embodiment is shown in The particles 104_1 , 104_2 , 104_3 in the solder material 100 may thus have a trimodal distribution, which may allow to fine-tune the formation of the intermetallic phase even better.

[0066] In various embodiments, the particles of the third amount of particles may have a third size distribution. 30% to 70% of the third amount of particles may have a particle size in the range of about 5 μm around the particle size of the highest number of particles according to the third size distribution. In other words, the majority or at least the majority of the third amount of particles may have the most common size or a size close to the most common size, for example, about ±2,5 μm around the most common size.

[0067] In various embodiments, the particles can be spherical or substantially spherical, for example, as opposed to a sputtered particle shape. For example, the particles can have an outer surface having only raised portions, i.e., no recessed portions on the surface. Figures 1A to 1C , most of the particles 104_1, 104_2, 104_3 are represented by circles indicating spherical particles. However, two particles indicated by arrows are illustrated as ellipses indicating ellipsoidal particles.

[0068] The size of each of the particles 104_1 , 104_2 , 104_3 may be understood as the average of its size along its longest axis and its size along its shortest axis (which is the same in the case of spherical particles).

[0069] In various embodiments, the amount of nickel in the solder material 100 may be in a range from about 35 at % to about 90 at %. The remainder of the solder material 100, i.e., between about 10 at % and about 65 at % of the solder material 100, may be partially or completely formed of tin. In addition to tin, additional materials may be part of the solder, such as silver (Ag), gold (Au), platinum (Pt) and / or palladium (Pd).

[0070] In various embodiments, the solder material 100 may be configured as a solder paste, for example as a tin-based soft solder, for example as a solder-based material 102 in which a first amount of particles 104_1 and a second amount of particles 104_2 (and optionally, a third amount of particles 104_3 and / or additional particles 104_E) are distributed.

[0071] In various embodiments, the solder material 100 may be configured as a solder wire including tin and nickel particles 104_1, 104_2 (and optionally, a third amount of particles 104_3 and / or additional particles 104_E), or as a different kind of preformed solid solder material, for example, a solder sheet (which may optionally be preformed to suit the intended application). The preformed solder material may, for example, be formed as a compacted solder powder or a solder preform.

[0072] Figure 1D and Fig. 9 The behavior of the solder material 100 during a soldering process for which it is configured is shown and will be further described in the context of having a layer structure 200 according to various embodiments, for example as FIG. 2A to FIG. 2J , Figure 3A or Figure 3B As shown in .

[0073] exist Figure 1D , the top view shows a solder material 100 according to various embodiments before a soldering process. A first amount of particles 104_1 and a second amount of particles 104_2 may be distributed in a solder base material 102. The middle view shows an intermediate stage of the soldering process, wherein small particles, i.e. the first amount of particles 104_1, have dissolved (and are therefore shown as dashed lines and marked as 104_1d), while large particles, i.e. the second amount of particles 104_2, are more or less unchanged. The bottom view shows the resulting (second) layer 101, wherein an outer portion 104_1d of the second amount of particles 104_2 is also dissolved, and the base material 102 forms a transformed base material 102c together with the dissolved first amount of particles 104_1d and the dissolved portion 104_2d of the second amount of particles 104_2.

[0074] The conversion process as well as the composition and properties of the (second) layer 101 and the converted base material 102c are described elsewhere herein, but some features will be referred to in Fig. 9 Briefly described, therein the (second) layer 101 is formed between a silicon chip 220 with a backside metallization 222 , 220B as a first layer 222 and a copper substrate 224 as a third layer 222 .

[0075] The (second) layer 101 may include a high temperature Ni-Sn phase 992 and, in this particular embodiment, a high temperature Cu-Sn-Ni phase 998, since the first layer 222 may be formed from a copper layer (e.g., lead frame) 224. The nickel and tin containing phases 992, 998 may form an interconnect structure having a high melting point. The interconnect structure may, for example, act as a stabilizing skeleton, for example during use of a device including the layer structure 200 and / or during further heating processes, such as during a second level mounting process, and in particular during thermal cycling, which may be less prone to fatigue due to cyclic deformation. The interconnect structure may, for example, have a sponge-like shape.

[0076] In various embodiments, a small portion of the unconverted solder material 100 remains, for example embedded in the skeleton structure. In addition, during the soldering process, voids 996 may have formed in the (second) layer. The nickel and tin containing phases 992, 998, the unconverted solder material 100 and the voids 996 may together form or be part of the converted base material 102c.

[0077] At least a portion of each of the second amount of particles 104_2 embedded in the converted base material 102c may still not be dissolved.

[0078] FIG. 2A to FIG. 2J , Figure 3A and Figure 3B Each of them shows a schematic cross-sectional view of a layer structure 200 according to various embodiments.

[0079] exist FIG. 2A to FIG. 2H , Figure 2J , Figure 3A and Figure 3B In an exemplary embodiment of the present invention, the layer structure 200 includes a chip 220 (also referred to as a die). The chip 220 may be, for example, a semiconductor chip based on silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or other semiconductor materials known in the art. The thickness of the chip 220 may be in the range from about 20 μm to about 380 μm, wherein the thickness may include chip metallization 220B, 220F.

[0080] Various embodiments may not include chip 220, such as Fig.2IAs shown in the exemplary embodiment of FIG.

[0081] The layer structure 200 may include a first layer 222, which may include nickel or a nickel alloy or a different metal commonly used for chip metallization, such as copper, gold, silver, tin, zinc, platinum and / or palladium, and a third layer 222, which includes nickel or a nickel alloy or a different metal commonly used for conductive substrates 224, 222 (e.g., lead frames) and / or for a conductive layer 222 formed on the substrate 224, and a second layer 101 between the first layer 222 and the third layer 222.

[0082] The first layer 222 and the third layer 222 may be similar or identical, or may be configured differently. However, since they are in principle interchangeable, they are identified by the same reference numeral 222 .

[0083] The following table shows what kind of metallization may be suitable as first layer 222 or second layer 222, respectively (in an exemplary manner for front side metallization FSM, for back side metallization BSM and for PCB metallization, respectively):

[0084]

[0085] In the table, X may represent any suitable metal, such as metals known in the art, such as copper, copper alloys, aluminum, aluminum alloys, or the like. The entries in the table may indicate the suitability of using the solder material 100 to form the layer structure 200 according to various embodiments. + may indicate good suitability, + may indicate very good suitability, and (+) may indicate limited / reduced suitability.

[0086] Regarding Cu metallization, a key issue in combination with Sn-rich solders may be the continuous Cu-Sn phase formation, which may often lead to complete consumption of the copper and subsequent failure of the device. However, experiments have shown (see e.g. Fig. 9 ), Cu is an applicable metallization because most of the Sn can be converted into the thermodynamically stable high temperature Ni-Sn phase, and only a small amount of Sn, if any, may be available for Cu-Sn phase formation, so that the Cu layer is usually not completely consumed.

[0087] The second layer 101 may be formed from the solder material 100. In order to distinguish between the solder material 100 before the soldering process and the solder layer 101 formed by the soldering process, different reference numerals 100, 101 are used.

[0088] The first layer 222 and / or the third layer 222 may include, consist of, or consist essentially of at least one of the following group, the group including nickel, nickel vanadium (NiV), nickel phosphide, such as NiP, nickel silicide (NiSi), copper, gold, silver, tin, zinc, platinum and palladium and / or alloys of any of these materials.

[0089] The thickness of the first layer 222 and / or the thickness of the third layer 222 may be in a range from about 100 nm to about 5 μm.

[0090] like Figure 2J As shown in , the electrically conductive substrate 224 may have a further layer 222 on its bottom side which may face away from the second layer 101 .

[0091] exist Fig.2I , the first layer 222 and the third layer 222 are shown without any additional elements to which they may be attached (except the second layer 101). However, in general, each of the first layer 222 and / or the third layer 222 may be part of or fixed to an element or device that should be connected by the second layer 101.

[0092] An exemplary embodiment of a layer structure 200 including such an element or device is FIG. 2A to FIG. 2H , Figure 3A and Figure 3B Shown in.

[0093] In various embodiments, the layer structure 200 may include a plurality of first layers 222 , a plurality of second layers 101 , and a plurality of third layers 222 .

[0094] In various embodiments, at least one of the first layer 222 and the third layer 222 may be or include chip metallization 220B, 220F, also referred to as contact surface. The chip metallization 220B, 220F may be present on two opposite sides of the chip 220, respectively referred to as back metallization 220B and front metallization 220F. One or both of the chip metallizations 220F, 220B may include or consist of nickel and / or a nickel alloy. In various embodiments, the nickel and / or nickel alloy may be capped by a metal finish (e.g., Ni / Au, NiP / Pd / Au, etc.) to avoid oxidation. The metal finish may be configured in such a manner, for example, with respect to thickness, composition, etc., so that the welding process as described herein, in particular the formation of intermetallic compound phases, is not disturbed or substantially not disturbed.

[0095] The thickness of one or both of the chip metallizations 220F, 220B may be at least 200 nm, for example in the range from about 200 nm to about 5 μm.

[0096] exist Figure 2A In an exemplary embodiment of the present invention, the first interconnect can be formed by one of the first layers 222, one of the second layers 101 and one of the third layers 222, one of the first layers 222 can be a nickel-containing plating layer 222 formed on a conductive substrate 224, such as a lead frame such as a copper lead frame, one of the second layers 101 is connected to the first layer 222, and one of the third layers 222 can be a nickel-containing back side metallization 220B of the chip 220, also referred to as the contact surface of the chip 220, i.e., the back side contact surface.

[0097] The second interconnect can be formed by another one of the first layer 222, which can be the nickel-containing front side metallization 220F of the chip 220, another one of the second layer 101 connected to the first layer 222, and another one of the third layer 222, wherein the other one of the third layer 222 can be a nickel-containing plated layer 222 formed on a conductive structure 226, such as on a clip such as a copper clip, or the like. Figure 2B The embodiments can be used with Figure 2A The embodiment of is different from that of in that the second interconnect does not include a clip carrying another one of the third layers 222. Instead, a metal contact 226 of a different configuration, such as a copper contact, may be provided on which another one of the third layers 222 is formed.

[0098] Figure 2C The embodiments can be used with Figure 2A and Figure 2B The embodiment of the present invention differs from that of the present invention in that substantially no second interconnect is formed. Instead, the front side metallization 220F of the chip 220 may be exposed, for example for contacting by conventional means, for example as described above, for example by diffusion solder interconnection.

[0099] Figure 2D The embodiments can be used with Figure 2B The embodiments are different, and the difference is basically that Figure 2D The conductive substrate 224 is replaced by an isolation substrate 224, 232, 234, which includes a conductive layer 224, such as a copper layer, having a first layer 222 formed on its front side, a ceramic layer 232 attached to the back side of the conductive layer 224 with its front side, and a metal layer 234 attached to the back side of the ceramic layer 232.

[0100] To indicate that the two second layers 101 may be formed in a common soldering process (in which case both layers will be transformed simultaneously from a layer of solder material 100 to a second layer 101) or in a consecutive process (in which case a first of the layers of solder material 100 will already be transformed to a second layer 100 and subsequently to a further second layer 101 before a further layer of the layer of solder material 100 is applied), in Figure 2B , Figure 2C and Figure 2D The corresponding layers are marked with two reference numerals 100 and 101 .

[0101] Figure 2E The embodiments can be used with Figure 2C The embodiments are different, and the difference is basically that Figure 2D The conductive substrate 224 is replaced by an isolation substrate 224, 232, 234, which includes a conductive layer 224, such as a copper layer, having a first layer 222 formed on its front side, a ceramic layer 232 attached to the back side of the conductive layer 224 with its front side, and a metal layer 234 attached to the back side of the ceramic layer 232.

[0102] Figure 2F The embodiments can be used with Figure 2E The embodiment of the present invention is different from the embodiment of the present invention, which is different basically in that no isolation substrate 224, 232, 234 is provided, but instead a two-layer isolation substrate 224, 232 is provided. The two-layer isolation substrate 224, 232 may include a conductive layer 224, such as a copper layer, having a first layer 222 formed on its front side, and an electrically insulating layer 232 attached to the back side of the conductive layer 224 at its front side. The electrically insulating layer 232 may include or consist of any electrically insulating material (one or more) used for isolation substrates in the art, such as ceramics, glass, organic materials, etc.

[0103] Figure 2G The embodiments can be used with Figure 2D The embodiment of the present invention is different from the embodiment of the present invention, which is different basically in that no isolation substrate 224, 232, 234 is provided, but instead a two-layer isolation substrate 224, 232 is provided. The two-layer isolation substrate 224, 232 may include a conductive layer 224, such as a copper layer, having a first layer 222 formed on its front side, and an electrically insulating layer 232 attached to the back side of the conductive layer 224 at its front side. The electrically insulating layer 232 may include or consist of any electrically insulating material (one or more) used for isolation substrates in the art, such as ceramics, glass, organic materials, etc.

[0104] Figure 2H The embodiments can be used with Figure 2B The embodiment of the present invention is different in that the first interconnect is not formed. Instead, the back side 220B of the chip 220 may be attached to the conductive substrate 224 by diffusion soldering.

[0105] In various embodiments, the second layer 101 may consist of or consist essentially of nickel and tin.

[0106] Figure 3A and Figure 3BThe exemplary embodiments of the layer structure 200 shown in each case can be combined with Figure 2C The layer structure 200 is similar or identical to that of FIG. 1 , except that the properties of the second layer 101 are visualized.

[0107] The second layer 101 may include an intermetallic compound phase of nickel and tin.

[0108] exist Figure 3A In various embodiments, an exemplary embodiment of which is shown in , the second layer 101 may consist of an intermetallic compound phase or consist essentially of an intermetallic compound phase. In this case, the absolute amount of nickel contained in the first amount of particles 104_1 of the solder material 100 and in the second amount of particles 104_2 of the solder material 100, and / or the relative amount of nickel contained in the first amount of particles 104_1 and in the second amount of particles 104_2, respectively, and / or the absolute and / or relative size of the first amount of particles 104_1 and the second amount of particles 104_2 may be selected so that not only the first amount of particles 104_1 are completely melted, but also the second amount of particles 104_2 are substantially or completely melted to form an intermetallic compound phase.

[0109] exist Figure 3B In various embodiments, exemplary embodiments of which are shown in , the second layer 101 may include nickel particles 104_2 having a size greater than the thickness of the first layer 222 and / or greater than the thickness of the third layer 222. The nickel particles 104_2 may be remnants of the amount of second particles 104_2 originally contained in the solder material 100, i.e., remnants of the amount of larger particles 104_2. During the soldering process, when the temperature of the solder material 100 surrounding the larger particles 104_2 reaches the melting temperature of nickel, a portion of the larger particles 104_2 may have melted. However, before melting the entire larger nickel particles 104_2, the molten solder material 100 reaches a composition suitable for forming an intermetallic compound phase and is thus solidified, thereby encapsulating the remaining larger particles 104_2.

[0110] A similar situation may occur if the particles have a size different from the size of the first amount of particles 104_1 and / or from the size of the second amount of particles 104_2, for example the third amount of particles 104_3 and / or the further particles 104_E. Particles up to a limiting size may have been completely melted and included in the intermetallic phase, while remnants of particles larger than the limiting size may remain in the second layer 101. The limiting size may be higher than the maximum size of the first amount of particles 104_1 present in the solder material 100.

[0111] In other words, the second layer 101 may further include additional nickel particles having a size smaller than that of the nickel particles 104_2 .

[0112] In various embodiments, the intermetallic compound phase may form between about 80% and about 95% by weight of the second layer 101 .

[0113] The intermetallic compound phase may consist of or consist essentially of Ni3Sn4 and / or Ni3Sn2 in various embodiments.

[0114] The thickness of the second layer 101 may be in the range from about 50 μm to about 70 μm.

[0115] Figure 4A and Figure 4B Each of them shows a schematic cross-sectional view of a chip package 400 according to various embodiments.

[0116] The chip package 400 may include the layer structure 200 as described above, for example as described in relation to FIG. 2A to FIG. 2J , Figure 3A and / or Figure 3B For the purpose of illustration, select Figure 2C The embodiment of FIG. 4 is used as the basis for the chip package 400 .

[0117] The chip package 400 may include a chip 220. The chip 220 is already included in FIG. 2A to FIG. 2H , Figure 3A and Figure 3B In the embodiment of the layer structure 200, however, it will need to be added to Figure 2J Embodiment of a layer structure 200 .

[0118] Chip 220 may include, for example, first layer 222 as (eg backside) chip metallization 220B, electrically conductive substrates 224 , 222 including third layer 222 , and an encapsulation 440 at least partially encapsulating chip 220 and at least one of first layer 222 , 220B, second layer 100 and third layer 222 .

[0119] Encapsulation 440 may include or consist of encapsulation materials known in the art and may be disposed by known processes.

[0120] exist Figure 4B In the exemplary embodiment shown in Figure 2J The layer structure 200 of FIG. 4 is used as a basis for the chip package 400 . However, any other layer structure 200 according to various embodiments may be used as a corresponding basis for the chip package 400 . Figure 4A The chip package 400 with Figure 4B The differences between the chip packages 400 may be Figure 4A The conductive substrate 224 may not be suitable as the (additional) layer 222, or may alternatively be suitable as the (additional) layer 222, and Figure 4B The electrically conductive substrate 224 may have a (further) layer 222 arranged on its bottom side opposite to the chip 220 . The (further) layer 222 or a respective suitability may refer to a suitability for soldering using the solder material 100 according to various embodiments.

[0121] Figure 4B (or alternatively, Figure 4A The chip package 400 may be configured to be soldered to contact pads, for example, contact pads of a printed circuit board. The conductive substrate 224 or at least one or more portions thereof forming or including the layer 222 may be configured to electrically contact the chip and may therefore be referred to as metal leads. They may be exposed or protrude from the encapsulation 440 of the chip package 400.

[0122] Fig. 10A and 10B Each of them shows a schematic cross-sectional view of a chip arrangement 1000 according to various embodiments.

[0123] The chip arrangement 1000 may include a chip package 400 according to various embodiments, for example Figure 4A and Figure 4B As shown in .

[0124] The chip package 400 may include one or more metal leads 224, 222 (in Fig. 10A and 10B In each of the figures, two metal leads 224, 222 are shown, which can be configured to electrically contact the chip 220. The metal leads 224, 222 can be exposed and can have an outer surface forming a layer 222, for example by providing the conductive substrate 224 with a material that can be suitable for soldering with the solder 100, or by providing a suitable layer 222 on the conductive substrate 224.

[0125] The chip arrangement 1000 may further include a printed circuit board 1100 , which may include a base material 1110 , which may be a dielectric, and at least one contact pad ( 1112 ).

[0126] The chip arrangement 1000 may further include a layer 101 between the at least one metal lead 224, 222 and the at least one contact pad 224, 222. The layer 101 may be similar or identical to the second layer 101 described above, for example in the context of the layer structure 400. The layer 101 may be formed of a solder material 100. The layer 101 may be formed by the soldering process described above and below according to various embodiments.

[0127] In various embodiments, the layer 101 may consist of or consist essentially of nickel and tin, and may include an intermetallic phase of nickel and tin. In various embodiments, the layer 101 may include nickel particles 104_2 having a size greater than the thickness of the metal leads 224, 222 and / or greater than the thickness of the contact pad 1112.

[0128] In various embodiments, at least one metal lead 224, 222 and at least one contact pad 1112 may respectively include at least one of or consist of a material from a group of materials including nickel, copper, gold, platinum, tin, zinc, palladium, and alloys of any of these materials.

[0129] In various embodiments, at least one metal lead 224 , 222 and / or at least one contact pad may include a plating layer 222 .

[0130] In various embodiments, the plating layer 222 may include at least one of or consist of a material from a group of materials consisting of nickel, copper, gold, palladium, and alloys of any of these materials.

[0131] In various embodiments, the thickness of the plating layer 222 may be in a range from about 100 nm to about 5 μm.

[0132] Figure 6 A flow chart 600 of a method of forming a layer structure according to various embodiments is shown.

[0133] The method may include disposing a layer of solder material as described above according to various embodiments between a first layer including nickel or a nickel alloy and a third layer including nickel or a nickel alloy ( 610 ).

[0134] Depending on the type of solder material that can be used, the arrangement can be done differently and essentially as known in the art, for example from solder materials containing lead.

[0135] For example, where the solder material is applied as solder paste, the solder paste may be applied by dispensing or printing the solder paste onto the first layer and / or the second layer, such as dispensing or printing onto the lead frame and / or the front side of the die and / or the clip and / or the back side of the die. Where the solder material is applied as a solder preform or other solid type of solder material, the solder preform or the like may be arranged on the first layer, and the second layer may be arranged on the solder material.

[0136] The method may further include heating the layer structure to a melting temperature of the solder material until an intermetallic phase is formed (620).

[0137] In various embodiments, multiple solder interconnects may be formed simultaneously in the same layer structure, for example one above the other.

[0138] Alternatively, since the melting temperature of the intermetallic compound phase is much higher than the melting temperature of the solder material, sequential formation of solder interconnections in the device may be performed.

[0139] For example, after arranging the solder material between the first layer and the second layer, for example, after placing the chip on the lead frame and placing the clip on the die front side (here, two solder connections can be formed simultaneously, one between the lead frame and the chip, and the other between the chip and the clip, which can result in Figure 2A After the layer structure shown in ), thus forming a stack, the stack can be heated in a reflow or box oven with a specific temperature profile adjusted to the mentioned materials and thicknesses. Alternatively, a two-step process with separate reflow processes for die attach and for clip attach can be performed.

[0140] Figure 7 A flowchart 700 of a method of forming a chip package according to various embodiments is shown.

[0141] The method may include arranging a layer of solder material as described above according to various embodiments between a first layer comprising nickel or a nickel alloy and a third layer comprising nickel or a nickel alloy, wherein the first layer is a chip metallization layer and wherein the second layer is part of a conductive substrate (710).

[0142] The method may further include heating the layer structure to a melting temperature of the solder material until an intermetallic phase is formed (720).

[0143] So far, the method of forming the chip package may be the same as the method of forming the layer structure in case the first layer is a chip metallization layer and the second layer is part of the conductive substrate.

[0144] The method may also include forming an encapsulation at least partially encapsulating the chip and the layer structure ( 730 ).

[0145] Figure 8 A flow chart 800 of a method of forming a chip arrangement is shown.

[0146] The method may include arranging a layer of solder material according to various embodiments between at least one metal lead of the chip package and a contact pad of a printed circuit board (810), and heating the solder material to a melting temperature of the solder material until an intermetallic phase is formed (820).

[0147] Various examples are described below:

[0148] Example 1 is a solder material. The solder material may include nickel and tin, wherein the nickel may include a first amount of particles and a second amount of particles, wherein the sum of the first amount of particles and the second amount of particles is the total amount of nickel or less, wherein the first amount of particles is between 5 at% and 60 at% (preferably between 25 at% and 60 at%) of the total amount of nickel, wherein the second amount of particles is between 10 at% and 95 at% (preferably between 10 at% and 75 at%) of the total amount of nickel, wherein the particles of the first amount of particles have a size in the range from about 1 μm to about 20 μm, and wherein the particles of the second amount of particles have a size in the range from about 30 μm to about 50 μm.

[0149] In Example 2, the subject matter of Example 1 can optionally include that a size of particles of the first amount of particles has a size from about 3 μm to about 7 μm.

[0150] In Example 3, the subject matter of Example 1 can optionally include that a size of particles of the first amount of particles has a size from about 5 μm to about 15 μm.

[0151] In Example 4, the subject matter of any one of Examples 1 to 3 can optionally include that a size of particles of the second amount of particles has a size from about 35 μm to about 40 μm.

[0152] In Example 5, the subject matter of any one of Examples 1 to 4 can optionally include the particles being spherical or substantially spherical.

[0153] In Example 6, the subject matter of any of Examples 1 to 5 can optionally include the nickel comprising a third amount of particles, wherein the sum of the first amount of particles, the second amount of particles, and the third amount of particles is the total amount of nickel or less, wherein the third amount of particles is between 10 at % and 85 at % of the total amount of nickel, and wherein particles of the third amount of particles have a size in a range from greater than 20 μm to less than 30 μm.

[0154] In Example 7, the subject matter of any one of Examples 1 to 6 can optionally include the solder material having a nickel amount in a range from about 35 at % to about 90 at %.

[0155] In Example 8, the subject matter of any one of Examples 1 to 7 can optionally include that the solder material is configured as a solder paste.

[0156] In Example 9, the subject matter of Example 8 can optionally include that the solder paste comprises a tin-based soft solder having a first amount of particles and a second amount of particles distributed therein.

[0157] In Example 10, the subject matter of any one of Examples 1 to 9 can optionally include that the solder material is configured as a solder wire.

[0158] In Example 11, the subject matter of any one of Examples 1 to 9 can optionally include that the solder material is configured as a compacted solder powder or as a solder preform.

[0159] Example 12 is a layer structure. The layer structure may include a first layer comprising nickel or a nickel alloy, a third layer comprising nickel or a nickel alloy, and a second layer between the first layer and the third layer, wherein the second layer consists of or consists essentially of nickel and tin, wherein the second layer includes an intermetallic phase of nickel and tin, and wherein optionally, the second layer includes nickel particles having a size greater than the thickness of the first layer and / or greater than the thickness of the third layer.

[0160] In Example 13, the subject matter of Example 12 can optionally include the intermetallic phase forming between about 80% and about 95% by weight of the second layer.

[0161] In Example 14, the subject matter of Example 13 can optionally include the intermetallic phase consisting of or consisting essentially of Ni3Sn4 and / or Ni3Sn2.

[0162] In Example 15, the subject matter of any one of Examples 12 to 14 can optionally include that the second layer further includes additional nickel particles having a size smaller than a size of the nickel particles.

[0163] In Example 16, the subject matter of any of Examples 12 to 15 may optionally include that the first layer and / or the third layer includes, consists of, or consists essentially of at least one of the group consisting of nickel, nickel vanadium (NiV), nickel phosphide, such as NiP, nickel silicide (NiSi), copper, gold, silver, platinum, tin, zinc, and palladium.

[0164] In Example 17, the subject matter of any one of Examples 12 to 16 can optionally include that a thickness of the first layer and / or a thickness of the third layer is in a range from about 100 nm to about 5 μm.

[0165] In Example 18, the subject matter of any one of Examples 12 to 17 can optionally include that the second layer has a thickness in a range from about 50 μm to about 70 μm.

[0166] Example 19 is a chip package. The chip package may include the layer structure of any one of Examples 12 to 18, a chip including a first layer, a conductive substrate including a third layer, and an encapsulation at least partially encapsulating the chip and at least one of the first layer, the second layer, and the third layer.

[0167] Example 20 is a method for forming a layer structure, the method comprising arranging a layer of a solder material according to any one of Examples 1 to 11 between a first layer comprising nickel or a nickel alloy and a third layer comprising nickel or a nickel alloy, and heating the layer structure to the melting temperature of the solder material until an intermetallic compound phase is formed.

[0168] In Example 21, the subject matter of Example 20 can optionally include that the second layer includes nickel particles having a size greater than a thickness of the first layer and / or greater than a thickness of the third layer.

[0169] In Example 22, the subject matter of Example 20 or 21 can optionally include the intermetallic phase forming between about 80% and about 95% by weight of the second layer.

[0170] In Example 23, the subject matter of any of Examples 20 to 22 can optionally include the intermetallic phase consisting of or consisting essentially of Ni3Sn4 and / or Ni3Sn2.

[0171] In Example 24, the subject matter of any one of Examples 20 to 23 can optionally include that the second layer further includes additional nickel particles having a size smaller than a size of the nickel particles.

[0172] In Example 25, the subject matter of any of Examples 20 to 24 may optionally include that the first layer and / or the third layer includes, consists of, or consists essentially of at least one of the group consisting of nickel, nickel vanadium (NiV), nickel phosphide, e.g., NiP, nickel silicide (NiSi), copper, gold, silver, platinum, tin, zinc, and palladium.

[0173] In Example 26, the subject matter of any one of Examples 20 to 25 can optionally include that a thickness of the first layer and / or a thickness of the third layer is in a range from about 100 nm to about 5 μm.

[0174] In Example 27, the subject matter of any one of Examples 20 to 26 can optionally include that the second layer has a thickness in a range from about 50 μm to about 70 μm.

[0175] Example 28 is a method of forming a chip package. The method may include forming a layer structure according to any one of Examples 20 to 27, wherein the first layer is a chip metallization layer, and wherein the second layer is part of a conductive substrate, and forming an encapsulation that at least partially encapsulates the chip and the layer structure.

[0176] Example 29 is a layer structure. The layer structure may include a first layer, the first layer includes at least one material of a first group of materials or consists of materials of the first group of materials, the first group includes nickel, copper, gold, silver, palladium, tin, zinc, platinum and alloys of any of these materials, a third layer, the third layer includes at least one material of a second group of materials or consists of materials of the second group of materials, the second group includes nickel, copper, gold, palladium, tin, silver, zinc, platinum and alloys of any of these materials, and a second layer between the first layer and the third layer, wherein the second layer consists of nickel and tin or consists essentially of nickel and tin, wherein the second layer includes an intermetallic compound phase of nickel and tin, and wherein optionally, the second layer includes nickel particles, the nickel particles having a size greater than the thickness of the first layer and / or greater than the thickness of the third layer.

[0177] In Example 30, the subject matter of Example 29 can optionally include an intermetallic phase forming an interconnect structure.

[0178] In Example 31, the subject matter of Example 19 can optionally include that the conductive substrate is a lead frame.

[0179] In Example 32, the subject matter of Example 31 can optionally include that the third layer is a plating layer formed on the lead frame.

[0180] In Example 33, the subject matter of Examples 19, 31, or 32 can optionally include the first layer being a plated layer formed on chip metallization.

[0181] In Example 34, the subject matter of any of Examples 19 or 31 to 33 may optionally include that the first layer and / or the third layer includes, consists of, or consists essentially of at least one of the group consisting of nickel, nickel vanadium (NiV), nickel phosphide, such as NiP, nickel silicide (NiSi), copper, gold, silver, tin, platinum, zinc, and palladium.

[0182] In Example 35, the subject matter of any one of Examples 19 or 31 to 34 can optionally include that a thickness of the first layer and / or a thickness of the third layer is in a range from about 100 nm to about 5 μm.

[0183] Example 36 is a chip arrangement. The chip arrangement may include a chip package, a printed circuit board, and a layer, the chip package including a chip and at least one metal lead for electrically contacting the chip from outside the package, the printed circuit board including at least one contact pad, the layer between the at least one metal lead and the at least one contact pad, wherein the layer consists of or consists essentially of nickel and tin, wherein the layer includes an intermetallic phase of nickel and tin, and wherein optionally, the layer includes nickel particles having a size greater than the thickness of the metal lead and / or greater than the thickness of the contact pad.

[0184] In Example 37, the subject matter of Example 36 may optionally include that at least one metal lead and at least one contact pad respectively include at least one of the materials in the group of materials or consist of materials in the group of materials, the group including nickel, copper, gold, platinum, palladium, tin, zinc, and alloys of any of these materials.

[0185] In Example 38, the subject matter of Example 36 or 37 can optionally include at least one metal lead and / or at least one contact pad including a plating layer.

[0186] In Example 39, the subject matter of Example 38 can optionally include that the coating includes, consists of, or consists essentially of at least one of the group consisting of nickel, nickel vanadium (NiV), nickel phosphide, e.g., NiP, and nickel silicide (NiSi), copper, gold, silver, platinum, tin, zinc, and palladium.

[0187] In Example 40, the subject matter of Example 39 can optionally include the plating layer having a thickness in a range from about 100 nm to about 5 μm.

[0188] Example 41 is a method of forming a layer structure. The method may include arranging a layer of a solder material according to any one of Examples 1 to 11 between a first layer and a third layer, wherein the first layer and the third layer each include at least one of a material in a group of materials or consist of a material in a group of materials, the group including nickel, copper, gold, palladium, and alloys of any of these materials, and heating the layer structure to a melting temperature of the solder material until an intermetallic compound phase is formed.

[0189] In Example 42, the subject matter of Example 40 may optionally further include forming the first layer and / or the third layer as a plating layer having at least one of the group including nickel vanadium (NiV), nickel phosphide, e.g., NiP, nickel silicide (NiSi), copper, gold, silver, platinum, tin, silver, zinc and palladium, and alloys of any of these materials.

[0190] In Example 43, the subject matter of Example 42 can optionally include a melting temperature of the intermetallic phase being higher than a melting temperature of the solder material.

[0191] Example 44 is a method of forming a chip arrangement. The method may include arranging a layer of a solder material according to any one of Examples 1 to 11 between at least one metal lead of a chip package and a contact pad of a printed circuit board, and heating the solder material to a melting temperature of the solder material until an intermetallic compound phase is formed.

[0192] In Example 45, the subject matter of Example 44 can optionally include a melting temperature of the intermetallic phase being higher than a melting temperature of the solder material, optionally by at least 100K higher.

[0193] In Example 46, the subject matter of Example 44 or 45 can optionally further include soldering at least one additional circuit element to the printed circuit board, thereby heating the intermetallic phase to a temperature above the melting temperature of the solder material but below the melting temperature of the intermetallic phase. Example 47 is a solder material. The solder material may include nickel and tin, wherein the nickel may include a first amount of particles and a second amount of particles, wherein the sum of the first amount of particles and the second amount of particles is the total amount of nickel or less, wherein the first amount of particles is between 5at% and 60at% (preferably between 25at% and 60at%) of the total amount of nickel, wherein the second amount of particles is between 10at% and 95at% (preferably between 10at% and 75at%) of the total amount of nickel, wherein the particles of the first amount of particles have a first size distribution, wherein the particles of the second amount of particles have a second size distribution, wherein 30% to 70% of the first amount of particles have a particle size within a range of approximately 5 μm around the particle size with the highest number of particles according to the first size distribution, and wherein 30% to 70% (optionally 40% to 60%) of the second amount of particles have a particle size within a range of approximately 5 μm around the particle size with the highest number of particles according to the second size distribution.

[0194] In Example 48, the subject matter of Example 47 can optionally include particles of the first amount of particles having a size in a range from about 0.5 μm to about 20 μm, and particles of the second amount of particles having a size in a range from about 30 μm to about 50 μm.

[0195] In Example 49, the subject matter of Example 47 or 48 can optionally include the tin being part of the tin-rich material.

[0196] In Example 50, the subject matter of Example 49 can optionally include that the tin-rich material includes at least one material from a group of materials, the group including Sn, SnAg, SnAgCu, SnCu, SnSb, and a different tin-rich material consisting essentially of Sn and being substantially lead-free or lead-free.

[0197] In Example 51, the subject matter of any of Examples 47 to 50 may optionally include the nickel comprising a third amount of particles, wherein the sum of the first amount of particles, the second amount of particles, and the third amount of particles is the total amount of nickel or less, the third amount of particles is between 10 at % and 85 at % of the total amount of nickel, and the particles of the third amount of particles have a third size distribution, wherein 30% to 70% (optionally 40% to 60%) of the third amount of particles have a particle size within a range of approximately 5 μm around the particle size having the highest amount of particles according to the third size distribution.

[0198] In Example 52, the subject matter of Example 51 can optionally include that particles of the third amount of particles have a size in a range from greater than 20 μm to less than 30 μm.

[0199] Although the present invention has been particularly shown and described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims. Therefore, the scope of the present invention is indicated by the appended claims and is therefore intended to include all changes within the meaning and range of equivalents of the claims.

Claims

1. A layer structure comprising: a first layer comprising at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and alloys of any of these materials; a third layer comprising at least one material selected from the second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and alloys of any of these materials; and The second floor, between the first and third floors; wherein the second layer consists of or consists essentially of nickel and tin, wherein the second layer comprises an intermetallic compound phase of nickel and tin, and The second layer further comprises nickel particles and additional nickel particles, the additional nickel particles having a size smaller than the size of the nickel particles. 2 . The layer structure according to claim 1 , wherein the size of the nickel particles of the second layer is greater than the thickness of the first layer and / or greater than the thickness of the third layer.

3. The layer structure of claim 1, wherein the intermetallic phase forms between about 60% and about 95% by weight of the second layer.

4. The layer structure according to claim 1, wherein the intermetallic compound phase consists of or essentially consists of Ni3Sn4 and / or Ni3Sn2. The layer structure according to claim 1 , wherein the intermetallic compound phase forms an interconnect structure. The layer structure according to claim 5 , wherein the interconnect structure has a sponge-like shape.

7. The layer structure according to claim 1, wherein the first layer and / or the third layer further comprises at least one of nickel, nickel vanadium, nickel phosphide, nickel silicide, copper, gold, silver, tin, platinum, palladium, and zinc. 8 . The layer structure according to claim 1 , wherein a thickness of the first layer and / or a thickness of the third layer is in the range from about 100 nm to about 5 μm. 9 . The layer structure according to claim 1 , wherein the thickness of the second layer is in the range from about 50 μm to about 70 μm.

10. A chip package, comprising: The layer structure according to claim 1; A chip including a first layer; a conductive substrate including a third layer; as well as Encapsulating, at least partially encapsulating the chip and at least one of the first layer, the second layer, and the third layer. The chip package according to claim 10 , wherein the conductive substrate is a lead frame. 12 . The chip package according to claim 11 , wherein the third layer is a plating layer formed on the lead frame.

13. The chip package of claim 10, wherein the first layer is a plating layer formed on chip metallization. 14 . The chip package according to claim 10 , wherein the first layer and / or the third layer comprises at least one of nickel, nickel vanadium, nickel phosphide, nickel silicide, copper, gold, silver, platinum, tin, zinc, and palladium. 15 . The chip package according to claim 10 , wherein a thickness of the first layer and / or a thickness of the third layer is in a range from about 100 nm to about 5 μm.

16. A chip arrangement comprising: The chip package according to claim 10; a metal lead configured to electrically contact the chip from outside the chip package; a printed circuit board including contact pads; and The layer between the metal leads and the contact pads, wherein the layer consists of or consists essentially of nickel and tin, Wherein the layer comprises an intermetallic compound phase of nickel and tin. 17 . The chip arrangement of claim 16 , wherein the layer between the metal lead and the contact pad comprises nickel particles having a size greater than a thickness of the metal lead and / or greater than a thickness of the contact pad. 18 . The chip arrangement of claim 16 , wherein the metal lead and the contact pad each comprise at least one of nickel, copper, gold, platinum, palladium, tin, zinc, and alloys of any of these materials. The chip arrangement according to claim 16 , wherein the metal leads and / or the contact pads comprise a plating layer.

20. A layer structure comprising: a first layer comprising at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and alloys of any of these materials; a third layer comprising at least one material selected from the second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and alloys of any of these materials; and The second floor, between the first and third floors, wherein the second layer consists of or consists essentially of nickel and tin, wherein the second layer comprises an intermetallic compound phase of nickel and tin, and The intermetallic compound phase forms an interconnected structure having a sponge-like shape.

21. A layer structure comprising: a first layer comprising at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and alloys of any of these materials; a third layer comprising at least one material selected from the second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and alloys of any of these materials; and The second floor, between the first and third floors, wherein the second layer consists of or consists essentially of nickel and tin, wherein the second layer comprises an intermetallic compound phase of nickel and tin, and The thickness of the first layer and / or the thickness of the third layer is in the range from about 100 nm to about 5 μm.

22. A layer structure comprising: a first layer comprising at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and alloys of any of these materials; a third layer comprising at least one material selected from the second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and alloys of any of these materials; and The second floor, between the first and third floors, wherein the second layer consists of or consists essentially of nickel and tin, wherein the second layer comprises an intermetallic compound phase of nickel and tin, and The thickness of the second layer is in the range from about 50 μm to about 70 μm.

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