User-defined instruction code operation method and device, computer equipment and storage medium

Abstract

The invention provides a user-defined instruction code operation method and device, computer equipment and a storage medium, and is applied to the technical field of computers, and the method specifically comprises the steps that whether preset operation is executed or not is detected, and the preset operation comprises data read / write traversal operation, data comparison operation and bit operation; when the preset operation needs to be executed, a user-defined instruction code corresponding to the preset operation is obtained in a user-defined instruction code set, and the operation corresponding to the user-defined instruction code is a combined operation corresponding to a series of conventional instruction codes; and executing an operation corresponding to the custom instruction code. According to the method, the burden of the processor caused by multiple reading operations and pre-decoding operations can be reduced, and the running efficiency of the processor is improved. Meanwhile, due to the fact that one custom instruction code can generally achieve the functions of a plurality of conventional instruction codes, the code space can be saved by using the custom instruction code set.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an operation method, device, computer equipment and storage medium of a custom instruction code. Background Art

[0002] RISC-V is an open source instruction set architecture. When a processor based on the RISC-V instruction set architecture needs to perform a certain operation, it will read the instruction code corresponding to the operation in the RISC-V instruction set in advance, then decode the instruction code to obtain the execution information corresponding to the instruction code, and then execute the operation based on the execution information.

[0003] In the prior art, each conventional instruction code in the RISC-V instruction set often corresponds to an operation. When multiple operations need to be performed, the processor often needs to read the corresponding instruction codes separately.

[0004] However, in implementing some application requirements that require executing multiple operations, the processor often reads multiple instruction codes in sequence and decodes each instruction code separately. Multiple reading and decoding operations increase the burden on the processor and reduce the processor's operating efficiency. Summary of the invention

[0005] The embodiments of the present application provide a method, apparatus, computer device and storage medium for operating a custom instruction code. In implementing certain specific application requirements, the method can reduce the burden on the processor due to multiple read operations and decoding operations, thereby improving the operating efficiency of the processor. At the same time, since a custom instruction code can usually implement the functions of multiple conventional instruction codes, using a custom instruction code set can save code space.

[0006] A first aspect of an embodiment of the present application provides an operation method of a custom instruction code, comprising: Detecting whether to execute a preset operation, wherein the preset operation includes a data read / write traversal operation, a data comparison operation, and a bit operation; When the preset operation needs to be executed, the custom instruction code corresponding to the preset operation is obtained from the custom instruction code set, and the operation corresponding to the custom instruction code is a combination of operations corresponding to a series of conventional instruction codes; Execute the operation corresponding to the custom instruction code; Wherein, when the preset operation is a data read traversal operation, the type of the first operand is a base register, the first operand is a base address indicated by the base register, the type of the second operand is an immediate number, and the operation corresponding to the execution of the custom instruction code includes: determining the target register according to the data bit corresponding to the target register in the custom instruction code; obtaining the data to be loaded from the base address, and loading the data to be loaded into the target register; obtaining a base address update value according to the base address and the second operand; and updating the base address indicated by the base register based on the base address update value; When the preset operation is a data write traversal operation, the type of the first operand is a base register, the first operand is the base address indicated by the base register, the type of the second operand is a source register, the second operand is the value stored in the source register, and the operation corresponding to the execution of the custom instruction code includes: obtaining the third operand in the custom instruction code, the type of the third operand is an immediate number; storing the second operand in the base address indicated by the base register; obtaining a base address update value according to the base address indicated by the base register and the third operand; and updating the base address indicated by the base register based on the base address update value.

[0007] Optionally, the preset operation also includes a data read operation. When the preset operation is a data read operation, the index value of the base register is GP, the type of the first operand is an immediate number, and the operation corresponding to the execution of the custom instruction code includes: Determine the number of left shifts according to the number of bytes of the loaded data; Based on the number of left shifts, perform a left shift operation on the first operand to obtain a first operand after left shift; Adding the first operand after the left shift and a base address indicated by a GP register to obtain a target address, wherein the GP register is determined based on an index value GP; The data to be loaded is obtained from the target address, and the data to be loaded is loaded into the target register.

[0008] Optionally, the preset operation also includes a data write operation. When the preset operation is a data write operation, when the index value of the base register is GP, the type of the first operand is a source register, the first operand is a value stored in the source register, and the type of the second operand is an immediate number, the operation corresponding to the execution of the custom instruction code includes: Determine the number of left shifts according to the number of bytes of the stored data; Based on the number of left shifts, performing a left shift operation on the second operand to obtain a left-shifted second operand; Adding the second operand after the left shift and the base address indicated by the GP register to obtain a target address, the GP register being determined based on the index value GP; The first operand is stored in the target address.

[0009] Optionally, when the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value. The operation corresponding to executing the custom instruction code includes: Obtain a third operand in the custom instruction code, where the type of the third operand is an offset; Comparing the first operand with the second operand to obtain a comparison result; Adding the current address of the custom instruction code and the third operand to obtain a preset target address; When the comparison result is equal, jump to the preset target address to obtain the instruction code; When the comparison result is unequal, the next instruction code of the custom instruction code is obtained.

[0010] Optionally, when the preset operation is a data comparison operation, the type of the first operand is an immediate number, and the type of the second operand is an immediate number; The operation corresponding to executing the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Comparing the first operand with the second operand to obtain a comparison result; When the comparison result is less than or equal to, writing 1 into the target register; When the comparison result is greater than, 0 is written into the target register.

[0011] Optionally, when the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is a value stored in the source register, the type of the second operand is a source register, and the second operand is a value stored in the source register; The operation corresponding to executing the custom instruction code includes: In the custom instruction code, a third operand is obtained, wherein the type of the third operand is an immediate number; Adding the second operand and the preset value to obtain a sum of the two; comparing the sum to the first operand; When the two are not equal, jump to the preset operation and save the sum in the source register; When the two are not equal, the next instruction code of the custom instruction code is obtained.

[0012] Optionally, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The operation corresponding to executing the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a third operand in the custom instruction code, and the type of the third operand is an immediate number; Determine a start interception position and an end interception position according to the second operand and the third operand; According to the start interception bit and the end interception bit, intercepting the first operand to obtain intercepted data; Performing unsigned bit extension or signed bit extension on the intercepted data to obtain extended data; The extended data is stored in the target register.

[0013] Optionally, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The operation corresponding to executing the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Obtain the data to be modified from the first operand according to the start bit and the end bit of the data to be modified; Modifying the data to be modified to obtain modified data; The modified data is stored in the target register.

[0014] Optionally, when the preset operation is a bit operation, executing the operation corresponding to the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a first operand in the custom instruction code, the type of the first operand is a source register, and the first operand is a value in the source register; Starting from the most significant bit of the first operand and ending with the least significant bit of the first operand, counting the number of times the sign bit appears consecutively to obtain statistical data; When the first operand is a preset value, the preset value is written into the target register; otherwise, statistical data is written into the target register.

[0015] Optionally, when the preset operation is a bit operation, executing the operation corresponding to the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, and obtain a first operand in the custom instruction code, wherein the type of the first operand is a source register and the first operand is a value in the source register; Starting from the most significant bit of the source register, determining a preset data bit; When the data of the preset data bit is a preset value, the preset value is written into the target register.

[0016] Optionally, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The operation corresponding to executing the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a third operand in the custom instruction code, and the type of the third operand is an immediate number; According to the second operand, performing a grouping operation on the first operand to obtain grouped data; According to the third operand, performing left shift and flip operations on the grouped data to obtain operated data; The post-operation data is stored in the target register.

[0017] Optionally, when the preset operation is a bit operation, The type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The operation corresponding to executing the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Performing sign bit extension on the second operand to obtain an extended immediate value; The first operand and the extended immediate number are multiplied to obtain a product result, and the product result is saved in the target register.

[0018] A second aspect of the embodiment of the present application provides an operating device for a custom instruction code, comprising: A detection unit, used to detect whether to perform a preset operation, wherein the preset operation includes a data read / write traversal operation, a data comparison operation, and a bit operation; An acquisition unit, used for acquiring, when the preset operation needs to be executed, a custom instruction code corresponding to the preset operation in the custom instruction code set, wherein the operation corresponding to the custom instruction code is a combination of operations corresponding to a series of conventional instruction codes; An execution unit, used for executing the operation corresponding to the custom instruction code; Wherein, when the preset operation is a data read traversal operation, the type of the first operand is a base register, the first operand is a base address indicated by the base register, the type of the second operand is an immediate number, and the execution unit is used to: determine the target register according to the data bit corresponding to the target register in the custom instruction code; obtain the data to be loaded from the base address, and load the data to be loaded into the target register; obtain a base address update value according to the base address and the second operand; and update the base address indicated by the base register based on the base address update value; When the preset operation is a data write traversal operation, the type of the first operand is a base register, the first operand is the base address indicated by the base register, the type of the second operand is a source register, the second operand is the value stored in the source register, and the execution unit is used to: obtain the third operand in the custom instruction code, the type of the third operand is an immediate number; store the second operand in the base address indicated by the base register; obtain a base address update value according to the base address indicated by the base register and the third operand; and update the base address indicated by the base register based on the base address update value.

[0019] Optionally, the preset operation further includes a data read operation. When the preset operation is a data read operation, the index value of the base register is GP, the type of the first operand is an immediate number, and the execution unit is configured to: Determine the number of left shifts according to the number of bytes of the loaded data; Based on the number of left shifts, perform a left shift operation on the first operand to obtain a first operand after left shift; Adding the first operand after the left shift and a base address indicated by a GP register to obtain a target address, wherein the GP register is determined based on an index value GP; The data to be loaded is obtained from the target address, and the data to be loaded is loaded into the target register.

[0020] Optionally, the preset operation further includes a data write operation. When the preset operation is a data write operation, when the index value of the base register is GP, the type of the first operand is a source register, the first operand is a value stored in the source register, and the type of the second operand is an immediate number, the execution unit is configured to: Determine the number of left shifts according to the number of bytes of the stored data; Based on the number of left shifts, performing a left shift operation on the second operand to obtain a left-shifted second operand; Adding the second operand after the left shift and the base address indicated by the GP register to obtain a target address, the GP register being determined based on the index value GP; The first operand is stored in the target address.

[0021] Optionally, when the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value. The execution unit is used for: Obtain a third operand in the custom instruction code, where the type of the third operand is an offset; Comparing the first operand with the second operand to obtain a comparison result; Adding the current address of the custom instruction code and the third operand to obtain a preset target address; When the comparison result is equal, jump to the preset target address to obtain the instruction code; When the comparison result is unequal, the next instruction code of the custom instruction code is obtained.

[0022] Optionally, when the preset operation is a data comparison operation, the type of the first operand is an immediate number, and the type of the second operand is an immediate number; The execution unit is used for: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Comparing the first operand with the second operand to obtain a comparison result; When the comparison result is less than or equal to, writing 1 into the target register; When the comparison result is greater than, 0 is written into the target register.

[0023] Optionally, when the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is a value stored in the source register, the type of the second operand is a source register, and the second operand is a value stored in the source register; The execution unit is used for: In the custom instruction code, a third operand is obtained, wherein the type of the third operand is an immediate number; Adding the second operand and the preset value to obtain a sum of the two; comparing the sum to the first operand; When the two are not equal, jump to the preset operation and save the sum in the source register; When the two are not equal, the next instruction code of the custom instruction code is obtained.

[0024] Optionally, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The execution unit is used for: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a third operand in the custom instruction code, and the type of the third operand is an immediate number; Determine a start interception position and an end interception position according to the second operand and the third operand; According to the start interception bit and the end interception bit, intercepting the first operand to obtain intercepted data; Performing unsigned bit extension or signed bit extension on the intercepted data to obtain extended data; The extended data is stored in the target register.

[0025] Optionally, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The execution unit is used for: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Obtain the data to be modified from the first operand according to the start bit and the end bit of the data to be modified; Modifying the data to be modified to obtain modified data; The modified data is stored in the target register.

[0026] Optionally, when the preset operation is a bit operation, the execution unit is used to: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a first operand in the custom instruction code, the type of the first operand is a source register, and the first operand is a value in the source register; Starting from the most significant bit of the first operand and ending with the least significant bit of the first operand, counting the number of times the sign bit appears consecutively to obtain statistical data; When the first operand is a preset value, the preset value is written into the target register; otherwise, statistical data is written into the target register.

[0027] Optionally, when the preset operation is a bit operation, the execution unit is used to: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a first operand in the custom instruction code, wherein the type of the first operand is a source register, and the first operand is a value in the source register; Starting from the most significant bit of the source register, determining a preset data bit; When the data of the preset data bit is a preset value, the preset value is written into the target register.

[0028] Optionally, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The execution unit is used for: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a third operand in the custom instruction code, and the type of the third operand is an immediate number; According to the second operand, performing a grouping operation on the first operand to obtain grouped data; According to the third operand, performing left shift and flip operations on the grouped data to obtain operated data; The post-operation data is stored in the target register.

[0029] Optionally, when the preset operation is a bit operation, The type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The execution unit is used for: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Performing sign bit extension on the second operand to obtain an extended immediate value; The first operand and the extended immediate number are multiplied to obtain a product result, and the product result is saved in the target register.

[0030] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0031] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0032] In the present application, among all the operations corresponding to a series of conventional instruction codes, some operations that can be combined and executed are found, and the custom instruction code is edited according to these combined operations. After that, it is detected whether to execute the preset operation. When the preset operation needs to be executed, the custom instruction code corresponding to the preset operation is obtained in the custom instruction code set, and the operation corresponding to the custom instruction code is executed, wherein the preset operation includes data read / write traversal operation, data comparison operation and bit operation. Since the operation corresponding to the custom instruction code is a combination operation corresponding to a series of conventional instruction codes, the processor can read the custom instruction code once, and there is no need to read the conventional instruction code corresponding to each operation separately, which reduces the number of times the processor reads the instruction. Moreover, the present application pre-decodes the custom instruction code once, and the operation corresponding to the custom instruction code can be executed, and there is no need to pre-decode each conventional instruction code in turn as in the prior art, which reduces the operation of the processor pre-decoding. Therefore, for a custom instruction code, the present application only needs to perform a read and pre-decode operation once, which can reduce the burden of the processor caused by multiple read operations and pre-decode operations, and improve the operating efficiency of the processor. At the same time, since one custom script can usually implement the functions of multiple conventional scripts, using a custom script set can save code space. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A flowchart of an operation method of a custom instruction code provided by an embodiment of the present application; Figure 2 A schematic diagram of an instruction format provided for one embodiment of the present application; Figure 3 A schematic diagram of the structure of an operating device for a custom instruction code provided in one embodiment of the present application; Figure 4 A schematic diagram of the computer device structure provided for one embodiment of the present application. DETAILED DESCRIPTION

[0034] RISC-V is an open source instruction set architecture. When a processor based on the RISC-V instruction set architecture needs to perform a certain operation, it will read the instruction code corresponding to the operation in the RISC-V instruction set in advance, then decode the instruction code to obtain the execution information corresponding to the instruction code, and then execute the operation based on the execution information.

[0035] In the prior art, each conventional instruction code in the RISC-V instruction set often corresponds to an operation. When multiple operations need to be performed, the processor often needs to read the corresponding instruction codes separately.

[0036] However, in implementing some application requirements that require executing multiple operations, the processor often reads multiple instruction codes in sequence and decodes each instruction code separately. Multiple reading and decoding operations increase the burden on the processor and reduce the processor's operating efficiency.

[0037] For some chips that are used in small-area, low-power and low-cost scenarios, their memory space is usually limited. When it is necessary to implement some more complex operations, it is usually necessary to use more conventional instruction code combinations in the program code. This will take up more memory space and cause the processor to be unable to support more complex operations at the same time.

[0038] In the process of implementing this application, the inventors discovered that each regular instruction code in the RISC-V instruction set often corresponds to an operation. In implementing some application requirements that require the execution of multiple operations, the processor often needs to read multiple instruction codes in sequence and decode each instruction code separately. Multiple reading and decoding operations will increase the burden on the processor and reduce the processor's operating efficiency.

[0039] In view of the above problems, an operation method of a custom instruction code is provided in an embodiment of the present application. The method designs feasible conventional instruction code operation combinations according to different multi-operation specific application scenario requirements, and defines these conventional operation combinations as different custom instruction codes. Afterwards, it is detected whether to execute the preset operation. When the preset operation needs to be executed, the custom instruction code corresponding to the preset operation is obtained in the custom instruction code set, and the operation corresponding to the custom instruction code is executed, wherein the preset operation includes a data read / write traversal operation, a data comparison operation and a bit operation. Since the operation corresponding to each custom instruction code is a combination operation corresponding to a series of conventional instruction codes, the processor can read the custom instruction code once, and does not need to read the conventional instruction code corresponding to each operation separately, thereby reducing the number of times the processor reads instructions. Moreover, the present application performs a pre-decoding of the custom instruction code once, and the processor can obtain the operation information corresponding to the custom instruction code, and does not need to perform a pre-decoding of each conventional instruction code in turn as in the prior art, thereby reducing the operation of the processor pre-decoding. Therefore, for a custom instruction code, the present application only needs to perform a read and pre-decoding operation once, which can reduce the burden of the processor caused by multiple read operations and pre-decoding operations, and improve the operating efficiency of the processor. At the same time, since one custom instruction code can usually complete a combination of operations corresponding to a series of conventional instruction codes, compared with storing a series of conventional instruction codes, storing only the custom instruction code can further save code space.

[0040] The embodiment of the present application provides an operation method of a custom instruction code. The execution subject of the method is a processor in any device, which can reduce the burden of the processor caused by multiple reading operations and decoding operations, improve the operation efficiency of the processor, and at the same time, since a custom instruction code can usually realize the functions of multiple conventional instruction codes, the use of a custom instruction code set can save code space. Figure 1 ,include: Step 101: Detect whether to execute a preset operation.

[0041] Among them, the preset operations include data read / write traversal operations, data comparison operations and bit operations.

[0042] Before executing this step, the embodiment of the present application finds some operations that can be executed in combination among all the operations corresponding to the conventional instruction codes, and edits the combined operations to obtain custom instruction codes, and then assembles the custom instruction codes into a custom set.

[0043] There are four basic instruction formats officially specified by RISC-V. The specific formats are as follows: Figure 2As shown, the instruction format I-type that supports the target register (rd), source register (rs1) and immediate value (imm) at the same time is used as the instruction format described later, wherein the total bit width of the instruction format I-type is 32 bits, and the rs1 field in the I-type instruction format is used to store the index value of the source register, which is used to find the source register, and the rd field is used to store the index value of the target register, which is used to find the target register. These two index fields need to occupy 5 bits respectively. The imm field is used to store the immediate value, the opcode field is used to store the operation code, and the funct3 field is used to store the function field.

[0044] like Figure 2 For some data traversal operations, load single-byte signed data from the address specified in the source register rs1 to the target register rd, and update the data in the source register rs1 to the sum of the data in the source register rs1 and the data in imm. Name the custom instruction code xl.lb rd, imm(rs1). Load single-byte unsigned data from the address specified in the source register rs1 to the target register rd, and update the data in the source register rs1 to the sum of the data in the source register rs1 and the data in imm. Name the custom instruction code xl.lbu rd, imm(rs1). Load double-byte signed data from the address specified in the source register rs1 to the target register rd, and update the data in the source register rs1 to the sum of the data in the source register rs1 and the data in imm. Name the custom instruction code xl.lh rd, imm(rs1). Load two-byte unsigned data from the address specified in the source register rs1 to the destination register rd, and update the data in the source register rs1 to the sum of the data in the source register rs1 and the data in imm. Name the custom instruction code xl.lhu rd, imm(rs1). Load four-byte signed data from the address specified in the source register rs1 to the destination register rd, and update the data in the source register rs1 to the sum of the data in the source register rs1 and the data in imm. Name the custom instruction code xl.lw rd, imm(rs1). Load four-byte unsigned data from the address specified in the source register rs1 to the destination register rd, and update the data in the source register rs1 to the sum of the data in the source register rs1 and the data in imm. Name the custom instruction code xl.lwu rd, imm(rs1).

[0045] In addition, in the above operation instruction format, the bit width of the immediate value is 12 bits. In the case of word alignment (the lowest 2 bits of imm are fixed to 0), its addressing range is -8192 to 8192. In order to meet the demand for a larger addressing range in some cases, the index value of the source register rs1 of the custom instruction code xl.lgp.wu instruction can be fixed to GP in hardware, so there is no need to specify the rs1 field in the instruction code, which can save 5 bits to expand the bit width occupied by the immediate value field. Therefore, the bit width of the immediate value (imm) of such an instruction can be as high as 17 bits, and in the case of word alignment (the lowest 2 bits of imm are fixed to 0), a larger memory access addressing range is achieved.

[0046] Further, when the index value of the source register rs1 is fixed to GP, the target address can also be obtained according to the base address indicated in the GP register and the immediate number, and the specific steps are: determine the number of left shifts according to the number of bytes of the loaded data; based on the number of left shifts, perform a left shift operation on the immediate number to obtain the immediate number after the left shift; add the immediate number after the left shift and the base address indicated by the GP register to obtain the target address. According to the base address indicated in the GP register and the immediate number, the target address is obtained, and a single-byte unsigned data is loaded from the target address to the target register rd, and the custom instruction code is named xl.lgp.b rd, imm. According to the base address indicated in the GP register and the immediate number, the target address is obtained. And a single-byte signed data is loaded from the target address to the target register rd, and the custom instruction code is named xl.lgp.b rd, imm. According to the base address indicated in the GP register and the immediate number, the target address is obtained. And load double-byte signed data from the target address into the target register rd, and name the custom instruction code xl.lgp.h rd, imm. According to the base address indicated in the GP register and the immediate number, the target address is obtained. And load double-byte unsigned data from the target address into the target register rd, and name the custom instruction code xl.lgp.hu rd, imm. According to the base address indicated in the GP register and the immediate number, the target address is obtained. And load four-byte signed data from the target address into the target register rd, and name the custom instruction code xl.lgp.w rd, imm. According to the base address indicated in the GP register and the immediate number, the target address is obtained. And load four-byte unsigned data from the target address into the target register rd, and name the custom instruction code xl.lgp.wu rd, imm. According to the base address indicated in the GP register and the immediate number, the target address is obtained. And load eight bytes of signed data from the target address into the target register rd, and name the custom instruction code xl.lgp.d rd, imm.

[0047] In the above instruction format, the rs2 field can also be included. The rs2 field can be used to store the index of the source register, can be used to store an immediate value, and can be set according to actual needs. When the rs2 field is used to store the index of the source register, the single-byte data in the source register rs2 is stored in the base address in the source register rs1, and the data in rs1 is updated to the sum of the data in rs1 and the data in imm, and the custom instruction code is named xl.sb rs2, imm(rs1). The double-byte data in the source register rs2 is stored in the base address in the source register rs1, and the data in rs1 is updated to the sum of the data in rs1 and the data in imm, and the custom instruction code is named xl.sh rs2, imm(rs1). The four-byte data in the source register rs2 is stored in the base address in the source register rs1, and the data in rs1 is updated to the sum of the data in rs1 and the data in imm, and the custom instruction code is named xl.sw rs2, imm(rs1). Store the eight-byte data in the source register rs2 to the base address in the source register rs1, and update the data in rs1 to the sum of the data in rs1 and the data in imm. Name the custom instruction code xl.sd rs2, imm(rs1).

[0048] Store the single-byte data in the source register rs2 to the base address in the source register rs1, and update the data in rs1 to the sum of the data in rs1 and the data in imm, and save it. Name the custom instruction code xl.sb rs2,imm(rs1). Store the double-byte data in the source register rs2 to the base address in the source register rs1, and update the data in rs1 to the sum of the data in rs1 and the data in imm, and save it. Name the custom instruction code xl.fsh rs2,imm(rs1). Store the four-byte data in the source register rs2 to the base address in the source register rs1, and update the data in rs1 to the sum of the data in rs1 and the data in imm, and save it. Name the custom instruction code xl.sw rs2,imm(rs1). Store the eight-byte data in the source register rs2 to the base address in the source register rs1, and update the data in rs1 to the sum of the data in rs1 and the data in imm, and save it. Name the custom instruction code xl.fsd rs2,imm(rs1).

[0049] Step 102: When a preset operation needs to be executed, a custom instruction code corresponding to the preset operation is obtained from the custom instruction code set.

[0050] The operation corresponding to the custom instruction code is a combination of operations corresponding to a series of conventional instruction codes. The combination of operations corresponding to a series of conventional instruction codes can be operations executed sequentially by the processor, for example, a data judgment operation and a subsequent data processing operation in a data comparison process, a data loading operation and a subsequent address update operation in a data read traversal process.

[0051] Since the corresponding relationship between the custom instruction code and the microinstruction combination is predefined in the processor, when the processor performs a pre-decoding operation on the custom instruction code, the corresponding microinstruction combination can be obtained based on the above corresponding relationship and the custom instruction code to be decoded. Afterwards, when multiple microinstructions are obtained, the processor can output them to the execution unit according to these microinstructions. In this step, the acquisition unit implements the above-mentioned similar operations, thereby realizing the pre-decoding and splitting operation on the custom instruction code.

[0052] Step 103: Execute the operation corresponding to the custom instruction code.

[0053] When the execution unit receives multiple microinstructions sent from the above acquisition unit. The execution unit will first decode these microinstructions, and after decoding, it will obtain information such as instruction type, instruction operands and destination register. Then, according to the instruction type, the operands are input into the corresponding execution subunit for execution. After the instruction is executed, for instructions that need to be written back, the processor will write the operation results back to the destination register. In this step, the execution unit implements similar operations as above, and then realizes the decoding, execution and write-back operations of the microinstructions after the above custom instruction code is split.

[0054] Further, when the preset operation is a data read traversal operation, the type of the first operand is a base register, the type of the first operand is a base register, the first operand is a base address indicated by the base register, and the type of the second operand is an immediate number, and the specific steps for executing the operation corresponding to the custom instruction code are: determining the target register according to the data bits corresponding to the target register in the custom instruction code; obtaining the data to be loaded from the base address, and loading the data to be loaded into the target register; obtaining a base address update value according to the base address and the second operand; and updating the base address indicated by the base register based on the base address update value.

[0055] The first operand is the value stored in the register corresponding to the rs1 domain, and the second operand is the data in the imm domain.

[0056] In this step, when the preset operation is a data read traversal operation, the custom instruction code at least includes a target register, a first operand, and a second operand. When the custom instruction code is executed, the corresponding target register is found according to the data bit corresponding to the target register in the custom instruction code; the data to be loaded is obtained from the base address, and the data to be loaded is loaded into the target register to read the data; the base address update value is obtained according to the base address and the second operand; based on the base address update value, the base address is updated to read the next data based on the updated base address.

[0057] For example, load single-byte signed data from the base address and update the base address to the sum of the base address and the second operand. Load single-byte unsigned data from the base address and update the base address to the sum of the base address and the second operand. Load double-byte signed data from the base address and update the base address to the sum of the base address and the second operand. Load double-byte unsigned data from the base address and update the base address to the sum of the base address and the second operand. Load four-byte signed data from the base address and update the base address to the sum of the base address and the second operand. Load four-byte unsigned data from the base address and update the base address to the sum of the base address and the second operand. Load 8-byte signed data from the base address and update the base address to the sum of the base address and the second operand. Load 8-byte unsigned data from the base address and update the base address to the sum of the base address and the second operand.

[0058] Furthermore, when the preset operation is a data write traversal operation, the type of the first operand is a base register, the first operand is the base address indicated by the base register, the type of the second operand is a source register, and the second operand is the value stored in the source register. Based on this, the specific steps of executing the operation corresponding to the custom instruction code include: obtaining the third operand in the custom instruction code, the type of the third operand is an immediate number; storing the second operand in the base address indicated by the base register; obtaining a base address update value according to the base address indicated by the base register and the third operand; and updating the base address indicated by the base register based on the base address update value.

[0059] Among them, the first operand is the value stored in the register corresponding to the rs1 domain, the second operand is the value stored in the register corresponding to the rs2 domain, and the third operand is the data in the imm domain.

[0060] The address updating step involved in this step is similar to the above-mentioned address updating step and is not limited here.

[0061] For example, read 2 bytes of signed data from the second operand, save it in the base address, update the base address to the base address and the second operand and save it in the base address register. Read 2 bytes of unsigned data from the second operand, save it in the base address, update the base address to the base address and the second operand and save it in the base address register. Read 4 bytes of signed data from the second operand, save it in the base address, update the base address to the sum of the base address and the second operand, and save it in the base address register. Read 4 bytes of unsigned data from the second operand, save it in the base address, update the base address to the sum of the base address and the second operand, and save it in the base address register. Read 8 bytes of signed data from the second operand, save it in the base address, update the base address to the sum of the base address and the second operand, and save it in the base address register. Read 8 bytes of unsigned data from the second operand, save it in the base address, update the base address to the sum of the base address and the second operand, and save it in the base address register.

[0062] The base register may be a floating-point register.

[0063] Furthermore, when the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is the value in the source register, and the type of the second operand is an immediate number, and the specific steps for executing the operation corresponding to the custom instruction code are: obtain the third operand in the custom instruction code, and the type of the third operand is an offset; compare the first operand with the second operand to obtain a comparison result; add the current address of the custom instruction code and the third operand to obtain a preset target address; when the comparison result is equal, jump to the preset target address to obtain the instruction code; when the comparison result is unequal, obtain the next instruction code of the custom instruction code.

[0064] The first operand is the value stored in the register corresponding to the rs1 field. The imm field is divided into the cimm field and the ofset field in the instruction code to store immediate values. The second operand is the data in the cimm field in the instruction code. The third operand is the data in the ofset field.

[0065] For example, compare rs1 with the cimm immediate value. If they are equal, jump to the current PC+ofset for execution. If they are not equal, get the next instruction code to be executed.

[0066] Furthermore, when the preset operation is a data comparison operation, the type of the first operand is an immediate number, and the type of the second operand is an immediate number; the execution steps of the operation corresponding to the custom instruction code are: determining the target register according to the data bits corresponding to the target register in the custom instruction code; comparing the first operand and the second operand to obtain a comparison result; when the comparison result is less than or equal to, writing 1 to the target register; when the comparison result is greater than, writing 0 to the target register.

[0067] Two imm fields are set in the instruction code to store immediate values. The second operand is the data in the imm1 field in the instruction code. The third operand is the data in the imm2 field.

[0068] For example, compare rs1 and rs2, if rs1 is less than or equal to rs2 (signed comparison), write 1 to the destination register, otherwise write 0. Compare rs1 and rs2, if rs1 is less than or equal to rs2 (unsigned comparison), write 1 to the destination register, otherwise write 0.

[0069] Furthermore, when the preset operation is a data comparison operation, the type of the first operand is a source register, and the first operand is the value stored in the source register; the type of the second operand is a source register, and the second operand is the value stored in the source register; the execution steps of the operation corresponding to the custom instruction code are: in the custom instruction code, obtain the third operand, and the type of the third operand is an immediate number; add the second operand and the preset value to obtain the sum of the two; compare the sum with the first operand; when the two are not equal, jump to the preset operation and save the sum to the first source register; when the two are not equal, obtain the next instruction of the custom instruction code.

[0070] Among them, the first operand is the value stored in the register corresponding to the rs1 field, the second operand is the value stored in the register corresponding to the rs2 field, and the third operand is the data in the imm field in the instruction code.

[0071] Furthermore, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is the value in the source register, and the type of the second operand is an immediate number; the specific steps for executing the operation corresponding to the custom instruction code are: determining the target register according to the data bit corresponding to the target register in the custom instruction code, obtaining the third operand in the custom instruction code, and the type of the third operand is an immediate number; determining the start interception bit and the end interception bit according to the second operand and the third operand; intercepting the first operand according to the start interception bit and the end interception bit to obtain intercepted data; performing unsigned bit extension or sign bit extension on the intercepted data to obtain extended data; storing the extended data in the target register.

[0072] The first operand is the value stored in the register corresponding to the rs1 domain. The imm domain is divided into the uimm2 domain and the uimm3 domain in the instruction code to store immediate values. The second operand is the data in the uimm2 domain in the instruction code. The third operand is the data in the uimm3 domain.

[0073] For example, the data between [uimm3+uimm2-1:uimm2] is intercepted from rs1, and then the sign bit is extended and saved to rd. The data between [rs2[9:5]+rs2[4:0]-1: rs2[4:0]] is intercepted from rs1, and then the sign bit is extended and saved to rd. The data between [uimm3+uimm2-1:uimm2] is intercepted from rs1, and then the unsigned bit is extended and saved to rd. The data between [rs2[9:5]+rs2[4:0]-1: rs2[4:0] is intercepted from rs1, and then the unsigned bit is extended and saved to rd.

[0074] Furthermore, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is the value in the source register, and the type of the second operand is an immediate number; the specific execution steps of executing the operation corresponding to the custom instruction code are: determining the target register according to the data bits corresponding to the target register in the custom instruction code; obtaining the data to be modified from the first operand according to the start bit and end bit of the data to be modified; modifying the data to be modified to obtain the modified data; and storing the modified data in the target register.

[0075] The first operand is the value stored in the register corresponding to the rs1 domain. The imm domain is divided into the uimm2 domain and the uimm3 domain in the instruction code to store immediate values. The second operand is the data in the uimm2 domain in the instruction code. The third operand is the data in the uimm3 domain.

[0076] For example, when executing the custom instruction code xl.insert rd, rs1, uimm3, uimm2, the data of the bit [td:bd] in rd is modified to rs1[ts:0], and the other bits in rd remain unchanged. When executing the custom instruction code xl.bset rd,rs1, uimm3, uimm2, the data of the bit [uimm3+uimm2:uimm2] in rs is changed to all 1, and the rest remains unchanged and saved in rd. When executing the custom instruction code xl.bsetr rd, rs1, rs2, the data of the bit [rs2[9:5]+rs2[4:0] : rs2[4:0] in rs1 is modified to all 1, and the rest remains unchanged and saved in rd. When executing the custom instruction code xl.bclr rd, rs1, uimm3, uimm2, the data of the bit [uimm3+uimm2:uimm2] in rs is changed to all 0, and the rest remains unchanged and saved in rd. When executing the custom instruction code xl.bclrr rd, rs1, rs2, the data of the bit [rs2[9:5]+rs2[4:0]:rs2[4:0] in rs1 is changed to all 0, and the rest remains unchanged and saved in rd.

[0077] Furthermore, when the preset operation is a bit operation, the execution steps of executing the operation corresponding to the custom instruction code are: determining the target register according to the data bit corresponding to the target register in the custom instruction code, obtaining a first operand in the custom instruction code, the type of the first operand is a source register, and the first operand is the value in the source register; starting from the most significant bit of the first operand and ending with the least significant bit of the first operand, counting the number of consecutive appearances of its sign bit to obtain statistical data; when the first operand is a preset value, writing the preset value into the target register, otherwise writing statistical data into the target register.

[0078] The first operand is based on the value stored in the register corresponding to the rs1 domain.

[0079] For example, when executing the custom instruction code xl.clb rd, rs1, the number of consecutive bits starting from the MSB of rs1 is counted. If rs1 is 0, 0 is returned to rd, otherwise the number is returned to rd.

[0080] Furthermore, when the preset operation is a bit operation, the execution of the operation corresponding to the custom instruction code includes: determining the target register according to the data bit corresponding to the target register in the custom instruction code, obtaining a first operand in the custom instruction code, wherein the type of the first operand is a source register, and the first operand is the value in the source register; starting from the most significant bit of the source register, determining the preset data bit; when the data of the preset data bit is a preset value, writing the preset value into the target register.

[0081] The first operand is based on the value stored in the register corresponding to the rs1 domain.

[0082] For example, when the custom instruction code xl.fl1 rd, rs1 is executed, starting from the MSB, the position of the last bit1 in rs1 is found. If rs1 is 0, rd is equal to 32 or 64. When the custom instruction code xl.ff1 rd, rs1 is executed, starting from the MSB, the position of the first bit1 in rs1 is found. If rs1 is 0, rd is equal to 32 or 64. For example, when the custom instruction code xl.fl0 rd, rs1 is executed, starting from the MSB, the position of the last bit0 in rs1 is found. If rs1 is 0, rd is equal to 32 or 64. For example, when the custom instruction code xl.ff0 rd, rs1 is executed, starting from the MSB, the position of the first bit0 in rs1 is found. If rs1 is 0, rd is equal to 32 or 64. Among them, MSB is the most significant bit.

[0083] Furthermore, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is the value in the source register, and the type of the second operand is an immediate number; the execution steps of executing the operation corresponding to the custom instruction code according to the first operand and the second operand are: determining the target register according to the data bit corresponding to the target register in the custom instruction code, obtaining a third operand in the custom instruction code, and the type of the third operand is an immediate number; performing a grouping operation on the first operand according to the second operand to obtain grouped data; performing a left shift and flip operation on the grouped data according to the third operand to obtain operated data. The operated data is stored in the target register.

[0084] The first operand is the value stored in the register corresponding to the rs1 domain. The imm domain is divided into the uimm2 domain and the uimm3 domain in the instruction code to store immediate values. The second operand is the data in the uimm2 domain in the instruction code. The third operand is the data in the uimm3 domain.

[0085] For example, when executing the custom instruction code xl.bitrev rd, rs1, uimm3, uimm2, rs1 is bit-flipped according to the specified mode and grouping, where uimm3 specifies the grouping information and uimm2 specifies the number of left shifts before flipping.

[0086] Optionally, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is the value in the source register, and the type of the second operand is an immediate number; the execution steps of executing the operation corresponding to the custom instruction code according to the first operand and the second operand are: determining the target register according to the data bits corresponding to the target register in the custom instruction code; performing sign bit extension on the second operand to obtain an extended immediate number; multiplying the first operand and the extended immediate number to obtain a product result, and saving the product result to the target register.

[0087] The first operand is the value stored in the register corresponding to the rs1 domain, and the second operand is the data in the imm domain.

[0088] For example, when the custom instruction code xl.muli rd, rs1, imm is executed, rs1 is multiplied by imm after the sign bit is extended and saved in rd.

[0089] Optionally, the preset operation also includes a data read operation. When the preset operation is a data read operation, the index value of the base register is GP, the type of the first operand is an immediate number, and the operation corresponding to the custom instruction code is executed, including: determining the number of left shift bits based on the number of bytes of the loaded data; performing a left shift operation on the first operand based on the number of left shift bits to obtain the first operand after the left shift; adding the first operand after the left shift and the base address indicated by the GP register to obtain a target address, and the GP register is determined based on the index value GP; obtaining the data to be loaded from the target address, and loading the data to be loaded into the target register.

[0090] The first operand is the data in the imm domain.

[0091] When the number of bytes of the loaded data is 1-byte unsigned data, the number of left shifts is determined to be 0. When the number of bytes of the loaded data is 2-byte unsigned data, the number of left shifts is determined to be 1. When the number of bytes of the loaded data is 2-byte signed data, the number of left shifts is determined to be 1. When the number of bytes of the loaded data is 4-byte unsigned data, the number of left shifts is determined to be 2. When the number of bytes of the loaded data is 4-byte signed data, the number of left shifts is determined to be 2. When the number of bytes of the loaded data is 8-byte unsigned data, the number of left shifts is determined to be 3. When the number of bytes of the loaded data is 8-byte signed data, the number of left shifts is determined to be 3.

[0092] It should be noted that, in the process of performing a left shift operation on the first operand based on the number of left shifts to obtain the first operand after the left shift, the data bits to be operated can also be selected in the first operand, and then, based on the number of left shifts, the data bits to be operated are left shifted to obtain the first operand after the left shift. For example, the data bits corresponding to the 0th to the 15th bits in the first operand are used as the data bits to be operated. The data bits corresponding to the 3rd to the 16th bits in the first operand are used as the data bits to be operated.

[0093] After determining the first operand after the left shift, the first operand after the left shift and the base address indicated by the GP register are added to obtain a target address; the data to be loaded is obtained from the target address, and the data to be loaded is loaded into the target register.

[0094] Optionally, the preset operation also includes a data write operation. When the preset operation is a data write operation, the index value of the base register is GP, the type of the first operand is a source register, the first operand is the value stored in the source register, and the type of the second operand is an immediate number. The specific steps for executing the operation corresponding to the custom instruction code are: determining the number of left shift bits based on the number of bytes of the stored data; performing a left shift operation on the second operand based on the number of left shift bits to obtain the second operand after the left shift; adding the second operand after the left shift and the base address indicated by the GP register to obtain the target address, and the GP register is determined based on the index value GP; and storing the first operand in the target address.

[0095] The first operand is a value stored in a register corresponding to the rs2 domain, and the second operand is data in the imm domain.

[0096] The moving operations involved in this step are similar to the above-mentioned moving operations and are not described in detail here.

[0097] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0098] See also Figure 3 An embodiment of the present application provides an operating device for a custom instruction code, comprising: A detection unit 301 is used to detect whether to perform a preset operation, wherein the preset operation includes a data read / write traversal operation, a data comparison operation, and a bit operation; An acquisition unit 302 is used to acquire, when the preset operation needs to be executed, a custom instruction code corresponding to the preset operation in the custom instruction code set, where the operation corresponding to the custom instruction code is a combination of operations corresponding to a series of conventional instruction codes; An execution unit 303 is used to execute the operation corresponding to the custom instruction code; Wherein, when the preset operation is a data read traversal operation, the type of the first operand is a base register, the first operand is a base address indicated by the base register, and the type of the second operand is an immediate number, and the execution unit 303 is used to: determine the target register according to the data bit corresponding to the target register in the custom instruction code; obtain the data to be loaded from the base address, and load the data to be loaded into the target register; obtain a base address update value according to the base address and the second operand; and update the base address indicated by the base register based on the base address update value; When the preset operation is a data write traversal operation, the type of the first operand is a base register, the first operand is the base address indicated by the base register, the type of the second operand is a source register, the second operand is the value stored in the source register, and the execution unit 303 is used to: obtain the third operand in the custom instruction code, the type of the third operand is an immediate number; store the second operand in the base address indicated by the base register; obtain a base address update value according to the base address indicated by the base register and the third operand; and update the base address indicated by the base register based on the base address update value.

[0099] Optionally, the preset operation further includes a data read operation. When the preset operation is a data read operation, the index value of the base register is GP, the type of the first operand is an immediate number, and the execution unit 303 is used to: Determine the number of left shifts according to the number of bytes of the loaded data; Based on the number of left shifts, perform a left shift operation on the first operand to obtain a first operand after left shift; Adding the first operand after the left shift and a base address indicated by a GP register to obtain a target address, wherein the GP register is determined based on an index value GP; The data to be loaded is obtained from the target address, and the data to be loaded is loaded into the target register.

[0100] Optionally, the preset operation further includes a data write operation. When the preset operation is a data write operation, when the index value of the base register is GP, the type of the first operand is a source register, the first operand is a value stored in the source register, and the type of the second operand is an immediate number, the execution unit 303 is used to: Determine the number of left shifts according to the number of bytes of the stored data; Based on the number of left shifts, performing a left shift operation on the second operand to obtain a left-shifted second operand; Adding the second operand after the left shift and the base address indicated by the GP register to obtain a target address, the GP register being determined based on the index value GP; The first operand is stored in the target address.

[0101] Optionally, when the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value. The execution unit 303 is used to: Obtain a third operand in the custom instruction code, where the type of the third operand is an offset; Comparing the first operand with the second operand to obtain a comparison result; Adding the current address of the custom instruction code and the third operand to obtain a preset target address; When the comparison result is equal, jump to the preset target address to obtain the instruction code; When the comparison result is unequal, the next instruction code of the custom instruction code is obtained.

[0102] Optionally, when the preset operation is a data comparison operation, the type of the first operand is an immediate number, and the type of the second operand is an immediate number; The execution unit 303 is used to: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Comparing the first operand with the second operand to obtain a comparison result; When the comparison result is less than or equal to, writing 1 into the target register; When the comparison result is greater than, 0 is written into the target register.

[0103] Optionally, when the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is a value stored in the source register, the type of the second operand is a source register, and the second operand is a value stored in the source register; The execution unit 303 is used to: In the custom instruction code, a third operand is obtained, wherein the type of the third operand is an immediate number; Adding the second operand and the preset value to obtain a sum of the two; comparing the sum to the first operand; When the two are not equal, jump to the preset operation and save the sum in the source register; When the two are not equal, the next instruction code of the custom instruction code is obtained.

[0104] Optionally, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The execution unit 303 is used to: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a third operand in the custom instruction code, and the type of the third operand is an immediate number; Determine a start interception position and an end interception position according to the second operand and the third operand; According to the start interception bit and the end interception bit, intercepting the first operand to obtain intercepted data; Performing unsigned bit extension or signed bit extension on the intercepted data to obtain extended data; The extended data is stored in the target register.

[0105] Optionally, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The execution unit 303 is used to: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Obtain the data to be modified from the first operand according to the start bit and the end bit of the data to be modified; Modifying the data to be modified to obtain modified data; The modified data is stored in the target register.

[0106] Optionally, when the preset operation is a bit operation, the execution unit 303 is configured to: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a first operand in the custom instruction code, the type of the first operand is a source register, and the first operand is a value in the source register; Starting from the most significant bit of the first operand and ending with the least significant bit of the first operand, counting the number of times the sign bit appears consecutively to obtain statistical data; When the first operand is a preset value, the preset value is written into the target register; otherwise, statistical data is written into the target register.

[0107] Optionally, when the preset operation is a bit operation, the execution unit 303 is configured to: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a first operand in the custom instruction code, wherein the type of the first operand is a source register, and the first operand is a value in the source register; Starting from the most significant bit of the source register, determining a preset data bit; When the data of the preset data bit is a preset value, the preset value is written into the target register.

[0108] Optionally, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The execution unit 303 is used to: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a third operand in the custom instruction code, and the type of the third operand is an immediate number; According to the second operand, performing a grouping operation on the first operand to obtain grouped data; According to the third operand, performing left shift and flip operations on the grouped data to obtain operated data; The post-operation data is stored in the target register.

[0109] Optionally, when the preset operation is a bit operation, The type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The execution unit 303 is used to: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Performing sign bit extension on the second operand to obtain an extended immediate value; The first operand and the extended immediate number are multiplied to obtain a product result, and the product result is saved in the target register.

[0110] For the specific definition of the operating device of the above-mentioned custom instruction code, please refer to the definition of the operating method of the custom instruction code in the above text, which will not be repeated here. Each module in the operating device of the above-mentioned custom instruction code can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0111] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 4 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, an operating method of a custom instruction code as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the operating method of the custom instruction code as described above is implemented.

[0112] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above-mentioned method for operating a custom instruction code can be implemented.

[0113] Those skilled in the art will appreciate that the embodiments of the present application may be provided as an operating method, system, or computer program product of a custom instruction code. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0114] The present application is described with reference to the flowcharts and / or block diagrams of the operating methods, devices (systems), and computer program products of the custom instruction codes according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0115] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0116] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0117] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0118] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for operating a custom instruction code, characterized in that: include: Detecting whether to execute a preset operation, wherein the preset operation includes a data read / write traversal operation, a data comparison operation, and a bit operation; When the preset operation needs to be executed, the custom instruction code corresponding to the preset operation is obtained from the custom instruction code set, and the operation corresponding to the custom instruction code is a combination of operations corresponding to a series of conventional instruction codes; Execute the operation corresponding to the custom instruction code; Wherein, when the preset operation is a data read traversal operation, the type of the first operand is a base register, the first operand is a base address indicated by the base register, and the type of the second operand is an immediate number, and the operation corresponding to the execution of the custom instruction code includes: determining the target register according to the data bit corresponding to the target register in the custom instruction code; obtaining the data to be loaded from the base address, and loading the data to be loaded into the target register; obtaining a base address update value according to the base address and the second operand; and updating the base address indicated by the base register based on the base address update value; When the preset operation is a data write traversal operation, the type of the first operand is a base register, the first operand is the base address indicated by the base register, the type of the second operand is a source register, the second operand is the value stored in the source register, and the execution of the operation corresponding to the custom instruction code includes: obtaining the third operand in the custom instruction code, the type of the third operand is an immediate number; storing the second operand in the base address indicated by the base register; obtaining a base address update value according to the base address indicated by the base register and the third operand; and updating the base address indicated by the base register based on the base address update value.

2. The method according to claim 1, characterized in that: The preset operation also includes a data read operation. When the preset operation is a data read operation, the index value of the base register is GP, the type of the first operand is an immediate number, and the operation corresponding to the execution of the custom instruction code includes: Determine the number of left shifts according to the number of bytes of the loaded data; Based on the number of left shifts, perform a left shift operation on the first operand to obtain a first operand after left shift; Adding the first operand after the left shift and a base address indicated by a GP register to obtain a target address, wherein the GP register is determined based on an index value GP; The data to be loaded is obtained from the target address, and the data to be loaded is loaded into the target register.

3. The method according to claim 1, characterized in that: The preset operation also includes a data write operation. When the preset operation is a data write operation, when the index value of the base register is GP, the type of the first operand is a source register, the first operand is a value stored in the source register, and the type of the second operand is an immediate number, the operation corresponding to the execution of the custom instruction code includes: Determine the number of left shifts according to the number of bytes of the stored data; Based on the number of left shifts, performing a left shift operation on the second operand to obtain a left-shifted second operand; Adding the second operand after the left shift and the base address indicated by the GP register to obtain a target address, the GP register being determined based on the index value GP; The first operand is stored in the target address.

4. The method according to claim 1, characterized in that: When the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value. The operation corresponding to executing the custom instruction code includes: Obtain a third operand in the custom instruction code, where the type of the third operand is an offset; Comparing the first operand with the second operand to obtain a comparison result; Adding the current address of the custom instruction code and the third operand to obtain a preset target address; When the comparison result is equal, jump to the preset target address to obtain the instruction code; When the comparison result is unequal, the next instruction code of the custom instruction code is obtained.

5. The method according to claim 1, characterized in that: When the preset operation is a data comparison operation, the type of the first operand is an immediate number, and the type of the second operand is an immediate number; The operation corresponding to executing the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Comparing the first operand with the second operand to obtain a comparison result; When the comparison result is less than or equal to, writing 1 into the target register; When the comparison result is greater than, 0 is written into the target register.

6. The method according to claim 1, characterized in that: When the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is a value stored in the source register, the type of the second operand is a source register, and the second operand is a value stored in the source register; The operation corresponding to executing the custom instruction code includes: In the custom instruction code, a third operand is obtained, wherein the type of the third operand is an immediate number; Adding the second operand and the preset value to obtain a sum of the two; comparing the sum to the first operand; When the two are not equal, jump to the preset operation and save the sum in the source register; When the two are not equal, the next instruction code of the custom instruction code is obtained.

7. The method according to claim 1, characterized in that: When the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The operation corresponding to executing the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a third operand in the custom instruction code, and the type of the third operand is an immediate number; Determine a start interception position and an end interception position according to the second operand and the third operand; According to the start interception bit and the end interception bit, intercepting the first operand to obtain intercepted data; Performing unsigned bit extension or signed bit extension on the intercepted data to obtain extended data; The extended data is stored in the target register.

8. The method according to claim 1, characterized in that: When the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The operation corresponding to executing the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Obtain the data to be modified from the first operand according to the start bit and the end bit of the data to be modified; Modifying the data to be modified to obtain modified data; The modified data is stored in the target register.

9. The method according to claim 1, characterized in that: When the preset operation is a bit operation, the operation corresponding to the execution of the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a first operand in the custom instruction code, the type of the first operand is a source register, and the first operand is a value in the source register; Starting from the most significant bit of the first operand and ending with the least significant bit of the first operand, counting the number of times the sign bit appears consecutively to obtain statistical data; When the first operand is a preset value, the preset value is written into the target register; otherwise, statistical data is written into the target register.

10. The method according to claim 1, characterized in that: When the preset operation is a bit operation, the operation corresponding to the execution of the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a first operand in the custom instruction code, wherein the type of the first operand is a source register, and the first operand is a value in the source register; Starting from the most significant bit of the source register, determining a preset data bit; When the data of the preset data bit is a preset value, the preset value is written into the target register.

11. The method according to claim 1, characterized in that: When the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value; The operation corresponding to executing the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a third operand in the custom instruction code, and the type of the third operand is an immediate number; According to the second operand, performing a grouping operation on the first operand to obtain grouped data; According to the third operand, performing left shift and flip operations on the grouped data to obtain operated data; The post-operation data is stored in the target register.

12. The method according to claim 1, characterized in that: When the preset operation is a bit operation, The type of the first operand is a source register, the first operand is the value in the source register, and the type of the second operand is an immediate value; The operation corresponding to executing the custom instruction code includes: Determine the target register according to the data bit corresponding to the target register in the custom instruction code; Performing sign bit extension on the second operand to obtain an extended immediate value; The first operand and the extended immediate number are multiplied to obtain a product result, and the product result is saved in the target register.

13. An operating device with a custom instruction code, characterized in that: include: A detection unit, used to detect whether to perform a preset operation, wherein the preset operation includes a data read / write traversal operation, a data comparison operation, and a bit operation; An acquisition unit, used for acquiring, when the preset operation needs to be executed, a custom instruction code corresponding to the preset operation in the custom instruction code set, wherein the operation corresponding to the custom instruction code is a combination of operations corresponding to a series of conventional instruction codes; An execution unit is used to execute the operation corresponding to the custom instruction code, wherein, when the preset operation is a data read traversal operation, the type of the first operand is a base register, the first operand is a base address indicated by the base register, and the type of the second operand is an immediate number, and the execution of the operation corresponding to the custom instruction code includes: determining the target register according to the data bit corresponding to the target register in the custom instruction code; obtaining the data to be loaded from the base address, and loading the data to be loaded into the target register; obtaining a base address update value according to the base address and the second operand; and performing an operation on the base address indicated by the base register based on the base address update value. Update; when the preset operation is a data write traversal operation, the type of the first operand is a base register, the first operand is the base address indicated by the base register, the type of the second operand is a source register, the second operand is the value stored in the source register, and the operation corresponding to the execution of the custom instruction code includes: obtaining the third operand in the custom instruction code, the type of the third operand is an immediate number; storing the second operand in the base address indicated by the base register; obtaining a base address update value according to the base address indicated by the base register and the third operand; and updating the base address indicated by the base register based on the base address update value.

14. A computer device comprising: The method comprises a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the method according to any one of claims 1 to 12 when executing the computer program.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 12 are implemented.

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