Address information verification method and device, equipment and storage medium

Abstract

The invention discloses an address information verification method and device, equipment and a storage medium, and belongs to the technical field of bus transmission. The method is executed by electronic equipment, bus connection is established between the electronic equipment and at least two pieces of expansion equipment, and the method comprises the steps that a request address of a service request is acquired, and the service request is used for indicating a service processing mode of first expansion equipment; base address information of the first expansion device and a first numerical value corresponding to the first expansion device are obtained, the base address information is used for indicating the initial storage position of a base address register of the first expansion device, the high bit in the first numerical value is a first value, and the low bit in the first numerical value is a second value; performing AND gate calculation based on the first numerical value and the request address to obtain a second numerical value; and in response to the fact that the second numerical value is the same as the base address information, sending a service request to the first expansion equipment corresponding to the base address information.

Description

Technical Field

[0001] The present application relates to the field of bus transmission technology, and in particular to a method, device, equipment and storage medium for verifying address information. Background Art

[0002] The high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCI-Express / PCIE) provides high-speed serial point-to-point dual-channel high-bandwidth transmission.

[0003] In the related art, a data processing unit (DPU) is connected to multiple physical function (PF) devices via PCIE, and an adder is used to compare the request address of a service request with the information of the base address register of the PF device to determine the PF device to which the service request is mapped.

[0004] How to save the computing resources required for verifying the PF device of the business request mapping is an urgent problem to be solved. Summary of the invention

[0005] The present application provides a method, device, equipment and storage medium for verifying address information. The technical solution is as follows:

[0006] According to one aspect of the present application, a method for verifying address information is provided, the method being performed by an electronic device, wherein a bus connection is established between the electronic device and at least two expansion devices, the method comprising:

[0007] Obtaining a request address of a service request, where the service request is used to indicate a service processing mode of the first extension device;

[0008] Acquire base address information of the first expansion device and a first value corresponding to the first expansion device, wherein the base address information is used to indicate a starting storage position of a base address register of the first expansion device, a high-order bit in the first value is a first value, a low-order bit in the first value is a second value, a number of binary digits of the high-order bit is greater than or equal to a maximum number of binary digits of the address length information of the first expansion device, and a number of binary digits of the low-order bit is less than a maximum number of binary digits of the address length information;

[0009] Perform an AND gate calculation based on the first value and the request address to obtain a second value;

[0010] In response to the second value being the same as the base address information, sending the service request to the first extension device corresponding to the base address information.

[0011] According to another aspect of the present application, a device for verifying address information is provided, the device is applied to an electronic device, a bus connection is established between the electronic device and at least two expansion devices, and the device includes:

[0012] An acquisition module, used to acquire a request address of a service request, where the service request is used to indicate a service processing mode of the first extension device;

[0013] The acquisition module is further used to acquire base address information of the first expansion device and a first value corresponding to the first expansion device, the base address information is used to indicate a starting storage position of a base address register of the first expansion device, a high-order bit in the first value is a first value, a low-order bit in the first value is a second value, a number of binary digits of the high-order bit is greater than or equal to a maximum number of binary digits of the address length information of the first expansion device, and a number of binary digits of the low-order bit is less than a maximum number of binary digits of the address length information;

[0014] a processing module, configured to perform an AND gate calculation based on the first value and the request address to obtain a second value;

[0015] The sending module is configured to send the service request to the first extension device corresponding to the base address information in response to the second value being the same as the base address information.

[0016] In an optional design of the present application, the acquisition module is further used for:

[0017] Acquire the address length information of the first expansion device, where the address length information is used to indicate the address space size of the base address register of the first expansion device;

[0018] A binary bit operation is performed based on the address length information to obtain the first value.

[0019] In an optional design of the present application, the acquisition module is further used for:

[0020] Determine the difference between the address length information and the third value as mask information, wherein the mask information is used to determine the binary digit whose binary digit number is less than the maximum binary digit number of the address length information as the first value;

[0021] The mask information is inverted to obtain the first value.

[0022] In an optional design of the present application, the sending module is further used for:

[0023] Calling an equality comparator to compare the second value with the base address information;

[0024] When the second value is equal to the base address information, the service request is sent to the first extension device corresponding to the base address information.

[0025] In an optional design of the present application, the processing module is further used for:

[0026] An AND gate circuit is called to calculate the first value and the request address to obtain the second value.

[0027] In an optional design of the present application, the acquisition module is further used for:

[0028] Acquire an address table of the at least two expansion devices stored in the electronic device, wherein the address table is used to indicate base address register information of at least two expansion devices with which a bus connection is established;

[0029] The base address information and the first value are obtained based on the address table.

[0030] In an optional design of the present application, the acquisition module is further used for:

[0031] Acquire application address spaces of the at least two expansion devices, where the application address spaces are used to indicate the number of binary difference bits between base address registers of the at least two expansion devices;

[0032] Acquire first sub-information in a base address register of any expansion device among the at least two expansion devices, and acquire at least two second sub-information corresponding to the base address registers of the at least two expansion devices in a one-to-one manner;

[0033] Based on the first sub-information and the at least two second sub-information, construct an address table of the at least two expansion devices;

[0034] The first sub-information is the binary bits in the base address register that are greater than or equal to the target bit number, and the second sub-information is the binary bits in the base address register that are less than the target bit number, and the target bit number is determined based on the application address space.

[0035] In an optional design of the present application, the processing module is further used for:

[0036] Determine the product of the number of binary digits corresponding to the application address space and n as a fourth value, where n is greater than 1;

[0037] The target number of digits is determined according to the fourth value, and the target number of digits is greater than or equal to the fourth value.

[0038] In an optional design of the present application, the processing module is further used for:

[0039] Calling a hash algorithm to process the request address to obtain a request hash value corresponding to the service request;

[0040] A hash table corresponding to the at least two expansion devices is obtained, and a target hash value that is the same as the request hash value is searched in the hash table, and there is an association relationship between the target hash value and the first expansion device.

[0041] In an optional design of the present application, the hash table includes a first sub-table and a second sub-table;

[0042] The processing module is also used for:

[0043] Searching for a first sub-hash value in the request hash value based on the first sub-table, where the first sub-hash value is a partial binary bit of the request hash value;

[0044] In the event that a conflict occurs when searching the first sub-hash value in the first sub-table, the target hash value that is the same as the second sub-hash value in the request hash value is obtained based on the search in the second sub-table, where the second sub-hash value is part of the binary bits of the request hash value, and the first sub-hash value and the second sub-hash value have different corresponding binary bit information in the request hash value.

[0045] According to another aspect of the present application, a computer device is provided, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the address information verification method as described above.

[0046] According to another aspect of the present application, a computer-readable storage medium is provided, in which at least one instruction, at least one program, a code set or an instruction set is stored, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the address information verification method as described above.

[0047] According to another aspect of the present application, a computer program product is provided, which includes computer instructions stored in a computer-readable storage medium, and a processor reads and executes the computer instructions from the computer-readable storage medium to implement the address information verification method described above.

[0048] The beneficial effects of the technical solution provided by this application include at least:

[0049] The second value is obtained by AND gate calculation. When the second value and the base address information are the same, a service request is sent to the first expansion device, which reduces the complexity of comparing the request address and the base address information, avoids comparing the request address with the base address information of the first expansion device and limiting the size relationship of the address information through an adder in the related art, simplifies the adder calculation into AND gate calculation, and saves computing resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0051] Figure 1 is a schematic diagram of a computer system provided by an exemplary embodiment of the present application;

[0052] Figure 2 is a schematic diagram of a computer system provided by an exemplary embodiment of the present application;

[0053] Figure 3 is a schematic diagram of a method for verifying address information provided by an exemplary embodiment of the present application;

[0054] Figure 4 is a flow chart of a method for verifying address information provided by an exemplary embodiment of the present application;

[0055] Figure 5 is a flow chart of a method for verifying address information provided by an exemplary embodiment of the present application;

[0056] Figure 6 is a flow chart of a method for verifying address information provided by an exemplary embodiment of the present application;

[0057] Figure 7 is a flow chart of a method for verifying address information provided by an exemplary embodiment of the present application;

[0058] Figure 8 is a flow chart of a method for verifying address information provided by an exemplary embodiment of the present application;

[0059] Fig. 9 is a flow chart of a method for verifying address information provided by an exemplary embodiment of the present application;

[0060] Fig.10 is a schematic diagram of base address register routing provided by an exemplary embodiment of the present application;

[0061] Fig.11 is a schematic diagram of a base address register routing table provided by an exemplary embodiment of the present application;

[0062] Fig.12 is a flow chart of a method for verifying address information provided by an exemplary embodiment of the present application;

[0063] Fig.13 is a structural block diagram of an address information verification device provided by an exemplary embodiment of the present application;

[0064] Fig.14 It is a structural block diagram of a server provided by an exemplary embodiment of the present application.

[0065] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application. DETAILED DESCRIPTION

[0066] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0067] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0068] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0069] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the request address and other information involved in this application are obtained with full authorization.

[0070] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0071] Figure 1 A schematic diagram of a computer system provided by an embodiment of the present application is shown. The computer system can be implemented as a system architecture of an address information verification method. The computer system may include: an electronic device 100 and at least two expansion devices. In this embodiment, the first expansion device 110 and the second expansion device 120 are used as examples for introduction; it can be understood that in different embodiments, more expansion devices may be included, such as hundreds or thousands of expansion devices, and the present application does not limit this.

[0072] The electronic device 100 is an electronic device with data calculation, processing and / or storage capabilities, which can be a terminal or a server, or a processing core in a terminal or a server, such as an independent physical server, a server cluster or a distributed system composed of multiple physical servers, a mobile phone, a tablet computer, a PC (Personal Computer), etc., or a processing core in the above devices, such as a data processor (Data Processing Unit, DPU).

[0073] The first expansion device 110 and the second expansion device 120 may be the same device or different devices, and the present application does not limit the type of expansion device for establishing a bus connection with the electronic device 100. The expansion device may be at least one of a network adapter (NIC), a host bus adapter (HBA), an application specific integrated circuit (ASIC), and a graphics processing unit (GPU).

[0074] The bus connection method between the electronic device 100 and at least two expansion devices can be based on a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCI-Express / PCIE), or can be established through other bus connection methods; exemplary methods include but are not limited to any one of Peripheral Component Interconnect (PCI) and Accelerated Graphics Port (AGP). This application does not limit the bus connection method.

[0075] Next, the establishment of bus connection between electronic devices and expansion devices based on PCIE is introduced.

[0076] Figure 2 A schematic diagram of a computer system provided by an embodiment of the present application is shown. The computer system can be implemented as a system architecture of a method for verifying address information. The computer system is introduced by taking an example of establishing a bus connection between an electronic device and an expansion device based on PCIE, and the expansion device is a system on a chip (System On a Chip, SOC).

[0077] The electronic device includes a first subsystem 210 and a second subsystem 220;

[0078] Specifically, the first subsystem 210 includes a first central processor 212, a root complex 214, and a first memory 216. The root complex 214 also includes a plurality of root ports (RPs). In this embodiment, the root complex 214 includes a first root port 214a and a second root port 214b.

[0079] The second subsystem 220 includes a User Datagram Protocol Server (UPS) 222, a Data Path 224, a Control Path 226, and a Block (blk) / Network / User 228. The data path 224 includes a first PCIE route (pcie_rout) 224a, and the control path 226 includes a second PCIE route (pcie_rout) 226a; a bus connection is established between the second PCIE route 226a and the system on chip 112. The system on chip 112 includes a second central processor 232, a second memory 234, and a processing unit 236. The processing unit 236 parses and processes the transaction layer packets (Transaction Layer Packets, TLP) sent by the second PCIE route 226a to the system on chip 112. Exemplarily, the processing unit is an integrated management unit (Integrated Management Unit, IMU).

[0080] Figure 3 A schematic diagram of a method for verifying address information provided by an exemplary embodiment of the present application is provided.

[0081] In this embodiment, a service request indicating the service processing mode of the first expansion device 320 is carried in a transaction layer packet (Transaction Layer Packets, TLP) 300. The transaction layer packet 300 corresponds to a request address 302, which is used to indicate the address information of the transaction layer packet 300; illustratively, the request address 302 is the same as the base address register (Base Address Register, BAR) of the first expansion device 320, which is 32-bit or 64-bit bit information.

[0082] A hash algorithm is called to process the request address 302 to obtain a request hash value 304 corresponding to the service request; a hash table 310 corresponding to at least two expansion devices is obtained, and a target hash value 312 identical to the request hash value 304 is searched in the hash table 310, and there is an association between the target hash value 312 and the first expansion device 320. Exemplarily, the hash table 310 may include multiple word tables, and the hash algorithm includes a cyclic redundancy check (CRC) algorithm.

[0083] Based on the base address register information of the first expansion device 320, the address length information 322 and the base address information 324 corresponding to the first expansion device 320 are obtained; wherein the address length information 322 and the base address information 324 are obtained by performing binary bit operations on the base address register information. The base address information is used to indicate the starting storage position of the base address register of the first expansion device, and the address length information is used to indicate the address space size of the base address register of the first expansion device.

[0084] The difference between the address length information 322 and the third value 333 is determined as the mask information 322a, and the mask information 322a is used to determine the binary bits that are smaller than the address length information as the first value (for example, the first value is 1); the NOT gate circuit 330a is called to perform an inversion calculation on the mask information 322a to obtain the first value 331. The binary bits in the first value that are greater than or equal to the address length information of the first expansion device are the first value (for example, the first value is 1), and the binary bits that are smaller than the address length information are the second value (for example, the second value is 0).

[0085] The AND gate circuit 330b is called to calculate the first value 331 and the request address 302 to obtain the second value 332. The equal sign comparator constructed by the XOR gate circuit 330c is called to compare the second value with the base address information to obtain a comparison result 340; when the second value and the base address information are equal, for example, when the comparison result 340 is 0, a service request is sent to the first expansion device corresponding to the base address information.

[0086] Next, the address information verification method will be introduced through the following embodiments.

[0087] Figure 4 A flowchart of a method for verifying address information provided by an exemplary embodiment of the present application is shown. The method can be executed by an electronic device. The method includes:

[0088] Step 510: Obtain the request address of the service request;

[0089] Exemplarily, the service request is used to indicate the service processing mode of the first expansion device; Exemplarily, the service processing mode includes but is not limited to calling the first expansion device to obtain, edit, and store data information. This embodiment does not limit the service processing mode. Exemplarily, the request address of the service request is used to indicate the transmission destination address of the service request. In one example, the service request is carried in a transaction layer packet (Transaction Layer Packets, TLP), and the request address of the service request is the address field of the TLP (also called TLP_ADDR).

[0090] Exemplarily, a bus connection is established between the electronic device and at least two expansion devices. As described above, the present application does not limit the manner of establishing the bus connection between the electronic device and the at least two expansion devices.

[0091] Step 520: Acquire base address information of the first expansion device and a first value corresponding to the first expansion device;

[0092] Exemplarily, the base address information is used to indicate the starting storage position of the base address register of the first expansion device, also referred to as ADDR_BASE. Exemplarily, the first expansion device corresponds to one or more base address registers.

[0093] Exemplarily, the first value is a value represented by binary. In one example, the number of bits of the first value is the same as the number of bits of the base address information, such as 32 or 64 bits. The high-order bits in the first value are the first value, and the low-order bits in the first value are the second value; in one example, the first value is 1, and the second value is 0. The number of binary bits of the high-order bits is greater than or equal to the maximum number of binary bits of the address length information of the first expansion device, and the number of binary bits of the low-order bits is less than the maximum number of binary bits of the address length information. Exemplarily, the address length information is used to indicate the address space size of the base address register of the first expansion device.

[0094] Step 530: performing AND gate calculation based on the first value and the request address to obtain a second value;

[0095] Exemplarily, the AND gate calculation of the first value and the request address may be implemented according to a logic circuit or a binary AND gate algorithm, which is not limited in the present application. Correspondingly, the second value is a binary value.

[0096] Step 540: In response to the second value being the same as the base address information, sending a service request to the first extension device corresponding to the base address information;

[0097] Exemplarily, the second value and the base address information being the same can be determined based on a logic circuit or can be obtained through a numerical comparison algorithm, and this application does not limit this. Exemplarily, the service request can be carried in a data packet and sent to the first expansion device, for example, the service request is carried in a transaction layer data packet.

[0098] In summary, the method provided in this embodiment obtains the second value through AND gate calculation, and sends a service request to the first expansion device when the second value and the base address information are the same, thereby reducing the complexity of comparing the request address and the base address information, avoiding the use of an adder to compare the request address and the base address information of the first expansion device and limiting the size relationship of the address information in the related art, simplifying the adder calculation to the AND gate calculation, and saving computing resources.

[0099] Figure 5 A flowchart of a method for verifying address information provided by an exemplary embodiment of the present application is shown. The method can be executed by an electronic device. Figure 4 In the illustrated embodiment, step 520 may be implemented as steps 521, 522, and 524:

[0100] Step 521: Obtain base address information of the first expansion device;

[0101] Exemplarily, the base address information is used to indicate the starting storage position of the base address register of the first expansion device. Exemplarily, the address space of the base address register is a space with the base address information as the starting storage position and the address length information as the address space size.

[0102] Step 522: Obtain address length information of the first expansion device;

[0103] Exemplarily, the address length information is used to indicate the address space size of the base address register of the first expansion device; in one example, the address space size of the base address register is 4KB, and accordingly, the maximum binary digit of the address length information is the twelfth bit (Bit12), the value of the twelfth bit is 1, and the values ​​of the zeroth bit (Bit0) to the eleventh bit (Bit11) are all 0, that is, the address length information is: 1000000000000. Accordingly, in the first value, the high-order bit whose binary digit is greater than or equal to Bit12 is 1, and the low-order bit whose binary digit is less than Bit12 is 0.

[0104] Step 524: performing binary bit operation based on the address length information to obtain a first value;

[0105] Exemplarily, the first value is obtained by binary bit operation, and the binary bit operation includes but is not limited to at least one of AND, OR, XOR, negation, left shift, and right shift. It can be understood that the binary bit operation can be implemented by a logic circuit or by a binary algorithm. The binary bit operation can be performed on multiple binary bits in parallel, or it can be performed on some binary bits based on the address length information. This application does not limit this.

[0106] In an optional implementation, step 524 in this embodiment may be implemented as the following sub-steps:

[0107] Sub-step 24a: determining the difference between the address length information and the third value as mask information;

[0108] Exemplarily, the mask information is a binary value, and in one example, the number of bits of the mask information is the same as the number of bits of the base address information. The mask information is used to determine the binary bits whose binary digits are less than the maximum binary digits of the address length information as the first value; Exemplarily, as described above, the address space size of the base address register is 4KB, and accordingly, the maximum binary digit of the address length information is the twelfth bit (Bit12), and the mask information is used to determine the binary bits whose binary digits are less than Bit12 as the first value, that is, to determine the zeroth bit (Bit0) to the eleventh bit (Bit11) as the first value, and further, the first value is 1.

[0109] It should be noted that the present application does not restrict the address space size of the base address register; in one example, the address space size of the base address register, i.e., the address length information, is not less than 4KB, but the present application does not exclude the situation where the address length information is less than 4KB. Furthermore, the present application does not restrict the address length information of multiple expansion devices connected to the electronic device, and the address length information of different expansion devices can be the same or different.

[0110] Sub-step 24b: performing inversion calculation on the mask information to obtain a first value;

[0111] In one example, the inversion calculation of the mask information is implemented based on a NOT gate circuit; it is understandable that the first value can also be obtained through a binary bit operation or a binary inversion algorithm, which is not limited in this embodiment.

[0112] In summary, the method provided in this embodiment determines the first value by performing binary bit operation on the address length information of the first expansion device, thereby effectively utilizing the address length information, and in the process of determining the first value, reduces the complexity of processing the address length information by inversion calculation; obtains the second value by AND gate calculation, and sends a service request to the first expansion device when the second value and the base address information are the same, thereby reducing the complexity of comparing the request address and the base address information, avoiding the use of an adder to compare the request address and the base address information of the first expansion device and limiting the size relationship of the address information in the related art, simplifying the adder calculation to the AND gate calculation, and saving computing resources.

[0113] Figure 6A flowchart of a method for verifying address information provided by an exemplary embodiment of the present application is shown. The method can be executed by an electronic device. Figure 4 In the illustrated embodiment, step 530 may be implemented as step 532, and step 540 may be implemented as step 542 and step 544:

[0114] Step 532: calling an AND gate circuit to calculate the first value and the request address to obtain a second value;

[0115] Exemplarily, calling an AND gate circuit to calculate the first value and the request address is based on a logic circuit calculating the first value and the request address, and the second value is the base address information of the base address register corresponding to the transmission destination address of the service request extracted from the request address.

[0116] It should be noted that 532 in this implementation can be combined with step 510, step 520, and step 540 in the above text to form a new implementation example and be implemented separately, and this application does not limit this.

[0117] Step 542: calling the equality comparator to compare the second value with the base address information;

[0118] Exemplarily, calling the equality comparator to compare the second value and the base address information is based on the logic circuit to compare and calculate the second value and the base address information. In an example, the equality comparator can be constructed based on an XOR gate circuit, or can be constructed based on an XNOR gate circuit. The present application does not limit the implementation of the equality comparator.

[0119] Step 544: When the second value and the base address information are equal, send a service request to the first extension device corresponding to the base address information;

[0120] Exemplarily, when the second value and the base address information are equal, the base address information of the base address register corresponding to the transmission destination address of the service request extracted from the request address is the same as the base address information corresponding to the first expansion device, and the transmission destination address of the service request corresponds to the first expansion device.

[0121] It should be noted that step 542 and step 544 in this embodiment can be Figure 4 Steps 510 to 530 in the embodiment are combined into a new embodiment and implemented separately, and this application does not limit this.

[0122] In summary, the method provided in this embodiment obtains the second value by calling the AND gate circuit, and sends a service request to the first expansion device when the second value and the base address information are compared to be the same by an equality comparator, thereby reducing the complexity of comparing the request address and the base address information, avoiding the use of an adder to compare the request address and the base address information of the first expansion device and limiting the size relationship of the address information in the related art, simplifying the adder calculation to the AND gate calculation, and saving computing resources.

[0123] Next, the equal sign comparator, AND gate circuit, etc. mentioned above are introduced through a specific example.

[0124] In an example, the transmission destination address indicated by the request address corresponds to a base address register in the first expansion device. During the verification process of the request address, the request address needs to be verified.

[0125] In the related art, it is necessary to sum the base address information (BAR_BASE) and the address length information (BAR_SIZE) of the base address register to calculate the limit address information (LIMIT_BAR_ADDR) of the base address register; the limit address information is used to indicate the end storage position of the base address register. It can be understood that the above summation process needs to be implemented by calling an adder.

[0126] Furthermore, it is also necessary to compare the size relationship between the request address and the base address information and the limit address information; when the request address is greater than or equal to the base address information, and the request address is less than or equal to the limit address information (also known as ADDR_BASE<=TLP_ADDR<=LIMIT_BAR_ADDR), send a service request to the first expansion device corresponding to the base address information. It is understandable that the above comparison process needs to call an adder to implement. It is understandable that in the related art, three adder circuits need to be called to verify the request address.

[0127] In the technical solution provided by the present application, when the address length information of the base address registers of different expansion devices is the same, the address length information is pre-set or determined by a table lookup. When the address length information of the base address registers of different expansion devices is different, the address length information corresponding to the first expansion device is obtained by table lookup.

[0128] The interpolation of the address length information and 1 is determined as the mask information, and the mask information is inverted to obtain a first value. The number of bits of the first value is the same as the number of bits of the base address information, such as 64 bits (Bit). Exemplarily, when the address length information is 4KB, the values ​​of the zeroth bit (Bit0) to the eleventh bit (Bit11) in the first value are all 0, and the values ​​of the twelfth bit (Bit12) to the sixty-third bit (Bit63) are all 1. Call the AND gate circuit to calculate the first value and the request address to obtain a second value, and the second value is the base address information of the base address register corresponding to the transmission destination address of the service request extracted from the request address.

[0129] The equal sign comparator is called to compare the second value with the base address information; when the second value and the base address information are equal, a service request is sent to the first extension device corresponding to the base address information.

[0130] It can be seen that in this embodiment, only the AND gate circuit and the equal sign comparator are called, which reduces the complexity of comparing the request address and the base address information, avoids the use of an adder to compare the request address with the base address information of the first expansion device and limit the size relationship of the address information in the related art, simplifies the adder calculation into an AND gate calculation, and saves computing resources.

[0131] Figure 7 A flowchart of a method for verifying address information provided by an exemplary embodiment of the present application is shown. The method can be executed by an electronic device. Figure 4 Based on the illustrated embodiment, step 515 is also included:

[0132] Step 515: Acquire an address table of at least two expansion devices stored in the electronic device;

[0133] Exemplarily, the electronic device stores an address table, which is used to indicate base address register information of at least two expansion devices that have a bus connection with the electronic device; the base address information and the first value in step 520 of this embodiment are obtained based on the address table.

[0134] In an example, the base address register information of at least two expansion devices in the address table may have a one-to-one correspondence with the hash value, which is not limited in this embodiment.

[0135] Exemplarily, the address table may include multiple storage parts, and the base address register information of the first expansion device is obtained by splicing the information of the multiple storage parts. Through the multiple storage parts included in the address table, it is possible to store the repeated parts in the base address register information of the expansion device only once, so as to save the storage space of the electronic device for the address table.

[0136] In summary, the method provided in this embodiment can quickly obtain the base address information and the first value of the first expansion device by storing the address table of at least two expansion devices in the electronic device; obtain the second value by AND gate calculation, and send the service request to the first expansion device when the second value and the base address information are the same, thereby reducing the complexity of comparing the request address and the base address information, avoiding the use of an adder to compare the request address and the base address information of the first expansion device and limiting the size relationship of the address information in the related art, simplifying the adder calculation to the AND gate calculation, and saving computing resources.

[0137] Next, the address table will be further introduced.

[0138] Figure 8 A flowchart of a method for verifying address information provided by an exemplary embodiment of the present application is shown. The method can be executed by an electronic device. Figure 7 In the illustrated embodiment, step 515 can be implemented as follows:

[0139] Step 515a: Obtain application address spaces of at least two extended devices;

[0140] Exemplarily, the application address space is used to indicate the number of binary digits of difference between the base address registers of at least two expansion devices; in one example, the application address space is obtained by comparing the base address register information of at least two expansion devices, and the application address space is used to indicate the highest number of digits of difference between the base address register information of at least two expansion devices. In another example, the address allocation of the expansion device is allocated according to continuous positions, but it does not exclude the situation that the address fine-tuning between some expansion devices and the existence of gaps are present. The application address space is used to indicate the pre-set space size for address allocation of at least two expansion devices. In one example, the pre-set size is 16MB (i.e., 2 20 *2 4 bits) space to allocate addresses to at least two expansion devices; accordingly, the number of binary difference bits indicated by the application address space is 24 bits.

[0141] Step 515b: Acquire the first sub-information in the base address register of any expansion device among the at least two expansion devices, and acquire at least two second sub-information corresponding to the base address registers of the at least two expansion devices in a one-to-one correspondence;

[0142] Exemplarily, the first sub-information and the second sub-information are partial information in the base address register information. Specifically, the first sub-information is the binary bits in the base address register that are greater than or equal to the target number of bits, and the second sub-information is the binary bits in the base address register that are less than the target number of bits. The target number of bits is determined based on the application address space. In one example, the target number of bits can be the sum of the binary number of bits indicated by the application address space and the maximum binary number of bits of the address length information of the first expansion device. Taking the binary difference number of bits indicated by the application address space as 24 bits and the address space size of the base address register as 4KB as an example, the target number of bits is 12+24=36 bits.

[0143] It should be noted that the first sub-information corresponds to the base address register of any one of the at least two expansion devices, and the number of the second sub-information is the same as the base address registers in the at least two expansion devices.

[0144] In an optional implementation, regarding the determination of the target number of digits, the following two steps are also included before this step:

[0145] Determine the product of the number of binary digits corresponding to the application address space and n as a fourth value;

[0146] ·Determine the target number of digits according to the fourth value;

[0147] Exemplarily, the value of n is greater than 1. In a preferred example, n is an integer, such as 2. Exemplarily, the target number of digits is greater than or equal to the fourth value. In an optional implementation, the target number of digits may be a homogeneous power of 2, a multiple of 2, or a multiple of 8. It is understandable that the target number of digits may also be implemented as other values ​​other than the above values, and this embodiment does not limit this.

[0148] Exemplarily, the target number of bits is determined based on the sum of the maximum binary digits of the fourth value and the address length information of the first expansion device. Taking the binary difference digit indicated by the application address space as 24 bits, the address space size of the base address register as 4KB, and n as 2 as an example, the sum of the maximum binary digits of the fourth value and the address length information of the first expansion device is 24*2=48 bits. The target number of bits is greater than the fourth value, and the target number of bits is a homogeneous power of 2, and the target number of bits is 64 bits. Exemplarily, the target number of bits is the smallest homogeneous power of 2 that is greater than or equal to the fourth value.

[0149] It should be noted that the fourth value is greater than the binary digit corresponding to the application address space, and the fourth value is a safety margin set for fine-tuning the addresses between some expansion devices and the presence of gaps. The target digit is a homogeneous power of 2 to facilitate the planning and setting of the alignment digits of the second storage part in the address table.

[0150] Step 515c: constructing an address table of at least two extended devices based on the first sub-information and at least two second sub-information;

[0151] Exemplarily, the first sub-information is used as the first storage part in the address table, and the multiple second sub-information corresponding to the base address register is used as the second storage part in the address table to construct the address table. It can be seen that only one first sub-information is stored in the address table, which saves the space occupied by the same storage information in the address table.

[0152] In summary, the method provided in this embodiment constructs an address table through the first sub-information and at least two second sub-information, thereby effectively reducing the storage space occupied by the storage address table; by storing the address table of at least two expansion devices in the electronic device, the base address information and the first value of the first expansion device can be quickly obtained; the second value is obtained by AND gate calculation, and when the second value and the base address information are the same, a service request is sent to the first expansion device, thereby reducing the complexity of comparing the request address and the base address information, avoiding the use of an adder to compare the request address and the base address information of the first expansion device and limiting the size relationship of the address information in the related art, simplifying the adder calculation to the AND gate calculation, and saving computing resources.

[0153] Next, the address table stored in the electronic device mentioned above is further introduced through a specific example.

[0154] In one example, the storage space of an expansion device connected to an electronic device is usually allocated with continuous addresses; specifically, the addresses of the base address register space of the expansion device are relatively continuous, and the base address registers can also be fine-tuned according to business needs, that is, there are gaps between the addresses of adjacent base address registers. It is understandable that due to the address allocation method of the base address registers, the base address information of the base address registers of different expansion devices has the same part.

[0155] Exemplarily, the application address space is used to indicate the number of binary difference bits between the base address registers of at least two expansion devices. In one example, the application address space indicates 6 bits;

[0156] Further, the fourth value is the application address space * 2 = 12 bits, and the target number of bits is a homogeneous power of 2 greater than the fourth value. In one example, the address table does not store the status information indicated by the address length information, that is, taking the address space size of the base address register as 4KB as an example, the lowest bit of the PCIE address that needs to be stored in the address table is the twelfth bit (Bit12); taking the address space size of the base address register as 8KB as an example, the lowest bit of the PCIE address that needs to be stored in the address table is the thirteenth bit (Bit13). In this embodiment, taking the address space size indicated by the address length information as 4KB as an example, the target number of bits is a homogeneous power of 2 greater than 12+12=24 bits. For example, the target number of bits is 32 bits. It can be seen that in this embodiment, the information from the twelfth bit to the thirty-second bit stored in the address table corresponds one-to-one to the base address register, and only one copy of the information higher than the thirty-second bit needs to be saved in the address table. When the number of expansion devices is 2k, the address space saved by constructing the address table is (64-32)*(2048-1)=32kbit-32bit, which reduces the storage resources required for the electronic device to store the address table.

[0157] In summary, the method provided in this embodiment constructs an address table through the first sub-information and at least two second sub-information, thereby effectively reducing the storage space occupied by the storage address table; by storing the address table of at least two expansion devices in the electronic device, the base address information and the first value of the first expansion device can be quickly obtained; the second value is obtained by AND gate calculation, and when the second value and the base address information are the same, a service request is sent to the first expansion device, thereby reducing the complexity of comparing the request address and the base address information, avoiding the use of an adder to compare the request address and the base address information of the first expansion device and limiting the size relationship of the address information in the related art, simplifying the adder calculation to the AND gate calculation, and saving computing resources.

[0158] Fig. 9 A flowchart of a method for verifying address information provided by an exemplary embodiment of the present application is shown. The method can be executed by an electronic device. Figure 4 Based on the embodiment shown, step 513 and step 514 are also included:

[0159] Step 513: Call the hash algorithm to process the request address and obtain the request hash value corresponding to the service request;

[0160] Exemplarily, the number of binary digits of the request hash value obtained by the hash algorithm is shorter than the number of binary digits of the request address. There is a corresponding relationship between the request hash value and the expansion device corresponding to the transmission destination address indicated by the request address. Exemplarily, the hash algorithm can process all the information in the request address or part of the information, which is not limited in this embodiment.

[0161] Exemplarily, the hash algorithm includes but is not limited to at least one of a cyclic redundancy check (CRC) algorithm, an MD5 message-digest algorithm (MD5), and a secure hash algorithm (SHA).

[0162] Step 514: Obtain hash tables corresponding to at least two expansion devices, and search the hash tables to obtain a target hash value that is the same as the requested hash value;

[0163] Exemplarily, the hash table is used to record hash values ​​of at least two expansion devices; further, there is a one-to-one correspondence between the hash value and the base address register of the expansion device. Exemplarily, the hash table is usually stored by an electronic device, but it does not exclude the situation where it is stored in the expansion device or other devices. Exemplarily, the target hash value that is the same as the requested hash value is obtained by searching in the hash table. This embodiment does not limit the method of searching the target hash value in the hash table, which can be obtained by searching character by character, or by at least one of sequential search, hash search, and binary tree search. Exemplarily, there is an association relationship between the target hash value and the first expansion device, and further, there is a corresponding association relationship between the target hash value and a base address register in the first expansion device.

[0164] In summary, the method provided in this embodiment reduces the time required for determining the first expansion device among multiple expansion devices by searching for the target hash value in the hash table; obtains the second value through AND gate calculation, and sends a service request to the first expansion device when the second value and the base address information are the same, thereby reducing the complexity of comparing the request address and the base address information, avoiding the use of an adder to compare the request address with the base address information of the first expansion device and the size relationship of the limit address information in the related art, simplifying the adder calculation to the AND gate calculation, and saving computing resources.

[0165] Next, step 514 above is further introduced.

[0166] In an optional implementation, step 514 may be implemented as the following two sub-steps:

[0167] Sub-step 14a: searching the first sub-hash value in the request hash value based on the first sub-table;

[0168] Exemplarily, the first sub-hash value is a portion of binary bits of the requested hash value; in one example, the first sub-hash value is the zeroth bit (Bit0) to the eleventh bit (Bit11) of the requested hash value.

[0169] Sub-step 14b: when a conflict occurs when searching the first sub-hash value in the first sub-table, obtaining a target hash value that is the same as the second sub-hash value in the request hash value based on searching in the second sub-table;

[0170] Exemplarily, the second sub-hash value is part of the binary bits of the request hash value, and the first sub-hash value and the second sub-hash value have different corresponding binary bit information in the request hash value; in one example, the first sub-hash value is the first bit (Bit1) to the twelfth bit (Bit12) in the request hash value. It should be noted that, in this embodiment, the algorithm initial value for calling the hash algorithm to process the request address data can be pre-configured, and the discreteness of the hash algorithm is adjusted by configuring different algorithm initial values ​​to reduce the conflict rate.

[0171] In summary, the method provided in this embodiment reduces the time required for determining the first expansion device among multiple expansion devices by searching the target hash value in the hash table, effectively reduces the probability of hash conflicts through the multiple sub-tables in the hash table, and ensures the hashing conditions between different expansion devices; obtains the second value through AND gate calculation, and sends a service request to the first expansion device when the second value and the base address information are the same, thereby reducing the complexity of comparing the request address and the base address information, avoiding the use of an adder to compare the request address with the base address information of the first expansion device and the size relationship of the limit address information in the related art, simplifying the adder calculation to the AND gate calculation, and saving computing resources.

[0172] Fig.10 A schematic diagram of base address register routing provided by an exemplary embodiment of the present application is shown.

[0173] The base address register routing (bar_rout) 610 includes a routing table of the base address register in the expansion device. Taking the first expansion device including two base address registers as an example, it includes a bar0 routing table (bar0_table_rout) 611 and a bar2 routing table (bar2_table_rout) 612. The base address register in this embodiment is a 64-bit BAR, but it does not exclude the case where the base address register in other embodiments is a 32-bit BAR. After obtaining the memory request (Memory Request) message, the bar0 routing table 611 and the bar2 routing table 612 are searched in parallel, and the host port routing (host_pn_rout) 613 and the system on chip port routing (soc_pn_rout) 614 are mapped synchronously. Exemplarily, the memory request mapping has at most one base address register. After the mapping results are aggregated in the routing hint (rout_hit_rist) 615, the memory request is written into the routing buffer (rout_fifo) 616. If the storage of the escape hash table (Hash Table level 2) 617 is not zero, the hash value of the memory request message is determined based on the record in the escape hash table 617. Exemplarily, the conflict rate can be reduced by adjusting the configuration and algorithm to avoid the storage of the escape hash table 617 being not zero.

[0174] Fig.11 A schematic diagram of a base address register routing table provided by an exemplary embodiment of the present application is shown. The base address register routing table in this embodiment is barN routing table 610a, which can be Fig.10 bar0 routing table 611 or bar2 routing table 612 in. Exemplarily, an AND gate calculation is performed on the first value 621 and the request address 622, and the AND gate calculation result and the initial value 623 are processed by calling the CRC algorithm, and the request hash value corresponding to the request address 622 is stored in the CRC register (CRCO_REG) 625, and the CRC register 625 also stores the port number 624a and the PCIE mode 624b. Among them, the first value 621 is obtained by inverting the mask information, and is recorded as ~barn_mask. For the introduction of the mask information, please refer to sub-step 24a above. The first value 621 is the initial input value of the CRC algorithm, recorded as crc_init_value. The 0th to Mth bits (crco[M:0]) in the request hash value are searched in the first sub-hash table (Hash Table level0) 626a, and the 1st to M+1th bits (crco[M+1:1]) in the request hash value are searched in the second sub-hash table (Hash Table level1) 626b.

[0175] Exemplarily, a D flip-flop (Data Flip-Flop, DFF) 627 is called to process the first part of the request address 622 (recorded as tlp_addr[high_width-1:low_width]), and the calculation result and the search results in the first sub-hash table 626a and the second sub-hash table 626b are respectively AND gated. The second part of the request address 622 (recorded as tlp_addr[63:high_width]) is directly compared with the base address information 628, and an AND gate calculation is performed. Exemplarily, the slots (slots) in the first sub-hash table 626a and the second sub-hash table 626b record the address information and the function number (function_num) and valid value (vaild) of the expansion device. By comparing the first part and the second part of the request address 622, the function number (function_num) corresponding to the request address 622 is obtained.

[0176] Fig.12 A flowchart of a method for verifying address information provided by an exemplary embodiment of the present application is shown. The method can be performed by an electronic device and an expansion device. Exemplarily, the first subsystem in the electronic device is a host device (Host), the second subsystem is an application layer device (Application), the expansion device is a system on chip, the second memory in the system on chip is a SOC memory, and the processing unit is a comprehensive management unit.

[0177] Step 702: The host device sends a configuration TLP to the application layer device;

[0178] Exemplarily, the host device 1. Power-on reset and evacuate, and the startup is the Basic Input / Output System (BIOS) or the Operating System (OS) enumeration and driver loading. Exemplarily, the BIOS is first run to initialize the hardware and start the operating system. The operating system enumerates and identifies the hardware devices of the computer and loads the corresponding device drivers to ensure that the hardware can be used and controlled normally by the operating system.

[0179] Step 704: The application layer device sends a configuration TLP to the SOC memory;

[0180] Exemplarily, the application layer device forwards the received configuration TLP (CFGTLP) to the SOC memory.

[0181] Step 706: The SOC memory sends a configuration TLP to the integrated management unit;

[0182] Exemplarily, the SOC memory forwards the received configuration TLP to the integrated management unit. Exemplarily, the hardware writes the configuration TLP to the SOC memory, and the integrated management unit reads and writes the configuration TLP and parses it according to the pointer state.

[0183] Step 708: The integrated management unit sends the register configuration to the application layer device;

[0184] Exemplarily, the integrated management unit configures information to the hardware device according to the configuration result of enumeration / driver loading; exemplary, the register configuration includes basic configuration of the routing table.

[0185] Step 710: The integrated management unit sends a response message to the application layer device;

[0186] Exemplarily, the response message includes a cpl / cpld message which is a completion message of the integrated management unit.

[0187] Step 712: The application layer device sends a response message to the host device;

[0188] Exemplarily, the application layer device forwards the response message to the host device.

[0189] Step 714: The host device sends a storage TLP to the application layer device;

[0190] Exemplarily, the host device accesses the device space through a memory TLP (Memory TLP).

[0191] Step 716: The application layer device sends a storage TLP to the SOC memory;

[0192] For example, the application layer device forwards the received storage TLP to the SOC memory; when the storage TLP passes through the hardware, it needs to check the routing table to determine the destination device to be accessed. If the mapping is to the on-chip device of the application layer device, it will be routed to the on-chip module. If it involves control management, it will be routed to the SOC memory (Soc Memory), and the integrated management unit will parse and process it. If the routing result is that the corresponding device is not found, it will be processed according to the protocol and an error will be reported.

[0193] Step 718: The SOC memory sends a storage TLP to the integrated management unit;

[0194] Exemplarily, the SOC memory forwards the received storage TLP to the integrated management unit.

[0195] Step 720: The integrated management unit sends the register or table configuration to the application layer device;

[0196] The integrated management unit sends registers or table configuration to the application layer device.

[0197] Step 722: The integrated management unit sends a response message to the application layer device;

[0198] Exemplarily, the response message includes a cpl / cpld message which is a completion message of the integrated management unit.

[0199] Step 724: The application layer device sends a response message to the host device;

[0200] Exemplarily, the application layer device forwards a response message (cpid tlp for memory read request) to the host device.

[0201] Those skilled in the art can understand that the above embodiments can be implemented independently, or the above embodiments can be freely combined to form new embodiments to implement the address information verification method of the present application.

[0202] Fig.13 A structural block diagram of an address information verification device provided by an exemplary embodiment of the present application is shown. The device is applied to an electronic device, a bus connection is established between the electronic device and at least two expansion devices, and the device includes:

[0203] An acquisition module 810 is used to acquire a request address of a service request, where the service request is used to indicate a service processing mode of the first extension device;

[0204] The acquisition module 810 is further used to acquire the base address information of the first expansion device and a first value corresponding to the first expansion device, the base address information is used to indicate the starting storage position of the base address register of the first expansion device, the high-order bits in the first value are the first value, the low-order bits in the first value are the second value, the number of binary digits of the high-order bits is greater than or equal to the maximum number of binary digits of the address length information of the first expansion device, and the number of binary digits of the low-order bits is less than the maximum number of binary digits of the address length information;

[0205] A processing module 820, configured to perform an AND gate calculation based on the first value and the request address to obtain a second value;

[0206] The sending module 830 is configured to send the service request to the first extension device corresponding to the base address information in response to the second value being the same as the base address information.

[0207] In an optional implementation of the embodiment, the acquisition module 810 is further used to:

[0208] Acquire the address length information of the first expansion device, where the address length information is used to indicate the address space size of the base address register of the first expansion device;

[0209] A binary bit operation is performed based on the address length information to obtain the first value.

[0210] In an optional implementation of the embodiment, the acquisition module 810 is further used to:

[0211] Determine the difference between the address length information and the third value as mask information, wherein the mask information is used to determine the binary digit whose binary digit number is less than the maximum binary digit number of the address length information as the first value;

[0212] The mask information is inverted to obtain the first value.

[0213] In an optional implementation of the embodiment, the sending module 830 is further used for:

[0214] Calling an equality comparator to compare the second value with the base address information;

[0215] When the second value is equal to the base address information, the service request is sent to the first extension device corresponding to the base address information.

[0216] In an optional implementation of the embodiment, the processing module 820 is further configured to:

[0217] An AND gate circuit is called to calculate the first value and the request address to obtain the second value.

[0218] In an optional implementation of the embodiment, the acquisition module 810 is further used to:

[0219] Acquire an address table of the at least two expansion devices stored in the electronic device, wherein the address table is used to indicate base address register information of at least two expansion devices with which a bus connection is established;

[0220] The base address information and the first value are obtained based on the address table.

[0221] In an optional implementation of the embodiment, the acquisition module 810 is further used to:

[0222] Acquire application address spaces of the at least two expansion devices, where the application address spaces are used to indicate the number of binary difference bits between base address registers of the at least two expansion devices;

[0223] Acquire first sub-information in a base address register of any expansion device among the at least two expansion devices, and acquire at least two second sub-information corresponding to the base address registers of the at least two expansion devices in a one-to-one manner;

[0224] Based on the first sub-information and the at least two second sub-information, construct an address table of the at least two expansion devices;

[0225] The first sub-information is the binary bits in the base address register that are greater than or equal to the target bit number, and the second sub-information is the binary bits in the base address register that are less than the target bit number, and the target bit number is determined based on the application address space.

[0226] In an optional implementation of the embodiment, the processing module 820 is further configured to:

[0227] Determine the product of the number of binary digits corresponding to the application address space and n as a fourth value, where n is greater than 1;

[0228] The target number of digits is determined according to the fourth value, and the target number of digits is greater than or equal to the fourth value.

[0229] In an optional implementation of the embodiment, the processing module 820 is further configured to:

[0230] Calling a hash algorithm to process the request address to obtain a request hash value corresponding to the service request;

[0231] A hash table corresponding to the at least two expansion devices is obtained, and a target hash value that is the same as the request hash value is searched in the hash table, and there is an association relationship between the target hash value and the first expansion device.

[0232] In an optional implementation of the embodiment, the hash table includes a first sub-table and a second sub-table;

[0233] The processing module 820 is further configured to:

[0234] Searching for a first sub-hash value in the request hash value based on the first sub-table, where the first sub-hash value is a partial binary bit of the request hash value;

[0235] In the event that a conflict occurs when searching the first sub-hash value in the first sub-table, the target hash value that is the same as the second sub-hash value in the request hash value is obtained based on the search in the second sub-table, where the second sub-hash value is part of the binary bits of the request hash value, and the first sub-hash value and the second sub-hash value have different corresponding binary bit information in the request hash value.

[0236] One point that needs to be explained is that the device provided in the above embodiment only uses the division of the above-mentioned functional modules as an example to implement its functions. In actual applications, the above-mentioned functions can be assigned to different functional modules according to actual needs, that is, the content structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0237] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method; the technical effects achieved by each module performing operations are the same as those in the embodiment of the method, and will not be elaborated here.

[0238] The present application also provides a computer device, which includes: a processor and a memory, wherein a computer program is stored in the memory; the processor is used to execute the computer program in the memory to implement the address information verification method provided by the above-mentioned method embodiments. Optionally, the computer device is a server. For example, Fig.14 2300 is a structural block diagram of a server provided by an exemplary embodiment of the present application. Generally, the server 2300 includes: a processor 2301 and a memory 2302 .

[0239] The processor 2301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 2301 may be implemented in at least one hardware form of digital signal processing (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). The processor 2301 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 2301 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 2301 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0240] The memory 2302 may include one or more computer-readable storage media, which may be non-transitory. The memory 2302 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 2302 is used to store at least one instruction, which is used to be executed by the processor 2301 to implement the address information verification method provided in the method embodiment of the present application.

[0241] In some embodiments, the server 2300 may also optionally include: an input interface 2303 and an output interface 2304. The processor 2301, the memory 2302, the input interface 2303, and the output interface 2304 may be connected via a bus or a signal line. Each peripheral device may be connected to the input interface 2303 and the output interface 2304 via a bus, a signal line, or a circuit board. The input interface 2303 and the output interface 2304 may be used to connect at least one peripheral device related to input / output (I / O) to the processor 2301 and the memory 2302. In some embodiments, the processor 2301, the memory 2302, the input interface 2303, and the output interface 2304 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 2301, the memory 2302, the input interface 2303, and the output interface 2304 may be implemented on a separate chip or circuit board, which is not limited in the embodiments of the present application.

[0242] Those skilled in the art will appreciate that the structure shown above does not constitute a limitation on the server 2300 , and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0243] In an exemplary embodiment, a chip is further provided. The chip includes a programmable logic circuit and / or program instructions. When the chip is run on a computer device, it is used to implement the address information verification method described in the above aspects.

[0244] In an exemplary embodiment, a computer program product is also provided, the computer program product includes computer instructions, the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor reads and executes the computer instructions from the computer-readable storage medium to implement the address information verification method provided in the above-mentioned method embodiments.

[0245] In an exemplary embodiment, a computer-readable storage medium is further provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the address information verification method provided by the above-mentioned method embodiments.

[0246] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0247] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0248] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for verifying address information, characterized in that: The method is performed by an electronic device, a bus connection is established between the electronic device and at least two expansion devices, and the method includes: Obtaining a request address of a service request, where the service request is used to indicate a service processing mode of the first extension device; Acquire base address information of the first expansion device and a first value corresponding to the first expansion device, wherein the base address information is used to indicate a starting storage position of a base address register of the first expansion device, a high-order bit in the first value is a first value, a low-order bit in the first value is a second value, a number of binary digits of the high-order bit is greater than or equal to a maximum number of binary digits of the address length information of the first expansion device, and a number of binary digits of the low-order bit is less than a maximum number of binary digits of the address length information; Perform an AND gate calculation based on the first value and the request address to obtain a second value; In response to the second value being the same as the base address information, sending the service request to the first extension device corresponding to the base address information.

2. The method according to claim 1, characterized in that The obtaining of a first value corresponding to the first extension device includes: Acquire the address length information of the first expansion device, where the address length information is used to indicate the address space size of the base address register of the first expansion device; A binary bit operation is performed based on the address length information to obtain the first value.

3. The method according to claim 2, characterized in that The performing binary bit operation based on the address length information to obtain the first value includes: Determine the difference between the address length information and the third value as mask information, wherein the mask information is used to determine the binary digit whose binary digit number is less than the maximum binary digit number of the address length information as the first value; The mask information is inverted to obtain the first value.

4. The method according to any one of claims 1 to 3, characterized in that: In response to the second value being the same as the base address information, sending the service request to the first extension device corresponding to the base address information includes: Calling an equality comparator to compare the second value with the base address information; When the second value is equal to the base address information, the service request is sent to the first extension device corresponding to the base address information.

5. The method according to any one of claims 1 to 3, characterized in that: The performing AND gate calculation based on the first value and the request address to obtain a second value includes: An AND gate circuit is called to calculate the first value and the request address to obtain the second value.

6. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: Acquire an address table of the at least two expansion devices stored in the electronic device, wherein the address table is used to indicate base address register information of at least two expansion devices with which a bus connection is established; The base address information and the first value are obtained based on the address table.

7. The method according to claim 6, characterized in that The acquiring the address table of the at least two extended devices stored in the electronic device includes: Acquire application address spaces of the at least two expansion devices, where the application address spaces are used to indicate the number of binary difference bits between base address registers of the at least two expansion devices; Acquire first sub-information in a base address register of any expansion device among the at least two expansion devices, and acquire at least two second sub-information corresponding to the base address registers of the at least two expansion devices in a one-to-one manner; Based on the first sub-information and the at least two second sub-information, construct an address table of the at least two expansion devices; The first sub-information is the binary bits in the base address register that are greater than or equal to the target bit number, and the second sub-information is the binary bits in the base address register that are less than the target bit number, and the target bit number is determined based on the application address space.

8. The method according to claim 7, characterized in that The method further comprises: Determine the product of the number of binary digits corresponding to the application address space and n as a fourth value, where n is greater than 1; The target number of digits is determined according to the fourth value, and the target number of digits is greater than or equal to the fourth value.

9. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: Calling a hash algorithm to process the request address to obtain a request hash value corresponding to the service request; A hash table corresponding to the at least two expansion devices is obtained, and a target hash value that is the same as the request hash value is searched in the hash table, and there is an association relationship between the target hash value and the first expansion device.

10. The method according to claim 9, characterized in that The hash table includes a first sub-table and a second sub-table; The step of searching in the hash table to obtain a target hash value that is the same as the requested hash value includes: Searching for a first sub-hash value in the request hash value based on the first sub-table, where the first sub-hash value is a partial binary bit of the request hash value; In the event that a conflict occurs when searching the first sub-hash value in the first sub-table, the target hash value that is the same as the second sub-hash value in the request hash value is obtained based on the search in the second sub-table, where the second sub-hash value is part of the binary bits of the request hash value, and the first sub-hash value and the second sub-hash value have different corresponding binary bit information in the request hash value.

11. A device for verifying address information, characterized in that: The device is applied to an electronic device, a bus connection is established between the electronic device and at least two expansion devices, and the device includes: An acquisition module, used to acquire a request address of a service request, where the service request is used to indicate a service processing mode of the first extension device; The acquisition module is further used to acquire base address information of the first expansion device and a first value corresponding to the first expansion device, the base address information is used to indicate a starting storage position of a base address register of the first expansion device, a high-order bit in the first value is a first value, a low-order bit in the first value is a second value, a number of binary digits of the high-order bit is greater than or equal to a maximum number of binary digits of the address length information of the first expansion device, and a number of binary digits of the low-order bit is less than a maximum number of binary digits of the address length information; a processing module, configured to perform an AND gate calculation based on the first value and the request address to obtain a second value; The sending module is configured to send the service request to the first extension device corresponding to the base address information in response to the second value being the same as the base address information.

12. A computer device, characterized in that: The computer device includes: a processor and a memory, wherein the memory stores at least one program; the processor is used to execute the at least one program in the memory to implement the address information verification method as described in any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that: The readable storage medium stores executable instructions, and the executable instructions are loaded and executed by a processor to implement the address information verification method according to any one of claims 1 to 10.

14. A computer program product, characterized in that The computer program product includes computer instructions, which are stored in a computer-readable storage medium. A processor reads and executes the computer instructions from the computer-readable storage medium to implement the address information verification method as described in any one of claims 1 to 10.

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