RAM (Random Access Memory) multiplexing method of SOC (System On Chip)

Abstract

The invention discloses an RAM (Random Access Memory) multiplexing method of an SOC (System On Chip). In the invention, the IDRAM which is defaulted to be used as the DRAM is converted into the IRAM, so that the use requirement is met. The design can reduce the chip area as much as possible on the premise of meeting the use scene of the chip, improves the processing speed of a CPU (Central Processing Unit), and also can save the cost by reducing the area and firmware overhead. The actual area of the IRAM, the actual area of the DRAM and the actual area of the IDRAM can be evaluated according to actual requirements, and the larger the IDRAM is, the larger the area can be saved. According to the design, an IDRAM time division multiplexing scheme is ingeniously designed by analyzing actual application requirements of different buses of a CPU, the area of RAMs which do not need to be used at the same time is greatly reduced, power consumption is reduced, cost is saved, meanwhile, better use flexibility is provided for firmware, and more sufficient hardware resources are provided for some special use scenes.

Description

Technical Field

[0001] The invention belongs to the technical field of SOC chips, and in particular relates to a RAM multiplexing method of SOC. Background Art

[0002] In today's trend of high-speed informatization, consumer electronic products are emerging in an endless stream, promoting technological progress while also providing consumers with a variety of choices. As a system on a chip, SOC chips can meet the application needs of a variety of different scenarios with a built-in CPU. In today's trend of high-speed informatization, consumer electronic products are emerging in an endless stream, promoting technological progress while also providing consumers with a variety of choices. As a system on a chip, SOC chips can meet the application needs of a variety of different scenarios with a built-in CPU.

[0003] However, the traditional SOC chip is difficult to use in mobile phones, tablets, and wearable devices due to its large area. The existing RAM structure, although it has time-sharing reuse of IDRAM in boot mode and normal working mode, cannot further save RAM overhead. In normal working mode, only the maximum usage requirements of IRAM and DRAM are processed without considering the actual application scenario. In actual use, it is often not necessary to use both at the same time. At the same time, the existing technology will use all the DRAM space for algorithm calculations, and printing can only be added to IRAM at this time. At this time, the size of DRAM usage can be flexibly changed by adjusting the firmware algorithm, and it is not necessary to use up all the space. In this case, the existing technology has caused a certain degree of resource waste.

[0004] In view of the above problems, the present invention adopts a RAM reuse method of SOC to reduce the total area of ​​RAM, thereby reducing the area of ​​SOC chip. The present invention is applied to SOC chip, but is not limited to SOC chip. Summary of the invention

[0005] The purpose of the present invention is to provide a RAM multiplexing method for SOC in order to solve the above-mentioned problem.

[0006] The technical solution adopted by the present invention is as follows: a RAM multiplexing method of a SOC, the method comprising the following steps:

[0007] S1: Determine the RAM requirements of the SOC chip, including the size and usage scenarios of IRAM and DRAM;

[0008] S2: Design a flexible and reusable IDRAM, whose size is evaluated based on the requirements of IRAM and DRAM;

[0009] S3: Reserve address space in the operating system so that it can be accessed normally when used as IRAM and DRAM;

[0010] S4: Add an IDRAM_sel register in the operating system to select the function of IDRAM;

[0011] S5: By default, IDRAM is used as DRAM to store data required by the system;

[0012] S6: According to the actual application scenario, the CPU writes a value to the IDRAM_sel register to change the function of the IDRAM;

[0013] S7: When IDRAM is used as IRAM, the internal hardware logic redirects the data to communicate with the instruction bus;

[0014] S8: When IDRAM is used as DRAM, the internal hardware logic redirects the data and communicates with the data bus;

[0015] S9: Through time-sharing multiplexing of IDRAM, hardware overhead is saved, power consumption and cost are reduced, and the flexibility of firmware operation is improved.

[0016] In a preferred embodiment, in step S1, a flexible and reusable IDRAM is used to expand the IRAM and DRAM in a time-sharing manner to save hardware overhead. In actual use, since the firmware will optimize the code to a certain extent, the IRAM will not often exceed the capacity. Therefore, the IDRAM will be used as the expansion of the DRAM by default. By reserving address space separately (such as Figure 1 ), so that IDRAM can be accessed normally as expansion in both usage scenarios. In some special application scenarios, such as debug mode, a larger IRAM space is required to meet the operation requirements of the firmware.

[0017] In a preferred embodiment, in step S2, the size of the IDRAM should be evaluated according to actual needs, and its area should be minimized while ensuring functionality. In order to achieve time-sharing multiplexing of the IDRAM, it is necessary to reserve address space in the IDRAM so that it can be normally accessed when used as an IRAM and a DRAM. There are many ways to reserve address space, such as dividing the address space of the IDRAM into multiple segments, each of which can be mapped to the address space of the IRAM or the DRAM respectively.

[0018] In a preferred embodiment, in step S4, a 1-bit IDRAM_sel register (readable and writable, configurable in multiple ways such as CPU or debug path) is added to select the actual function of IDRAM. After the system is powered on, when the default setting of the IDRAM_sel register is not configured, IDRAM is used as DRAM to store data required by the system. According to the changes in the actual usage scenario, the function of IDRAM will be flexibly changed. If the function of IDRAM needs to be changed, it is necessary to write a value to the register IDRAM_sel through the CPU to change the corresponding address space and usage status. After the writing is correct, the internal hardware logic will combine the IDRAM_sel register and the access address of the bus to redirect the data, communicate with the instruction bus or the data bus, and complete the conversion of different address spaces of IRAM, such as Figure 4 shown.

[0019] In a preferred embodiment, in step S5, when the IDRAM_sel register is "0" or "1", the IDRAM is time-division multiplexed. By design, it is possible to save RAM overhead by combining the actual use conditions of the SOC chip with only a small increase in hardware logic and address space. While this resource exchange saves area, it also improves the flexibility of firmware operation and provides flexible and variable RAM resources for different application scenarios.

[0020] In a preferred embodiment, in step S3, reserving address space in the operating system is the key to realizing RAM time-sharing multiplexing. There are many ways to reserve address space, such as dividing the address space of IDRAM into multiple segments, each of which can be mapped to the address space of IRAM or DRAM respectively. The advantage of this method is that the size of IRAM and DRAM can be flexibly adjusted to meet the needs of different application scenarios. For example, if a certain application requires a larger IRAM space, more address space in IDRAM can be mapped to the address space of IRAM.

[0021] In a preferred embodiment, in step S6, the function of IDRAM is changed by writing a value to the IDRAM_sel register through the CPU. For example, if a certain application requires a larger IRAM space, the value of the IDRAM_sel register can be set to "1" to use IDRAM as IRAM. This flexible way of changing the function of IDRAM can meet the needs of different application scenarios for RAM.

[0022] In a preferred embodiment, in step S7, when the CPU reads instructions from the IDRAM, it maps the address to the address space of the IRAM. This method can achieve the expansion of the IDRAM to the IRAM, thereby meeting the requirements of the application program for instruction storage space.

[0023] In a preferred embodiment, in step S8, when the CPU accesses data in the IDRAM, the address is mapped to the address space of the DRAM. This method can achieve the expansion of the DRAM by the IDRAM, thereby meeting the demand of the application for data storage space.

[0024] In a preferred embodiment, in step S9, IDRAM can be flexibly allocated to IRAM or DRAM according to the needs of actual application scenarios, thereby avoiding wasting RAM resources. For example, if a certain application requires a larger IRAM space, IDRAM can be used as IRAM, thereby avoiding adding additional IRAM chips, saving chip area and cost. At the same time, time-sharing multiplexing of IDRAM can also improve the flexibility of firmware operation, for example, the function of IDRAM can be easily switched to meet different application scenarios.

[0025] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0026] In the present invention, the IDRAM that is used as DRAM by default can be reused as IRAM to meet the usage requirements. Such a design can reduce the chip area as much as possible while improving the processing speed of the CPU under the premise of meeting the chip usage scenario. In addition, the reduction in area and firmware overhead can also save costs. The actual area of ​​IRAM, DRAM and IDRAM can be evaluated according to actual needs. The larger the IDRAM, the more area can be saved. This design cleverly designs an IDRAM time-sharing multiplexing scheme by analyzing the actual application requirements of different CPU buses, greatly reducing the area of ​​RAM that does not need to be used at the same time, achieving power consumption reduction and cost savings, while providing better usage flexibility for the firmware and providing more sufficient hardware resources for some special usage scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the structure of the IDRAM of the present invention being multiplexed into IRAM and DRAM respectively;

[0028] Figure 2 This is the RAM processing method of traditional SOC chips in normal working mode;

[0029] Figure 3 The RAM time-sharing multiplexing method for existing SOC chips is similar to this design;

[0030] Figure 4 It is a schematic diagram of time-division multiplexing gating of the SOC chip IDRAM in the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0032] Reference Figure 1-4 ,

[0033] A RAM multiplexing method for a SOC, the method comprising the following steps:

[0034] S1: Determine the RAM requirements of the SOC chip, including the size and usage scenarios of IRAM and DRAM;

[0035] S2: Design a flexible and reusable IDRAM, whose size is evaluated based on the requirements of IRAM and DRAM;

[0036] S3: Reserve address space in the operating system so that it can be accessed normally when used as IRAM and DRAM;

[0037] S4: Add an IDRAM_sel register in the operating system to select the function of IDRAM;

[0038] S5: By default, IDRAM is used as DRAM to store data required by the system;

[0039] S6: According to the actual application scenario, the CPU writes a value to the IDRAM_sel register to change the function of the IDRAM;

[0040] S7: When IDRAM is used as IRAM, the internal hardware logic redirects the data to communicate with the instruction bus;

[0041] S8: When IDRAM is used as DRAM, the internal hardware logic redirects the data and communicates with the data bus;

[0042] S9: Through time-sharing multiplexing of IDRAM, hardware overhead is saved, power consumption and cost are reduced, and the flexibility of firmware operation is improved.

[0043] In step S1, a flexible and reusable IDRAM is used to expand the IRAM and DRAM in time-sharing mode to save hardware overhead. In actual use, since the firmware will optimize the code to a certain extent, the IRAM will not often exceed the capacity. Therefore, the IDRAM will be used as the expansion of DRAM by default. By reserving address space separately (such as Figure 1 ), so that IDRAM can be accessed normally as expansion in both usage scenarios. In some special application scenarios, such as debug mode, a larger IRAM space is required to meet the operation requirements of the firmware.

[0044] In step S2, the size of IDRAM should be evaluated according to actual needs, and its area should be minimized while ensuring functionality. In order to achieve time-sharing multiplexing of IDRAM, address space needs to be reserved in the operating system so that it can be accessed normally when used as IRAM and DRAM. There are many ways to reserve address space, such as dividing the address space of IDRAM into multiple segments, each of which can be mapped to the address space of IRAM or DRAM respectively.

[0045] In step S4, a 1-bit IDRAM_sel register is added (readable and writable, and can be configured in multiple ways such as the CPU or debug path) to select the actual function of the IDRAM. After the system is powered on, when the IDRAM_sel register is not configured in the default state, the IDRAM is used as a DRAM to store data that the system needs to use. According to changes in actual usage scenarios, the function of the IDRAM will be flexibly changed. If the function of the IDRAM needs to be changed, it is necessary to write a value to the register IDRAM_sel through the CPU to change the corresponding address space and usage status. After the writing is correct, the internal hardware logic will combine the IDRAM_sel register and the bus access address to redirect the data, communicate with the instruction bus or the data bus, and complete the conversion of different address spaces of IRAM, such as Figure 4 shown.

[0046] In step S5, when the IDRAM_sel register is "0" or "1", the IDRAM is time-division multiplexed. By design, it is possible to save RAM overhead by adding only a small amount of hardware logic and address space, combined with the actual use conditions of the SOC chip. While this resource exchange saves area, it also improves the flexibility of firmware operation and provides flexible and variable RAM resources for different application scenarios.

[0047] In step S3, reserving address space in IDRAM is the key to realizing RAM time-sharing multiplexing. There are many ways to reserve address space, such as dividing the address space of IDRAM into multiple segments, each of which can be mapped to the address space of IRAM or DRAM respectively. The advantage of this method is that the size of IRAM and DRAM can be flexibly adjusted to meet the needs of different application scenarios. For example, if an application requires a larger IRAM space, more address space in IDRAM can be mapped to the address space of IRAM.

[0048] In step S6, the CPU writes a value to the IDRAM_sel register to change the function of the IDRAM. For example, if an application requires a larger IRAM space, the value of the IDRAM_sel register can be set to "1" to use the IDRAM as an IRAM. This flexible way of changing the function of the IDRAM can meet the needs of different application scenarios for RAM.

[0049] In step S7, when the CPU reads an instruction from the IDRAM, it maps its address to the address space of the IRAM. This method can achieve the expansion of the IDRAM to the IRAM, thereby meeting the requirements of the application program for the instruction storage space.

[0050] In step S8, when the CPU accesses the data in the IDRAM, the address is mapped to the address space of the DRAM. This method can realize the expansion of the DRAM by the IDRAM, thereby meeting the demand of the application program for data storage space.

[0051] In step S9, IDRAM can be flexibly allocated to IRAM or DRAM according to the needs of the actual application scenario, thereby avoiding wasting RAM resources. For example, if an application requires a larger IRAM space, IDRAM can be used as IRAM, thereby avoiding adding additional IRAM chips, saving chip area and cost. At the same time, time-sharing multiplexing of IDRAM can also improve the flexibility of firmware operations. For example, the function of IDRAM can be easily switched to meet different application scenarios.

[0052] In the present invention, the IDRAM that is used as DRAM by default can be reused as IRAM to meet the usage requirements. Such a design can reduce the chip area as much as possible while improving the processing speed of the CPU under the premise of meeting the chip usage scenario. In addition, the reduction in area and firmware overhead can also save costs. The actual area of ​​IRAM, DRAM and IDRAM can be evaluated according to actual needs. The larger the IDRAM, the more area can be saved. This design cleverly designs an IDRAM time-sharing multiplexing scheme by analyzing the actual application requirements of different CPU buses, greatly reducing the area of ​​RAM that does not need to be used at the same time, achieving power consumption reduction and cost savings, while providing better usage flexibility for the firmware and providing more sufficient hardware resources for some special usage scenarios.

[0053] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0054] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A RAM multiplexing method for a SOC, characterized in that: The method comprises the following steps: S1: Determine the RAM requirements of the SOC chip, including the size and usage scenarios of IRAM and DRAM; S2: Design a flexible and reusable IDRAM, whose size is evaluated based on the requirements of IRAM and DRAM; S3: Reserve address space in the operating system so that IDRAM can be accessed normally when used as IRAM and DRAM; S4: Add an IDRAM_sel register in the operating system to select the function of IDRAM; S5: By default, IDRAM is used as DRAM to store data required by the system; S6: According to the actual application scenario, the CPU writes a value to the IDRAM_sel register to change the function of the IDRAM; S7: When IDRAM is used as IRAM, the internal hardware logic redirects the data to communicate with the instruction bus; S8: When IDRAM is used as DRAM, the internal hardware logic redirects the data and communicates with the data bus; S9: Through time-sharing multiplexing of IDRAM, hardware overhead is saved, power consumption and cost are reduced, and the flexibility of firmware operation is improved.

2. The RAM multiplexing method of a SOC as claimed in claim 1, characterized in that: In step S1, a flexible and reusable IDRAM is used to expand the IRAM and DRAM in time-sharing to save hardware overhead; IDRAM is used as DRAM expansion by default; by reserving address space separately, IDRAM can be accessed normally as expansion in both usage scenarios.

3. The RAM multiplexing method of a SOC as claimed in claim 1, characterized in that: In step S2, the size of IDRAM should be evaluated according to actual needs, and its area should be reduced as much as possible while ensuring functionality; in order to achieve time-sharing multiplexing of IDRAM, address space needs to be reserved in the operating system so that it can be accessed normally when used as IRAM and DRAM; there are many ways to reserve address space, dividing the address space of IDRAM into multiple segments, and each segment is mapped to the address space of IRAM or DRAM respectively.

4. The RAM multiplexing method of a SOC as claimed in claim 1, characterized in that: In the step S4, a 1-bit IDRAM_sel register is added to select the actual function of the IDRAM; after the system is powered on, when the IDRAM_sel register is not configured in the default state, the IDRAM is used as a DRAM to store data required by the system; and according to changes in actual usage scenarios, the function of the IDRAM will be flexibly changed; if the function of the IDRAM needs to be changed, the register IDRAM_sel needs to be written by the CPU to change the corresponding address space and usage status; after the writing is correct, the internal hardware logic will combine the IDRAM_sel register and the bus access address to redirect the data, communicate with the instruction bus or the data bus, and complete the conversion of different address spaces of the IRAM.

5. The RAM multiplexing method of a SOC as claimed in claim 1, characterized in that: In the step S5, when the IDRAM_sel register is "0" or "1", the IDRAM is time-division multiplexed.

6. The RAM multiplexing method of a SOC as claimed in claim 1, characterized in that: In step S3, reserving address space in IDRAM is the key to realizing RAM time-sharing multiplexing; there are multiple ways to reserve address space, dividing the address space of IDRAM into multiple segments, and each segment is mapped to the address space of IRAM or DRAM respectively.

7. The RAM multiplexing method of a SOC as claimed in claim 1, characterized in that: In step S6, the CPU writes a value to the IDRAM_sel register to change the function of the IDRAM; if an application requires a larger IRAM space, the value of the IDRAM_sel register is set to "1" to use the IDRAM as IRAM; this is a flexible way to change the function of the IDRAM.

8. The RAM multiplexing method of a SOC as claimed in claim 1, characterized in that: In step S7, when the CPU reads an instruction from the IDRAM, it maps its address to the address space of the IRAM.

9. The RAM multiplexing method of a SOC as claimed in claim 1, characterized in that: In step S8, when the CPU accesses data in the IDRAM, the address thereof is mapped to the address space of the DRAM.

10. The RAM multiplexing method of a SOC as claimed in claim 1, characterized in that: In step S9, the IDRAM is flexibly allocated to the IRAM or DRAM according to the requirements of the actual application scenario.

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