Multiplier based on radix-4Booth coding and improved Wallace compression tree

Abstract

The invention relates to a multiplier based on radix-4Booth coding and an improved Wallace compression tree, and the multiplier comprises a partial product generation module which recodes an input multiplier into a plurality of partial products through employing a Radix-4Booth algorithm, and forms a compact partial product array; the partial product compression module is used for quickly compressing the partial product through two compressors by utilizing an improved Wallace tree compression structure, and reducing the calculation path delay; and the final summation module is used for summing the compressed partial product by using a high-speed summator to obtain a final multiplication result. According to the invention, a radix-4Booth coding algorithm is adopted, so that a partial product array is regularly arranged, the circuit area is reduced, a new tree type compression structure in which a 3-2 compressor and a 4-2 compressor are mixed is adopted to realize a Wallace tree, the compression efficiency is improved, and the key delay is reduced.

Description

Technical Field

[0001] The invention relates to the field of electronic devices, and in particular to a multiplier based on base-4 Booth coding and improved Wallace compression tree. Background Art

[0002] Multipliers are widely used in digital systems, and usually have problems of high power consumption and long delay. Currently, there are two main efficient and low-power multiplier algorithms and architectures: Booth and Wallace tree structures. The Booth algorithm encodes the continuous bits of the multiplier and generates addition and subtraction operations to reduce the number of partial products, thereby improving the multiplication speed. Common Booth algorithms based on Radix-4 and Radix-8 are suitable for processing numbers with many consecutive identical bits. The Wallace tree structure uses parallel processing and multi-level compression to improve the multiplication speed. It generates a partial product matrix, then uses a multi-level adder with a tree structure to compress the partial product, and finally uses a high-speed multiplier to sum the multiplication results. However, the existing multipliers have a large number of adders and a complex structure, and there are still large resource consumption and delay problems in the partial product generation and compression process. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a multiplier based on radix-4 Booth coding and improved Wallace compression tree to solve the shortcomings of the prior art.

[0004] The object of the present invention is achieved by the following technical scheme: a multiplier based on base-4 Booth coding and improved Wallace compression tree, the multiplier comprising a partial product generation module, a partial product compression module and a final summation module;

[0005] The partial product generation module: re-encodes the input multiplier into multiple partial products by adopting the Radix-4 Booth algorithm to form a compact partial product array;

[0006] The partial product compression module: by utilizing an improved Wallace tree compression structure, the partial product is quickly compressed by two compressors to reduce the computation path delay;

[0007] The final summation module uses a high-speed adder to sum the compressed partial products to obtain a final multiplication result.

[0008] The Radix-4 Booth algorithm recodes the multipliers and generates corresponding control signals. According to the number of multipliers, three multipliers are grouped as one group, and two groups overlap by one. Each group is divided into two groups according to B=B. n-1 ×(-2) n-1 +Bn-2 ×2 n-2 +…+B1×2 1 +B0×2 0 +B -1 The encoding is performed in a manner of , where B represents the multiplier.

[0009] The two compressors include a carry-save adder and a one-bit full adder with carry, and the critical paths of the two compressors have a delay of 2 XOR gates.

[0010] The improved Wallace tree compression structure consists of two carry-preserved adders and two one-bit full adders with carry; the partial product generation module generates a total of 8 partial products P0-P8, the partial products of P0 and P1 are added by 1 and input into the first carry-preserved adder, the partial product of P1 is directly input into the first carry-preserved adder, the partial products of P3-P5 are input into the second carry-preserved adder, the two carry-preserved adders are both input into the first one-bit full adder with carry, and the first one-bit full adder with carry and the partial products of P6 and P7 are input into the second one-bit full adder with carry.

[0011] The present invention has the following advantages: a multiplier based on radix-4 Booth coding and improved Wallace compression tree, adopting radix-4 Booth coding algorithm to arrange partial product arrays regularly, reducing circuit area, adopting a new tree compression structure mixed with 3-2 and 4-2 compressors to realize Wallace tree, improving compression efficiency and reducing key delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a structural schematic diagram of the present invention;

[0013] Figure 2 It is a schematic diagram of the partial product summation structure;

[0014] Figure 3 It is the optimized XOR gate logic circuit diagram;

[0015] Figure 4 This is the optimized 3-2 compressor logic circuit diagram;

[0016] Figure 5 This is a schematic diagram of the improved Wallace tree compression structure;

[0017] Figure 6 Schematic diagram of the compression process of the addition tree. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided below in conjunction with the drawings is not intended to limit the scope of protection of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application. The present invention is further described below in conjunction with the drawings.

[0019] like Figure 1 As shown, the present invention specifically relates to a multiplier based on radix-4 Booth coding and improved Wallace compression tree, which is used for multiplication of two 16-bit signed numbers, including the generation of partial products, compression of partial products, and the fast summation of two groups of partial products at the end; in order to obtain a partial product array with good tree structure compression, radix-4 Booth coding is used in the partial product generation module, and a compact and regular array composed of 8 partial products is generated from two 16-bit binary numbers. The improved Wallace tree structure is used in the partial product compression module to quickly compress the partial product array. The structure rearranges the optimized 3-2 compressor and 4-2 compressor according to the number of partial products, and the formed compression structure has a small critical path delay and low resource consumption.

[0020] The present invention adopts base-4 Booth multiplication, and then uses Booth coding for one hot coding to select one of four partial products. Compared with traditional multiplication operation (or base-2 Booth), base-4 Booth multiplication only requires n / 2-1 additions, where n is the bit width, which greatly speeds up the speed.

[0021] The radix-4 Booth encoding algorithm is implemented by the formula

[0022] B=B n-1 ×(-2) n-1 +B n-2 ×2 n-2 +…+B1×2 1 +B0×2 0 +B -1 The multiplier is re-encoded and the corresponding control signal is generated, as shown in Table 1. For a 16-bit multiplier, a 0 is added to the lowest bit to become a 17-bit number. The multiplier is divided into 8 groups in the manner of three bits as a group and two groups overlap by one bit. Each group is re-encoded according to Table 1, where B represents the multiplier, A represents the multiplicand, and B represents the digit.i-1 , B i , B i+1 All are 1-digit numbers, so there are only 8 possible partial products.

[0023] Table 1. Booth coding table

[0024] <![CDATA[B i+1 ]]> <![CDATA[B i ]]> <![CDATA[B i-1 ]]> <![CDATA[-2B i-1 +B i +B i-1 ]]> PP 0 0 0 +0 0 0 0 1 +1 +A 0 1 0 +1 +A 0 1 1 +2 +2A 1 0 0 -2 -2A 1 0 1 -1 -A 1 1 0 -1 -A 1 1 1 -0 0

[0025] Therefore, for multiplication of any number of bits, at most w+1+3=w+4 bits are needed to determine each partial product (the remaining bits are all 0), where w represents the bit width of the multiplier (multiplicand), that is, the number of bits of the operand. Figure 2 As shown, h is the mantissa, s represents the sign bit of the final partial product, which is obtained by the exclusive OR operation of the sign bit of the original multiplicand and the + / - (1 is +, 0 is -) of the multiplicand.

[0026] The 3-2 compressor is a carry-preserving adder, and the 4-2 compressor is a one-bit full adder with carry. There are two XOR gates (exclusive OR gates) delay on its critical path, and its logical expression is: and Sum means sum, C out Indicates output carry, C in Indicates input borrow, such as Figure 3 and Figure 4 As shown, parts and items can be output to the next level.

[0027] like Figure 5 As shown in the figure, P0 to P7 are 8 partial products generated by the partial product generation module. This structure uses a combination of full adders and half adders. Through parallel operation, the compression of 8 partial products only uses 2 CSAs (3-2 compressors after line optimization) and 2 4-2 compressors, which shortens the path length of the addition operation. In addition, it also has corresponding scalability and can be easily applied to higher bit width calculations.

[0028] The addition tree compression process based on the above improved compression structure is as follows: Figure 6 As shown, the whole is divided into 5 parts: add1_7, 32A, 32B, 42A, and 42B, where the blank circle represents data 0, h represents the plus-one signal added after the partial product in pp_generate, the solid circle, C, and S represent data or generated data, HA indicates that a half adder is used, FA indicates that a full adder is used, and the black frame marked with a 42 compressor represents that a 4-2 compressor is used for addition operations.

[0029] In the add1_7 part, pp0 and pp1 are 21-bit input signals. The plus-one signal of the eighth partial product is placed at the 15th bit. Six half adders are used at HA to generate S1-S6 and C1-C6. The weight of signal C is 2 and needs to be shifted left by one bit. Therefore, the 15th bit pp0_1 will be left empty and filled with the plus-one signal h to output the new 21-bit pp0_1 and pp1_1.

[0030] During the 32A compression process, the add1_7 method is used at the 3rd and 4th bits to use 2 half adders to fill in the plus-one signal, and 17 full adders are used at the 5th to 21st bits to implement the 3-to-2 process, and the full adders will generate C and S signals. During the 32B module compression process, the low bits only have data of two signals, which are directly output. The 9th and 10th bits use 2 half adders, the 11th to 25th bits use 15 full adders, the 26th and 27th bits use half adders, and the above-mentioned carry left shift is used, and then the blank space is filled with data to implement the 32B 3-to-2 operation.

[0031] In the 42A module part, the data of the 5th and 6th bits are shifted left with a carry, and Cout is used as the carry of the 24th full adder to achieve 4-2 compression. The carry is shifted left and the blank is filled with the carry of the half adder. This method is used to achieve 4-2 reduction. The 4-2 compressor at the 29th bit will generate three signals Cout, C, and S, among which C is shifted left by one bit and S is retained. Cout is used as the carry of the 30th full adder to achieve 4-2 compression, and the 31st bit uses a half adder to achieve 3-2 reduction.

[0032] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used for various other combinations, modifications and improvements, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A multiplier based on radix-4 Booth coding and improved Wallace compression tree, characterized in that: The multiplier includes a partial product generation module, a partial product compression module and a final summation module; The partial product generation module: re-encodes the input multiplier into multiple partial products by adopting the Radix-4 Booth algorithm to form a compact partial product array; The partial product compression module: by utilizing an improved Wallace tree compression structure, the partial product is quickly compressed by two compressors to reduce the computation path delay; The final summation module uses a high-speed adder to sum the compressed partial products to obtain a final multiplication result.

2. A multiplier based on base-4 Booth coding and improved Wallace compression tree according to claim 1, characterized in that: The Radix-4 Booth algorithm recodes the multipliers and generates corresponding control signals. According to the number of multipliers, three multipliers are grouped as one group, and two groups overlap by one. Each group is divided into two groups according to B=B. n-1 ×(-2) n-1 +B n-2 ×2 n-2 +…+B1×2 1 +B0×2 0 +B -1 The encoding is performed in a manner of , where B represents the multiplier.

3. A multiplier based on radix-4 Booth coding and improved Wallace compression tree according to claim 1, characterized in that: The two compressors include a carry-save adder and a one-bit full adder with carry, and the critical paths of the two compressors have a delay of 2 XOR gates.

4. A multiplier based on radix-4 Booth coding and improved Wallace compression tree according to claim 3, characterized in that: The improved Wallace tree compression structure consists of two carry-preserved adders and two one-bit full adders with carry; the partial product generation module generates a total of 8 partial products P0-P8, the partial products of P0 and P1 are added by 1 and input into the first carry-preserved adder, the partial product of P1 is directly input into the first carry-preserved adder, the partial products of P3-P5 are input into the second carry-preserved adder, the two carry-preserved adders are both input into the first one-bit full adder with carry, and the first one-bit full adder with carry and the partial products of P6 and P7 are input into the second one-bit full adder with carry.

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