Software and hardware communication method, system and equipment supporting multiple FPGAs (Field Programmable Gate Array), and storage medium
By creating a communication model in a multi-piece FPGA emulator and achieving accurate mapping of signal data, the problem of inaccurate communication of software and hardware in the prior art is solved, and seamless collaboration and efficient simulation of software and hardware are achieved.
Patent Information
- Application Number
- CN202411588913.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-02-14
AI Technical Summary
In the emulator of multi-chip FPGA, the prior art is difficult to achieve accuracy and seamless collaboration of software and hardware communication, resulting in incomplete and inaccurate data transmission and inaccurateness of seamless collaboration.
By creating a communication model, including the mapping relationship of signals on the FPGA chip, flexible binding between the software side and multiple FPGAs is achieved. The software side unit interacts with the test platform unit through the API interface, grabs signal data, and converts formats through Adapter. The software and hardware communication unit determines the target FPGA chip corresponding to the signal data according to the communication model and transmits the data through the PCIE interface.
It realizes accurate mapping between user design and multi-piece FPGA, ensures accurate data transmission between software and hardware, realizes seamless coordination between software and hardware, and improves simulation efficiency and accuracy.
Smart Images
Figure CN119442995A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of software-hardware collaborative simulation, and in particular to a method, system, device and storage medium supporting multi-chip FPGA software-hardware communication. Background Art
[0002] FPGA, the full name of Field Programmable Gate Array, is an integrated chip mainly based on digital circuits, and is also a type of programmable logic device (PLD). Software-hardware communication is a basic and key field in computer science and information technology. It mainly focuses on the information exchange process between computer hardware and software. Software-hardware communication involves multiple aspects such as the interface and protocol between hardware and software, data representation, signal and timing. Through mechanisms such as operating systems, drivers, communication buses and network communications, communication between software and hardware is achieved, thereby supporting the operation of various complex computing tasks and applications.
[0003] Because the simulator of a single FPGA has limitations, mainly reflected in the limited resources of a single FPGA such as logic units, registers, memory blocks, DSP modules, etc., in order to make large or complex system designs run normally, most of the existing technologies use simulators with multiple FPGAs. However, when multiple FPGAs are used for software and hardware communication, large or complex system designs need to transmit more data. Under the existing technology, problems such as incomplete and inaccurate data transmission and inability to seamlessly coordinate software and hardware are prone to occur in software and hardware interaction. Summary of the invention
[0004] In order to achieve accurate mapping between user design and multiple FPGAs so that data can be accurately transmitted between software and hardware, the present application provides a method, system, device and storage medium that supports software and hardware communication on multiple FPGAs.
[0005] In the first aspect, the present application provides a method for supporting multi-chip FPGA hardware and software communication, using the following technical solution:
[0006] The method is based on a software-hardware communication system, which includes a test platform unit containing hardware design code, a software side unit for transmitting and processing data, a software-hardware communication unit and a hardware FPGA unit, and the method includes:
[0007] The software and hardware communication unit creates a communication model, wherein the communication model includes a mapping relationship between the signals on the FPGA chip;
[0008] The software side unit performs data interaction with the hardware design code of the test platform unit through an API interface during the simulation process, and captures signal data generated by the data interaction;
[0009] The software side unit converts the format of the signal data through an Adapter;
[0010] The software side unit transmits the converted signal data to the software and hardware communication unit;
[0011] The hardware and software communication unit determines the target FPGA chip corresponding to the converted signal data according to the communication model;
[0012] The software and hardware communication unit transmits the converted signal data to the hardware FPGA unit through the PCIE interface.
[0013] Through the above technical solution, accurate mapping between user design and multiple FPGAs can be achieved, so that data can be accurately transmitted between software and hardware, ensuring that the software and hardware can work together seamlessly and can simulate the entire system efficiently and accurately.
[0014] In a specific implementation scheme, the software and hardware communication unit creates a communication model including:
[0015] The software and hardware communication unit obtains a signal file, and parses signal information of multiple signals in the signal file, wherein the signal information is used to determine a channel corresponding to transmitting the signal;
[0016] The software and hardware communication unit obtains a channel parameter file and parses a channel configuration in the channel parameter file, wherein the channel configuration includes a correspondence between a signal transmission channel and an FPGA chip in data transmission;
[0017] The software and hardware communication unit creates a communication model according to the signal information and the channel configuration.
[0018] Through the above technical solution, establishing a communication model can clarify the mapping relationship between different signals on multiple FPGAs. Establishing the model in advance can help FPGA software and hardware communication be more accurate and faster.
[0019] In a specific implementation scheme, the signal data generated by the crawling data interaction includes:
[0020] The software-side unit determines target signal information of the signal data according to the signal file, wherein the target signal information includes a target transmission channel of the signal data;
[0021] The software-side unit inputs signal data through the target transmission channel.
[0022] Through the above technical solution, setting up a transmission channel for signal data can enable software and hardware to communicate. At the same time, each signal has a corresponding transmission channel, which is more conducive to accurate data transmission between software and hardware.
[0023] In a specific implementation scheme, the software and hardware communication unit determines the target FPGA chip corresponding to the converted signal data according to the communication model, including:
[0024] The software and hardware communication unit determines the target FPGA chip agent bound to the target transmission channel according to the communication model;
[0025] The software and hardware communication unit determines the target FPGA chip corresponding to the converted signal data through the target FPGA chip agent.
[0026] Through the above technical solution, accurate mapping between signal data and multiple FPGAs is achieved, so that data can be accurately transmitted between software and hardware.
[0027] In a specific implementation scheme, after determining the target FPGA chip corresponding to the converted signal data according to the communication model, the method further includes:
[0028] The software and hardware communication unit establishes a ServiceLoop module, which is responsible for managing and scheduling data transmission tasks.
[0029] Through the above technical solution, the ServiceLoop module cyclically checks whether there is data that needs to be transmitted between software and hardware, and triggers related tasks according to simulation requirements to avoid data loss or delay. Through efficient task scheduling, ServiceLoop ensures the real-time and accuracy of simulation.
[0030] In a specific implementation scheme, after the software and hardware communication unit transmits the converted signal data to the hardware FPGA unit through the PCIE interface, the method further includes:
[0031] The hardware FPGA unit performs simulation according to the converted signal data to obtain hardware simulation data;
[0032] The hardware FPGA unit transmits the hardware simulation data to the software side unit through the PCIE channel;
[0033] The software side unit converts the format of the hardware simulation data through the Adapter to obtain verification data, and transmits the verification data to the test platform unit;
[0034] The test platform unit verifies whether the user design meets expectations based on the verification data and the signal data.
[0035] Through the above technical solution, when designing a large or complex system design, data verification can ensure that the mapping between the user design and multiple FPGAs is accurate, there are no errors in the software and hardware communication, and the entire system can be accurately simulated.
[0036] In a specific implementation scheme, the test platform unit verifies whether the user design meets expectations based on the verification data and the signal data, including:
[0037] The test platform unit analyzes the signal data and the verification data to determine whether the signal data and the verification data are consistent;
[0038] If the signal data and the verification data are consistent, it is determined that the verification user design meets expectations;
[0039] If the signal data and verification data are inconsistent, the verification user design does not meet expectations.
[0040] Through the above technical solution, a specific verification method is provided, which makes the verification process clearer and more specific, and determines more accurately whether the operation of the multi-chip FPGA hardware and software communication method is wrong.
[0041] In a second aspect, the present application provides a multi-chip FPGA hardware and software communication system, which adopts the following technical solution: the system includes:
[0042] A software and hardware communication unit, used to create a communication model, wherein the communication model includes a mapping relationship between the signal on the FPGA chip;
[0043] A software side unit, the software side unit is used to perform data interaction with the hardware design code of the test platform unit through an API interface during the simulation process, and capture signal data generated by the data interaction;
[0044] A software side unit, the software side unit is used to convert the format of the signal data through an Adapter;
[0045] A software side unit, used to transmit the converted signal data to the software and hardware communication unit;
[0046] A software and hardware communication unit, used to determine a target FPGA chip corresponding to the converted signal data according to a communication model;
[0047] The software and hardware communication unit is used to transmit the converted signal data to the hardware FPGA unit through the PCIE interface.
[0048] In a third aspect, the present application provides a computer device, which adopts the following technical solution: it includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and executes the above-mentioned multi-FPGA hardware and software communication method.
[0049] In a fourth aspect, the present application provides a computer-readable storage medium, which adopts the following technical solution: storing a computer program that can be loaded by a processor and execute the above-mentioned multi-FPGA hardware and software communication method.
[0050] In summary, this application has the following beneficial technical effects:
[0051] When the simulators of multiple FPGAs perform software and hardware communication, the software side is flexibly bound to the multiple FPGAs by establishing a communication model, so that the user's complete hardware design can be mapped to multiple FPGAs, so that data can be accurately transmitted between software and hardware, ensuring that the software and hardware can work together seamlessly; this application simplifies the complex software and hardware interaction, allowing users to efficiently use multiple FPGAs to simulate complex systems; at the same time, the method of this application supports multi-FPGA simulation, and can handle large-scale data and complex computing tasks; during the simulation process, signal data is captured through the API interface, supporting high real-time and efficient simulation, significantly improving simulation efficiency, meeting diverse simulation needs, and simplifying user operations. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] Figure 1 It is a flow chart of the multi-FPGA hardware and software communication method in an embodiment of the present application.
[0053] Figure 2 It is a framework diagram of the multi-FPGA hardware and software communication method in the embodiment of the present application.
[0054] Figure 3 It is a schematic diagram of the communication model in the embodiment of the present application. DETAILED DESCRIPTION
[0055] The following is combined with Figure 1-3 This application is described in further detail.
[0056] The embodiment of the present application discloses a method for supporting software and hardware communication of multiple FPGAs, and the method is used for software and hardware communication in a simulator of multiple FPGAs.
[0057] FPGA, the full name of Field Programmable Gate Array, is an integrated chip mainly based on digital circuits, and is also a type of programmable logic device (PLD). Software-hardware communication is a basic and key field in computer science and information technology. It mainly focuses on the information exchange process between computer hardware and software. Software-hardware communication involves multiple aspects such as the interface and protocol between hardware and software, data representation, signal and timing. Through mechanisms such as operating systems, drivers, communication buses and network communications, communication between software and hardware is achieved, thereby supporting the operation of various complex computing tasks and applications.
[0058] Because the simulator of a single FPGA has limitations, mainly reflected in the limited resources of a single FPGA such as logic units, registers, memory blocks, DSP modules, etc., in order to make large or complex system designs run normally, most of the existing technologies use simulators with multiple FPGAs. However, when multiple FPGAs are used for software and hardware communication, large or complex system designs need to transmit more data. Under the existing technology, problems such as incomplete and inaccurate data transmission and inability to seamlessly coordinate software and hardware are prone to occur in software and hardware interaction.
[0059] Therefore, the present application proposes a method for supporting software and hardware communication of multiple FPGAs, and utilizes this method to more accurately implement software and hardware communication in a simulator of multiple FPGAs.
[0060] like Figure 1 As shown, the method specifically comprises the following steps:
[0061] S10, the software and hardware communication unit creates a communication model, and the communication model includes a mapping relationship between signals on the FPGA chip.
[0062] Specifically, the software and hardware communication unit creates a communication model before the simulation process begins. The communication model includes all possible signals that may appear in the simulation process, determines the transmission channel corresponding to each signal and the FPGA chip corresponding to each transmission channel, thereby obtaining the mapping relationship of the signal on the FPGA chip, and stores this information in the communication model for future use.
[0063] S20, during the simulation process, the software side unit interacts with the hardware design code of the test platform unit through the API interface to capture signal data generated by the data interaction.
[0064] Specifically, the hardware design code of a large or complex system design is stored in the test platform unit. When the system starts running, that is, the simulation starts, the hardware design code of the test platform unit starts running and generates signals. The software side unit interacts with the test platform unit through the API interface to capture the signal data generated during the data interaction.
[0065] S30, the software side unit converts the format of the signal data through the Adapter.
[0066] Specifically, the software side unit converts the software high-level data structure into a data format that can be recognized and processed by the hardware logic layer through the Adapter.
[0067] S40, the software side unit transmits the converted signal data to the software and hardware communication unit.
[0068] Specifically, the software-hardware communication unit is equivalent to a software-hardware collaborative interface for connecting the software side and the hardware side. To realize software-hardware communication, the converted signal data needs to be first transmitted to the software-hardware communication unit.
[0069] S50, the software and hardware communication unit determines the target FPGA chip corresponding to the converted signal data according to the communication model.
[0070] Specifically, the communication model contains the mapping relationship of all possible signals on the FPGA chip during the simulation process. After the software and hardware communication unit receives the signal data, it searches the communication model for the mapping relationship of the signal data on the FPGA chip to determine the target FPGA chip corresponding to the signal data.
[0071] S60, the software and hardware communication unit transmits the converted signal data to the hardware FPGA unit through the PCIE interface.
[0072] Specifically, the software and hardware communication unit connects the software side and the hardware side, determines the target FPGA chip corresponding to the signal data, and then transmits the signal data to the hardware side through the PCIE (Peripheral Component Interconnect Express) interface to complete the software and hardware communication of multiple FPGA chips.
[0073] Figure 2 The framework diagram of the multi-FPGA hardware and software communication method. The test platform unit interacts with the software unit data through the API. After receiving the signal data, the software unit converts the format of the signal data through the Adapter. Then the hardware and software communication unit determines the FPGA chip corresponding to the signal data through the communication model and transmits the signal data to the hardware FPGA unit.
[0074] In one embodiment, considering that the prior art involves large or complex system designs, too much signal data needs to be transmitted. If a signal data communication model is not established in advance, the transmission efficiency is low and the time is long during the software and hardware communication process.
[0075] In order to improve the communication efficiency of multiple FPGA hardware and software, the steps of creating a communication model by the hardware and software communication unit can be specifically performed as follows:
[0076] The software and hardware communication unit obtains the signal file and parses the signal information of multiple signals in the signal file. The signal information is used to determine the channel corresponding to the transmission signal. Specifically, first, the software and hardware communication unit obtains the signal file, which includes all possible signals that may appear in the simulation process, including but not limited to input, output and internal signals. Then, the signal information in the signal file is parsed. The transmission channel of each signal is determined according to the characteristics of the signal. The transmission channel may be a port or a pipe, so the signal information is used to determine the channel corresponding to the transmission signal.
[0077] The software and hardware communication unit obtains a channel parameter file and parses the channel configuration in the channel parameter file. The channel configuration includes the correspondence between the signal transmission channel and the FPGA chip in data transmission. Specifically, first, the software and hardware communication unit obtains the channel parameter file, which includes detailed information on software and hardware modeling. Then, the channel configuration in the channel parameter file is parsed, wherein the key information is the position information of the signal transmission channel on multiple FPGA chips, that is, the correspondence between the signal transmission channel and the FPGA chip, so the channel configuration can be used to determine the FPGA chip corresponding to the signal transmission channel.
[0078] The hardware and software communication unit creates a communication model based on signal information and channel configuration. Figure 3 ,The principle of the communication model is that the signal information is used to ,determine the channel corresponding to the transmission signal, and the channel ,configuration is used to determine the FPGA chip corresponding to the signal transmission ,channel configuration. Combining the signal information and the channel ,configuration can derive the mapping
[0079] The existing technology involves large or complex system designs, which require too much data to be transmitted. Building a model in advance helps FPGA software and hardware communicate more accurately and quickly.
[0080] In one embodiment, in order to better transmit signal data, the step of capturing signal data generated by data interaction can be specifically performed as follows:
[0081] The software side unit determines the target signal information of the signal data according to the signal file, and the target signal information includes the target transmission channel of the signal data. Specifically, the signal file includes all possible signals that may appear in the simulation process. The signal information determines the transmission channel of each signal according to the characteristics and requirements of the signal, so the transmission channel of the signal data can be determined according to the signal data. The software side unit inputs the signal data through the target transmission channel. Specifically, capturing the signal data is actually inputting the signal data into the software side unit, determining the target transmission channel, and transmitting the signal data to the software side unit to achieve data capture. It should be noted that the software side unit transmits the converted signal data to the software and hardware communication unit through the target transmission channel. Determining the target transmission channel and transmitting the signal data to the software and hardware communication unit is part of the operation of the communication model. By setting up a transmission channel for signal data, the software and hardware can communicate, and each signal has a corresponding transmission channel, which is more conducive to accurate data transmission between software and hardware.
[0082] In one embodiment, the step of the software and hardware communication unit determining the target FPGA chip corresponding to the converted signal data according to the communication model can be specifically performed as follows:
[0083] The software and hardware communication unit determines the target FPGA chip agent bound to the target transmission channel according to the communication model. Specifically, the software and hardware communication unit involves a binding mechanism: the transmission channel is bound to the corresponding FPGA chip agent. The binding mechanism is established based on the channel parameter file. The reason why the software and hardware communication unit is bound to the FPGA chip agent instead of the specific FPGA chip is that the software and hardware communication unit is used to connect the software side and the hardware side, and the specific FPGA chip belongs to the hardware side and does not belong to the software and hardware communication unit. The software and hardware communication unit determines the target FPGA chip corresponding to the converted signal data through the target FPGA chip agent. Each FPGA chip agent corresponds to a specific FPGA chip, so the target FPGA chip corresponding to the converted signal data can be determined through the target FPGA chip agent. At this time, accurate mapping between signal data and multiple FPGA chips is achieved, so that data can be accurately transmitted between software and hardware.
[0084] In one embodiment, in order to transmit the data completely to the hardware side and reduce omissions, after determining the target FPGA chip corresponding to the converted signal data according to the communication model, the following steps are also included:
[0085] The software and hardware communication unit establishes a ServiceLoop module, which is responsible for managing and scheduling data transmission tasks. Specifically, the ServiceLoop module is also called a service loop module. After the signal data is transmitted to the software and hardware communication unit and the FPGA chip to be transmitted is determined, the ServiceLoop module checks that the signal data needs to be transmitted to the hardware side, issues instructions for transmitting the signal data, and transmits the signal data to the hardware side. In addition, the ServiceLoop module cyclically checks whether there is data that needs to be transmitted between the software and hardware to avoid data loss or delay. Through efficient task scheduling, ServiceLoop ensures the real-time and accuracy of the simulation.
[0086] In one embodiment, in order to ensure the accuracy of software and hardware communication of multiple FPGAs, after the software and hardware communication unit transmits the converted signal data to the hardware FPGA unit through the PCIE interface, the following steps may be performed:
[0087] The hardware FPGA unit performs simulation according to the converted signal data to obtain hardware simulation data. Specifically, for example, the FPGA chip corresponding to the converted signal data A is FPGA chip 1. When the signal data A is transmitted to the FPGA chip 1 in the hardware FPGA unit, the FPGA chip 1 will perform hardware-side simulation according to the signal data A to obtain hardware simulation data 1; the hardware FPGA unit transmits the hardware simulation data to the software side unit through the PCIE channel. Specifically, in order to verify whether the mapping between the user design and multiple FPGA chips is accurate, it is necessary to transmit the hardware simulation data 1 back to the test platform unit for verification, so the hardware FPGA unit first transmits the hardware simulation data 1 to the software side unit through the PCIE channel; the software side unit transmits the hardware simulation data 1 to the software side unit through the PCIE channel. The format of the hardware simulation data is converted through the Adapter to obtain the verification data, and the verification data is transmitted to the test platform unit. Specifically, the data structure on the hardware side cannot be recognized and transmitted by the software side. The hardware simulation data 1 is first converted into the verification data A that can be recognized and transmitted by the software side through the Adapter, and the verification data A is transmitted to the test platform unit for verification; the test platform unit verifies whether the user design meets the expectations based on the verification data and the signal data. Specifically, the signal data is transmitted to the target FPGA chip through the target transmission channel. When the hardware simulation data of the target FPGA chip is transmitted back to the test platform unit through the software and hardware communication system, by comparing the verification data and the signal data, it can be verified whether the user design meets the expectations.
[0088] In one embodiment, the test platform unit verifies whether the user design meets expectations and is accurate based on the verification data and signal data. This step can be specifically performed as follows:
[0089] The test platform unit analyzes the signal data and the verification data to determine whether the signal data and the verification data are consistent. Specifically, if the user design meets expectations and there is no transmission error or data omission during software and hardware communication, the test platform unit can determine whether the user design meets expectations by whether the signal data and the verification data are consistent. Therefore, the test platform unit analyzes and first determines whether the signal data and the verification data are consistent; if the signal data and the verification data are consistent, the user design is determined to meet expectations. Specifically, when the signal data and the verification data are consistent, the user design runs as expected, and the user design is determined to meet expectations; if the signal data and the verification data are inconsistent, the user design is determined to not meet expectations. Specifically, when the signal data and the verification data are inconsistent, an error occurs during the operation of the user design, and the user design is determined to not meet expectations.
[0090] Based on the above method, the embodiment of the present application also discloses a multi-chip FPGA hardware and software communication system. The system includes the following modules:
[0091] A software and hardware communication unit, used to create a communication model, which includes the mapping relationship of signals on the FPGA chip;
[0092] The software side unit is used to interact with the hardware design code of the test platform unit through the API interface during the simulation process and capture the signal data generated by the data interaction;
[0093] The software side unit is used to convert the format of signal data through the Adapter;
[0094] The software side unit is used to transmit the converted signal data to the software and hardware communication unit;
[0095] A software and hardware communication unit, used for determining a target FPGA chip corresponding to the converted signal data according to a communication model;
[0096] The software and hardware communication unit is used to transmit the converted signal data to the hardware FPGA unit through the PCIE interface.
[0097] In one embodiment, the software and hardware communication unit is specifically used for the software and hardware communication unit to obtain a signal file, parse signal information of multiple signals in the signal file, the signal information is used to determine the channel corresponding to the transmission signal; the software and hardware communication unit obtains a channel parameter file, parses the channel configuration in the channel parameter file, the channel configuration includes the correspondence between the signal transmission channel in data transmission and the FPGA chip; the software and hardware communication unit creates a communication model according to the signal information and the channel configuration.
[0098] In one embodiment, the software side unit is specifically used for the software side unit to determine the target signal information of the signal data according to the signal file, the target signal information includes the target transmission channel of the signal data; the software side unit inputs the signal data through the target transmission channel.
[0099] In one embodiment, the software and hardware communication unit is specifically used to determine the target FPGA chip agent bound to the target transmission channel according to the communication model; the software and hardware communication unit determines the target FPGA chip corresponding to the converted signal data through the target FPGA chip agent.
[0100] In one embodiment, the software and hardware communication unit is specifically used to establish a ServiceLoop module, which is responsible for managing and scheduling data transmission tasks.
[0101] In one embodiment, a hardware FPGA unit is specifically used for simulating the hardware FPGA unit according to the converted signal data to obtain hardware simulation data; the hardware FPGA unit transmits the hardware simulation data to the software side unit through the PCIE channel; the software side unit converts the format of the hardware simulation data through the Adapter to obtain verification data, and transmits the verification data to the test platform unit; the test platform unit verifies whether the user design meets expectations based on the verification data and the signal data; the test platform unit analyzes the signal data and the verification data to determine whether the user design meets expectations; if the signal data and the verification data are consistent, it is determined that the user design meets expectations; if the signal data and the verification data are inconsistent, it is determined that the user design does not meet expectations.
[0102] The embodiment of the present application also discloses a computer device.
[0103] Specifically, the computer device includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and execute the above-mentioned multi-FPGA hardware and software communication method.
[0104] The embodiment of the present application also discloses a computer-readable storage medium.
[0105] Specifically, the computer-readable storage medium stores a computer program that can be loaded by a processor and execute the multi-FPGA hardware and software communication method mentioned above. The computer-readable storage medium includes, for example: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.
Claims
1. A method for supporting software and hardware communication of multiple FPGAs, characterized in that: The method is based on a software-hardware communication system, which includes a test platform unit containing hardware design code, a software side unit for transmitting and processing data, a software-hardware communication unit and a hardware FPGA unit, and the method includes: The software and hardware communication unit creates a communication model, wherein the communication model includes a mapping relationship between the signals on the FPGA chip; The software side unit performs data interaction with the hardware design code of the test platform unit through an API interface during the simulation process, and captures signal data generated by the data interaction; The software side unit converts the format of the signal data through an Adapter; The software side unit transmits the converted signal data to the software and hardware communication unit; The hardware and software communication unit determines the target FPGA chip corresponding to the converted signal data according to the communication model; The software and hardware communication unit transmits the converted signal data to the hardware FPGA unit through the PCIE interface.
2. The method according to claim 1, characterized in that: The software and hardware communication unit creates a communication model including: The software and hardware communication unit obtains a signal file, and parses signal information of multiple signals in the signal file, wherein the signal information is used to determine a channel corresponding to transmitting the signal; The software and hardware communication unit obtains a channel parameter file and parses a channel configuration in the channel parameter file, wherein the channel configuration includes a correspondence between a signal transmission channel and an FPGA chip in data transmission; The software and hardware communication unit creates a communication model according to the signal information and the channel configuration.
3. The method according to claim 2, characterized in that: The signal data generated by the captured data interaction includes: The software-side unit determines target signal information of the signal data according to the signal file, wherein the target signal information includes a target transmission channel of the signal data; The software-side unit inputs signal data through the target transmission channel.
4. The method according to claim 3, characterized in that: The hardware and software communication unit determines the target FPGA chip corresponding to the converted signal data according to the communication model, including: The software and hardware communication unit determines the target FPGA chip agent bound to the target transmission channel according to the communication model; The software and hardware communication unit determines the target FPGA chip corresponding to the converted signal data through the target FPGA chip agent.
5. The method according to claim 1, characterized in that: After determining the target FPGA chip corresponding to the converted signal data according to the communication model, the method further includes: The software and hardware communication unit establishes a ServiceLoop module, which is responsible for managing and scheduling data transmission tasks.
6. The method according to claim 1, characterized in that: After the software and hardware communication unit transmits the converted signal data to the hardware FPGA unit through the PCIE interface, it also includes: The hardware FPGA unit performs simulation according to the converted signal data to obtain hardware simulation data; The hardware FPGA unit transmits the hardware simulation data to the software side unit through the PCIE channel; The software side unit converts the format of the hardware simulation data through the Adapter to obtain verification data, and transmits the verification data to the test platform unit; The test platform unit verifies whether the user design meets expectations based on the verification data and the signal data.
7. The method according to claim 6, characterized in that: The test platform unit verifies whether the user design meets expectations according to the verification data and the signal data, including: The test platform unit analyzes the signal data and the verification data to determine whether the signal data and the verification data are consistent; If the signal data is consistent with the verification data, it is determined that the user design meets expectations; If the signal data and the verification data are inconsistent, it is determined that the user design does not meet expectations.
8. A multi-chip FPGA hardware and software communication system, characterized in that: The system comprises: A software and hardware communication unit, used to create a communication model, wherein the communication model includes a mapping relationship between the signal on the FPGA chip; A software side unit, the software side unit is used to perform data interaction with the hardware design code of the test platform unit through an API interface during the simulation process, and capture signal data generated by the data interaction; A software side unit, the software side unit is used to convert the format of the signal data through an Adapter; A software side unit, used to transmit the converted signal data to the software and hardware communication unit; A software and hardware communication unit, used to determine a target FPGA chip corresponding to the converted signal data according to a communication model; The software and hardware communication unit is used to transmit the converted signal data to the hardware FPGA unit through the PCIE interface.
9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and executes the method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method according to any one of claims 1 to 7.