Display device

Abstract

A display device includes: a display panel including pixels connected to light emission control lines; and a light emission control driver including a light emission control stage providing a light emission control signal to the pixels through the light emission control line, in which the light emission control stage includes: a first light emission control transistor including a first electrode connected to the light emission control line, a gate electrode connected to a first light emission control clock line, and a second electrode connected to a first node; a first power supply voltage line to which a first power supply voltage is applied; and a shield pattern extending between the first light emission control transistor and the first power supply voltage line and receiving a power supply voltage higher than the first power supply voltage.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] The display device includes a pixel and a driver for driving the pixel. The driver includes a plurality of transistors and a power supply voltage line to which a power supply voltage is applied. When the transistor is arranged near the power supply voltage line, the presence of the power supply voltage line sometimes causes the threshold voltage of the transistor to drift. Accordingly, the reliability of the driver may deteriorate. Summary of the invention

[0003] The embodiment provides a display device including a driver having improved reliability.

[0004] A display device according to an embodiment includes: a display panel including pixels connected to a light emitting control line; and a light emitting control driver including a light emitting control stage providing a light emitting control signal to the pixels through the light emitting control line.

[0005] In an embodiment, the light emitting control stage may include: a first light emitting control transistor, including a first electrode connected to a light emitting control line, a gate electrode connected to a first light emitting control clock line, and a second electrode connected to a first node; a first power supply voltage line, to which a first power supply voltage is applied; and a shielding pattern, extending between the first light emitting control transistor and the first power supply voltage line and receiving a power supply voltage higher than the first power supply voltage.

[0006] In an embodiment, the light emission control stage may further include a second power supply voltage line to which a second power supply voltage higher than the first power supply voltage is applied.

[0007] In an embodiment, the shielding pattern is connected to the second power supply voltage line through a contact hole.

[0008] In an embodiment, the light emission control stage may further include a first capacitor including a first electrode connected to the second power supply voltage line and a second electrode connected to the second node.

[0009] In an embodiment, the shielding pattern may be disposed at the same layer as the second electrode of the first capacitor.

[0010] In an embodiment, the light emission control stage may further include a second light emission control transistor including a first electrode connected to the first power supply voltage line, a gate electrode connected to the third node, and a second electrode connected to the fourth node.

[0011] In an embodiment, the shielding pattern may further extend between the second light emission control transistor and the first power supply voltage line.

[0012] In an embodiment, the light emission control stage may further include a third light emission control transistor including a first electrode connected to the fifth node, a gate electrode connected to the first power supply voltage line, and a second electrode connected to the sixth node.

[0013] In an embodiment, the shielding pattern may further extend between the third light emission control transistor and the first power supply voltage line.

[0014] In an embodiment, the first power voltage line may extend in the first direction.

[0015] In an embodiment, the shielding pattern may include a first portion extending in a first direction and a second portion extending in a second direction crossing the first direction.

[0016] In an embodiment, the light emission control stage may further include a light emission prevention signal line receiving a light emission prevention signal.

[0017] In an embodiment, the second portion of the shielding pattern may partially overlap the light emission preventing signal line.

[0018] In an embodiment, the first portion of the shielding pattern may be disposed between the first light emission control transistor and the first power supply voltage line.

[0019] According to an embodiment, a display device includes: an active pattern including a first area, a second area spaced apart from the first area, and a first channel area disposed between the first area and the second area; a first gate electrode disposed on the active pattern; a second gate electrode disposed on the first gate electrode and including a 2-1 sub-gate electrode and a 2-2 sub-gate electrode; a first light emitting control clock line disposed on the second gate electrode and extending in a first direction; a first power supply voltage line disposed on the second gate electrode, extending in the first direction and receiving a first power supply voltage; a second power supply voltage line disposed on the second gate electrode, extending in the first direction and receiving a second power supply voltage higher than the first power supply voltage; a light emitting control line disposed on the first power supply voltage line, connected to the first area of ​​the active pattern and receiving a light emitting control signal; and a first light emitting control transistor including a first channel area of ​​the active pattern, the first area of ​​the active pattern, the second area of ​​the active pattern, and a portion of the first gate electrode overlapping with the first channel area of ​​the active pattern.

[0020] In an embodiment, the 2-1 sub-gate electrode may extend between the first channel region of the active pattern and the first power supply voltage line.

[0021] In an embodiment, the 2-1 sub-gate electrode may include a first portion extending in a first direction and a second portion extending in a second direction crossing the first direction.

[0022] In an embodiment, a first portion of the 2-1 sub-gate electrode may extend to be disposed between a first channel region of the active pattern and a first power supply voltage line.

[0023] In an embodiment, the display device may further include a light emission preventing signal line to which the light emission preventing signal is applied.

[0024] In an embodiment, a second portion of the 2-1 sub-gate electrode may partially overlap the light emission preventing signal line and may be connected to the second power supply voltage line through a contact hole.

[0025] In an embodiment, the active pattern may further include a third region connected to the first power supply voltage line, a fourth region spaced apart from the third region, and a second channel region disposed between the third region and the fourth region.

[0026] In an embodiment, the display device may further include a second light emission control transistor including a second channel region of the active pattern, a third region of the active pattern, a fourth region of the active pattern, and a portion of the first gate electrode overlapping the second channel region of the active pattern.

[0027] In an embodiment, the first portion of the 2-1 sub-gate electrode may further extend between the second channel region of the active pattern and the first power supply voltage line.

[0028] In an embodiment, the active pattern may further include a fifth region, a sixth region spaced apart from the fifth region, and a third channel region disposed between the fifth region and the sixth region.

[0029] In an embodiment, the display device may further include a third light emission control transistor including a third channel region of the active pattern, a fifth region of the active pattern, a sixth region of the active pattern, and a portion of the first gate electrode overlapping the first channel region of the active pattern.

[0030] In an embodiment, the first portion of the 2-1 sub-gate electrode may further extend between the third channel region of the active pattern and the first power supply voltage line.

[0031] The display device according to the embodiment may include a light emission control driver. The light emission control driver may include at least one light emission control transistor disposed adjacent to the first power supply voltage line. In addition, the light emission control driver may include a shielding pattern extending to be disposed between the first power supply voltage line and the light emission control transistor. The shielding pattern may be connected to a second power supply voltage line to which a positive voltage is applied.

[0032] Since the shield pattern to which the positive voltage is applied is provided between the light emission control transistor and the first power supply voltage line, it is possible to prevent positive charges from accumulating on the upper portion of the substrate due to the first power supply voltage line to which the negative voltage is applied. Since the positive charges are prevented from accumulating on the upper portion of the substrate, it is possible to prevent the threshold voltage of the light emission control transistor from drifting negatively. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0034] Figure 1 is a plan view showing a display device according to an embodiment.

[0035] Figure 2 It is shown Figure 1 A block diagram of a display device.

[0036] Figure 3 It is shown in Figure 1 A cross-sectional view of a pixel included in a display device.

[0037] Figure 4 It is shown in Figure 2 A circuit diagram of a light emitting control driver included in a display device.

[0038] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 It is shown Figure 1 Layout diagram of a display device.

[0039] Fig.14 It is shown Figure 4 Layout diagram of the first light emission control stage and the second light emission control stage.

[0040] Fig.15 It is along Fig.13 A cross-sectional view taken along line II'.

[0041] Fig.16 It is along Fig.13 A cross-sectional view taken along line II-II'.

[0042] Fig.17 is a layout diagram showing a first light emission control stage and a second light emission control stage according to another embodiment. DETAILED DESCRIPTION

[0043] Hereinafter, a display device according to an embodiment will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0044] Figure 1 is a plan view showing a display device according to an embodiment. Figure 2 It is shown Figure 1 A block diagram of a display device.

[0045] refer to Figure 1 , the display device DD according to the embodiment may include a display area DA and a non-display area NDA. The display area DA may be defined as an area capable of generating light or displaying an image by adjusting the transmittance of light provided from an external light source. The non-display area NDA may be an area where an image is not displayed. In addition, the non-display area NDA may be disposed around at least a portion of the display area DA.

[0046] A plurality of pixels PX may be disposed in the display area DA. Each of the plurality of pixels PX may emit light. The plurality of pixels PX may be repeatedly arranged along a first direction DR1 and a second direction DR2 crossing the first direction DR1.

[0047] refer to Figure 1 and Figure 2 The driver may be disposed in the non-display area NDA. The driver may include a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a light emission control driver 600.

[0048] The display area DA may include a plurality of scan lines G1, G2, . . . , Gn, a plurality of data lines D1, D2, . . . , Dm, and a plurality of light emitting control lines E1, E2, . . . , En.

[0049] In addition, the display area DA may include a plurality of pixels PX11, PX12, ..., PX1m arranged in a first row, a plurality of pixels PX21, PX22, ..., PX2m arranged in a second row, and a plurality of pixels PXn1, PXn2, ..., PXnm arranged in an nth row.

[0050] Each of the plurality of scan lines G1, G2, ..., Gn and the plurality of light emission control lines E1, E2, ..., En may extend in the second direction DR2. In addition, each of the plurality of data lines D1, D2, ..., Dm may extend in the first direction DR1.

[0051] The driving controller 200 may receive input image data IMG and an input control signal CONT from an external device. According to an embodiment, the input image data IMG may include red image data, green image data, and blue image data. In another embodiment, the input image data IMG may further include white image data. In another embodiment, the input image data IMG may include magenta image data, yellow image data, and cyan image data.

[0052] The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0053] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0054] The driving controller 200 may generate a first control signal CONT1 based on the input control signal CONT. The driving controller 200 may output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0055] The driving controller 200 may generate a second control signal CONT2 based on the input control signal CONT. The driving controller 200 may output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0056] The driving controller 200 may generate a third control signal CONT3 based on the input control signal CONT. The driving controller 200 may output the third control signal CONT3 to the gamma reference voltage generator 400.

[0057] The driving controller 200 may generate a fourth control signal CONT4 based on the input control signal CONT. The driving controller 200 may output the fourth control signal CONT4 to the light emission control driver 600.

[0058] The driving controller 200 may generate a data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 500.

[0059] The gate driver 300 may generate a gate signal for driving the plurality of scan lines G1, G2, ..., Gn in response to the first control signal CONT1 input from the driving controller 200. The gate driver 300 may output the gate signal to the plurality of scan lines G1, G2, ..., Gn. For example, the gate signal may include a data initialization gate signal, a compensation gate signal, a data write gate signal, and the like.

[0060] The first scan line G1 may be electrically connected to each of the plurality of pixels PX11, PX12, ..., PX1m disposed in the first row. The first scan line G1 may transmit a gate signal to each of the plurality of pixels PX11, PX12, ..., PX1m disposed in the first row.

[0061] The second scan line G2 may be electrically connected to each of the plurality of pixels PX21, PX22, ..., PX2m disposed in the second row. The second scan line G2 may transmit a gate signal to each of the plurality of pixels PX21, PX22, ..., PX2m disposed in the second row.

[0062] The nth scan line Gn may be electrically connected to each of the plurality of pixels PXn1, PXn2, ..., PXnm disposed in the nth row. The nth scan line Gn may transmit a gate signal to each of the plurality of pixels PXn1, PXn2, ..., PXnm disposed in the nth row.

[0063] The gamma reference voltage generator 400 may generate the gamma reference voltage VGREF in response to the third control signal CONT3 input from the driving controller 200. The gamma reference voltage generator 400 may provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF may have a value corresponding to each of the data signals DATA.

[0064] In an embodiment, the gamma reference voltage generator 400 may be spaced apart from the data driver 500. In another embodiment, the gamma reference voltage generator 400 may be disposed in the driving controller 200. In another embodiment, the gamma reference voltage generator 400 may be disposed in the data driver 500.

[0065] The data driver 500 may receive a second control signal CONT2 and a data signal DATA from the driving controller 200. In addition, the data driver 500 may receive a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into an analog data voltage using the gamma reference voltage VGREF. The data driver 500 may output the analog data voltage to each of the plurality of data lines D1, D2, ..., Dm.

[0066] The first data line D1 may be electrically connected to each of the plurality of pixels PX11, PX21, ..., PXn1 disposed in the first column. The first data line D1 may transmit an analog data voltage to each of the plurality of pixels PX11, PX21, ..., PXn1 disposed in the first column.

[0067] The second data line D2 may be electrically connected to each of the plurality of pixels PX12, PX22, ..., PXn2 disposed in the second column. The second data line D2 may transmit an analog data voltage to each of the plurality of pixels PX12, PX22, ..., PXn2 disposed in the second column.

[0068] The mth data line Dm may be electrically connected to each of the plurality of pixels PX1m, PX2m, ..., PXnm disposed in the mth column. The mth data line Dm may transmit an analog data voltage to each of the plurality of pixels PX1m, PX2m, ..., PXnm disposed in the mth column.

[0069] The light emission control driver 600 may generate a light emission control signal in response to the fourth control signal CONT4 input from the driving controller 200. The light emission control driver 600 may output the light emission control signal to each of the plurality of light emission control lines E1, E2, . . . , En.

[0070] The first light emission control line E1 may be electrically connected to each of the plurality of pixels PX11, PX12, ..., PX1m disposed in the first row. The first light emission control line E1 may transmit a light emission control signal to each of the plurality of pixels PX11, PX12, ..., PX1m disposed in the first row.

[0071] The second light emission control line E2 may be electrically connected to each of the plurality of pixels PX21, PX22, ..., PX2m disposed in the second row. The second light emission control line E2 may transmit a light emission control signal to each of the plurality of pixels PX21, PX22, ..., PX2m disposed in the second row.

[0072] The nth light emission control line En may be electrically connected to each of the plurality of pixels PXn1, PXn2, ..., PXnm disposed in the nth row. The nth light emission control line En may transmit a light emission control signal to each of the plurality of pixels PXn1, PXn2, ..., PXnm disposed in the nth row.

[0073] exist Figure 2 In the embodiment, the gate driver 300 may be disposed in the non-display area NDA adjacent to the first side of the display area DA, and the light emission control driver 600 may be disposed in the non-display area NDA adjacent to the second side of the display area DA. However, the present disclosure is not limited to Figure 2Example arrangement of .

[0074] For example, the gate driver 300 and the light emission control driver 600 may be disposed in the non-display area NDA adjacent to the first side of the display area DA. In some embodiments, the gate driver 300 and the light emission control driver 600 may be integrally formed.

[0075] Figure 3 It is shown in Figure 1 A cross-sectional view of a pixel included in a display device.

[0076] refer to Figure 3 The pixel PX may include a substrate SUB, a barrier layer BAR, a buffer layer BUF, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, a through-hole insulating layer VIA, an active pattern PACT, a source electrode PSE, a first gate electrode PGE1, a second gate electrode PGE2, a drain electrode PDE, a pixel electrode PE, a pixel defining layer PDL, a light emitting layer EML, a common electrode CE, and an encapsulation layer TFE.

[0077] The substrate SUB may include a transparent material or an opaque material. The substrate SUB may be formed of a transparent resin substrate. Examples of the transparent resin substrate may include a polyimide substrate. In this case, the polyimide substrate may include a first organic layer, a first barrier layer, a second organic layer, and the like.

[0078] Alternatively, the substrate SUB may include a quartz substrate (eg, a synthetic quartz substrate, a fluorine-doped quartz substrate), a calcium fluoride substrate, a soda lime substrate, and / or an alkali-free glass substrate, etc. These substrates may be used alone or in combination with each other.

[0079] The barrier layer BAR may be disposed on the substrate SUB. The barrier layer BAR may prevent impurities from penetrating into the upper portion of the substrate SUB from the outside. For example, the barrier layer BAR may include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride. These materials may be used alone or in combination with each other. In addition, the barrier layer BAR may be formed into a single-layer structure or a multi-layer structure.

[0080] The buffer layer BUF may be disposed on the barrier layer BAR. The buffer layer BUF may prevent metal atoms or impurities from diffusing from the substrate SUB to the active pattern PACT.

[0081] In some embodiments, the buffer layer BUF may include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride, etc. These materials may be used alone or in combination with each other.

[0082] The active pattern PACT may be disposed on the buffer layer BUF. The active pattern PACT may include a source region, a drain region, and a channel region disposed between the source region and the drain region.

[0083] The active pattern PACT may include an inorganic semiconductor (eg, amorphous silicon, polycrystalline silicon, metal oxide semiconductor) and / or an organic semiconductor, etc. These materials may be used alone or in combination with each other.

[0084] The metal oxide semiconductor may include a binary compound ("AB") containing indium ("In"), zinc ("Zn"), gallium ("Ga"), tin ("Sn"), titanium ("Ti"), aluminum ("Al"), hafnium ("Hf"), zirconium ("Zr"), and / or magnesium ("Mg"), etc. x ”), ternary compounds (“AB x C y ”) and / or quaternary compounds (“AB x C y D z ")wait.

[0085] For example, the metal oxide semiconductor may include zinc oxide (“ZnO x ”), gallium oxide (“GaO x ”), tin oxide (“SnO x ”), indium oxide (“InO x ”), indium gallium oxide “(IGO”), indium zinc oxide (“IZO”), indium tin oxide (“ITO”), indium zinc tin oxide (“IZTO”) and / or indium gallium zinc oxide (“IGZO”). These materials may be used alone or in combination with each other.

[0086] The gate insulating layer GI may be disposed on the buffer layer BUF. The gate insulating layer GI may sufficiently cover the active pattern PACT.

[0087] For example, the gate insulating layer GI may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide, etc. These materials may be used alone or in combination with each other.

[0088] The first gate electrode PGE1 may be disposed on the gate insulating layer GI. The first gate electrode PGE1 may be disposed in a plan view (eg, in a direction parallel to the first direction DR1 (eg, see Figure 1 ) in a third direction DR3 intersecting the second direction DR2) overlaps with the channel region of the active pattern PACT.

[0089] The first gate electrode PGE1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, and / or a transparent conductive material, etc. Examples of the metal may include silver ("Ag"), molybdenum ("Mo"), aluminum ("Al"), tungsten ("W"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), and / or scandium ("Sc"), etc. These materials may be used alone or in combination with each other.

[0090] Examples of the conductive metal oxide may include indium tin oxide and / or indium zinc oxide, etc. These materials may be used alone or in combination with each other.

[0091] In addition, examples of metal nitrides may include aluminum nitride (“AlN x ”), tungsten nitride (“WN x ”) and / or chromium nitride (“CrN x ””), etc. These materials can be used alone or in combination with each other.

[0092] The first interlayer insulating layer ILD1 may be disposed on the gate insulating layer GI. The first interlayer insulating layer ILD1 may sufficiently cover the first gate electrode PGE1.

[0093] For example, the first interlayer insulating layer ILD1 may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide, etc. These materials may be used alone or in combination with each other.

[0094] The second gate electrode PGE2 may be disposed on the first interlayer insulating layer ILD1. The second gate electrode PGE2 may overlap the first gate electrode PGE1 in a plan view. The second gate electrode PGE2 may include the same material as that of the first gate electrode PGE1.

[0095] The second interlayer insulating layer ILD2 may be disposed on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may sufficiently cover the second gate electrode PGE2.

[0096] For example, the second interlayer insulating layer ILD2 may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide, etc. These materials may be used alone or in combination with each other.

[0097] The source electrode PSE may be disposed on the second interlayer insulating layer ILD2 . The source electrode PSE may be connected to the source region of the active pattern PACT through a first contact hole penetrating the gate insulating layer GI, the first interlayer insulating layer ILD1 , and the second interlayer insulating layer ILD2 .

[0098] The drain electrode PDE may be disposed on the second interlayer insulating layer ILD2 . The drain electrode PDE may be connected to the drain region of the active pattern PACT through a second contact hole penetrating the gate insulating layer GI, the first interlayer insulating layer ILD1 , and the second interlayer insulating layer ILD2 .

[0099] For example, the source electrode PSE may include a metal, an alloy, a metal nitride, a conductive metal oxide, and / or a transparent conductive material, etc. These materials may be used alone or in combination with each other. The drain electrode PDE may be formed by the same process as that of the source electrode PSE and may include the same material.

[0100] The via insulating layer VIA may be disposed on the second interlayer insulating layer ILD2. The via insulating layer VIA may sufficiently cover the source electrode PSE and the drain electrode PDE. In addition, the via insulating layer VIA may have a substantially flat top surface without generating steps around the source electrode PSE and the drain electrode PDE.

[0101] The via insulating layer VIA may include an organic material. For example, the via insulating layer VIA may include phenolic resin, acrylic resin, polyimide resin, polyamide resin, siloxane resin and / or epoxy resin, etc. These materials may be used alone or in combination with each other.

[0102] The pixel electrode PE may be disposed on the through-hole insulating layer VIA. The pixel electrode PE may be connected to the drain electrode PDE through a third contact hole penetrating the through-hole insulating layer VIA.

[0103] The pixel electrode PE may include a metal, an alloy, a metal nitride, a conductive metal oxide and / or a transparent conductive material, etc. These materials may be used alone or in combination with each other. In an embodiment, the pixel electrode PE may have a stacked structure including ITO / Ag / ITO. For example, the pixel electrode PE may operate as an anode.

[0104] The pixel defining layer PDL may be disposed on the via insulating layer VIA. The pixel defining layer PDL may cover a side portion of the pixel electrode PE. In addition, an opening exposing a portion of an upper surface of the pixel electrode PE may be defined in the pixel defining layer PDL.

[0105] For example, the pixel defining layer PDL may include an inorganic material or an organic material. In an embodiment, the pixel defining layer PDL may include an organic material such as an epoxy resin or a silicone resin. These materials may be used alone or in combination with each other. In another embodiment, the pixel defining layer PDL may further include a light shielding material including a black pigment and / or a black dye.

[0106] The light emitting layer EML may be disposed on the pixel electrode PE. The light emitting layer EML may include an organic material that emits light of a predetermined color. For example, the light emitting layer EML may include an organic material that emits red light. However, the present disclosure is not limited thereto, and the light emitting layer EML may emit light of a color different from red.

[0107] The common electrode CE may be disposed on the light emitting layer EML and the pixel defining layer PDL. The common electrode CE may include metal, alloy, metal nitride, conductive metal oxide and / or transparent conductive material, etc. These materials may be used alone or in combination with each other. The common electrode CE may operate as a cathode.

[0108] The encapsulation layer TFE may be disposed on the common electrode CE. The encapsulation layer TFE may prevent impurities and moisture from penetrating from the outside into the pixel electrode PE, the light emitting layer EML, and the common electrode CE. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer.

[0109] For example, the inorganic layer may include silicon oxide, silicon nitride and / or silicon oxynitride, etc. These materials may be used alone or in combination with each other. The organic layer may include a polymer cured product such as polyacrylate.

[0110] Although referenced Figure 3 An exemplary embodiment of the pixel PX is described, but the pixel PX is not limited to Figure 3 That is, the pixel PX may include all structures that receive an electrical signal and emit light having a brightness corresponding to the intensity of the electrical signal.

[0111] Figure 4 It is shown in Figure 2 A circuit diagram of a light emitting control driver included in a display device.

[0112] refer to Figure 2 and Figure 4 The light emission control driver 600 may include a plurality of light emission control stages. For example, the light emission control driver 600 may include a first light emission control stage STEG1 and a second light emission control stage STEG2.

[0113] Each of the plurality of light emission control stages may output a current light emission control signal based on a previous light emission control signal output from a previous light emission control stage. That is, the plurality of light emission control stages may be configured in the form of a shift register.

[0114] For example, the second light emitting control stage STEG2 may output a second light emitting control signal based on the first light emitting control signal output from the first light emitting control stage STEG1. In this case, the first light emitting control signal may be transmitted to each of the plurality of pixels PX11, PX12, ..., PX1m arranged in the first row through the first light emitting control line E1. In addition, the second light emitting control signal may be transmitted to each of the plurality of pixels PX21, PX22, ..., PX2m arranged in the second row through the second light emitting control line E2.

[0115] However, the first light emitting control stage STEG1 may be driven by receiving the light emitting control start signal FLM.

[0116] In addition, the first light control clock line CLK1 and the second light control clock line CLK2 can be sequentially and alternately connected to the plurality of light control stages. For example, the first light control stage STEG1 can be connected to the first light control clock line CLK1, and the second light control stage STEG2 can be connected to the second light control clock line CLK2.

[0117] Since the structures of the plurality of light emission control stages are substantially the same as each other, reference will be made to Figure 4 The first light emission control stage STEG1 is described.

[0118] The first light emitting control stage STEG1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0119] The first transistor T1 may include a first electrode to which the light emission control start signal FLM is applied, a gate electrode connected to the first light emission control clock line CLK1, and a second electrode connected to the first node N1. The first transistor T1 may be referred to herein as a "first light emission control transistor."

[0120] A first electrode of the first transistor T1 included in each of the plurality of light emitting control stages except the first light emitting control stage STEG1 may be connected to a corresponding light emitting control line among the plurality of light emitting control lines E1 , E2 , . . . , En.

[0121] The second transistor T2 may include a first electrode connected to the second power voltage line VGH, a gate electrode connected to the seventh node N7, and a second electrode connected to the eighth node N8.

[0122] The third transistor T3 may include a first electrode connected to the eighth node N8, a gate electrode connected to the ninth node N9, and a second electrode connected to the second light emitting control clock line CLK2.

[0123] The fourth transistor T4 may include a first electrode connected to the seventh node N7 , a gate electrode connected to the first node N1 , and a second electrode connected to the third node N3 .

[0124] The fifth transistor T5 may include a first electrode connected to the fourth node N4, a gate electrode connected to the third node N3, and a second electrode connected to the first power supply voltage line VGL. The fifth transistor T5 may be referred to herein as a "second light emission control transistor."

[0125] The sixth transistor T6 may include a first electrode connected to the second node N2 , a gate electrode connected to the second light emitting control clock line CLK2 , and a second electrode connected to the tenth node N10 .

[0126] The seventh transistor T7 may include a first electrode connected to the tenth node N10 , a gate electrode connected to the eleventh node N11 , and a second electrode connected to the second light emitting control clock line CLK2 .

[0127] The eighth transistor T8 may include a first electrode connected to the second power voltage line VGH, a gate electrode connected to the fifth node N5, and a second electrode connected to the twelfth node N12.

[0128] The ninth transistor T9 may include a first electrode connected to the second power voltage line VGH, a gate electrode connected to the twelfth node N12, and a second electrode connected to the thirteenth node N13.

[0129] The tenth transistor T10 may include a first electrode connected to the thirteenth node N13 , a gate electrode connected to the sixth node N6 , and a second electrode connected to the first power voltage line VGL.

[0130] The eleventh transistor T11 may include a first electrode connected to the eleventh node N11 , a gate electrode connected to the first power voltage line VGL, and a second electrode connected to the fourth node N4 .

[0131] The twelfth transistor T12 may include a first electrode connected to the sixth node N6, a gate electrode connected to the first power voltage line VGL, and a second electrode connected to the fifth node N5. The twelfth transistor T12 may be referred to herein as a "third light emission control transistor."

[0132] The thirteenth transistor T13 may include a first electrode connected to the second power voltage line VGH, a gate electrode connected to the light emission preventing signal line ESR, and a second electrode connected to the fourteenth node N14.

[0133] The first capacitor C1 may include a first electrode connected to the second power voltage line VGH and a second electrode connected to the second node N2 .

[0134] The second capacitor C2 may include a first electrode connected to the tenth node N10 and a second electrode connected to the eleventh node N11.

[0135] The third capacitor C3 may include a first electrode connected to the eighth node N8 and a second electrode connected to the ninth node N9.

[0136] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 It is shown Figure 1 Specifically, Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 It is shown Figure 4 Layout diagram of the second light emitting control stage STEG2.

[0137] refer to Figure 5 , display device (e.g., Figure 1The display device DD) in the embodiment may include an active pattern ACT. The active pattern ACT may include a first channel region CH1, a second channel region CH2, a third channel region CH3, a fourth channel region CH4, a fifth channel region CH5, a sixth channel region CH6, a seventh channel region CH7, an eighth channel region CH8, a ninth channel region CH9, a tenth channel region CH10, an eleventh channel region CH11, a twelfth channel region CH12, a thirteenth channel region CH13, a first region A1, a second region A2, a third region A3, a fourth region A ... District A4, District A5, District A6, District A7, District A8, District A9, District A10, District A11, District A12, District A13, District A14, District A15, District A16, District A17, District A18, District A19, District A20, District A21, District A22, District A23, District A24, District A25, District A26, District A27, District A28, District A29, District A30, District A31, District A32, District A33, District A34, District A35, District A36, District A37, District A38, District A39, District A40, District A41

[0138] The first channel region CH1 may be disposed between the first region A1 and the second region A2. That is, the first region A1 and the second region A2 may be spaced apart from each other. The second channel region CH2 may be disposed between the third region A3 and the fourth region A4. That is, the third region A3 and the fourth region A4 may be spaced apart from each other. The third channel region CH3 may be disposed between the fifth region A5 and the sixth region A6. That is, the fifth region A5 and the sixth region A6 may be spaced apart from each other.

[0139] The fourth channel region CH4 may be disposed between the seventh region A7 and the eighth region A8. That is, the seventh region A7 and the eighth region A8 may be spaced apart from each other.

[0140] The fifth channel region CH5 may be disposed between the ninth region A9 and the tenth region A10. That is, the ninth region A9 and the tenth region A10 may be spaced apart from each other. The sixth channel region CH6 may be disposed between the eleventh region A11 and the twelfth region A12. That is, the eleventh region A11 and the twelfth region A12 may be spaced apart from each other.

[0141] The seventh channel region CH7 may be disposed between the thirteenth region A13 and the fourteenth region A14. That is, the thirteenth region A13 and the fourteenth region A14 may be spaced apart from each other. The eighth channel region CH8 may be disposed between the fifteenth region A15 and the sixteenth region A16. That is, the fifteenth region A15 and the sixteenth region A16 may be spaced apart from each other. The ninth channel region CH9 may be disposed between the sixteenth region A16 and the seventeenth region A17. That is, the sixteenth region A16 and the seventeenth region A17 may be spaced apart from each other.

[0142] The tenth channel region CH10 may be disposed between the seventeenth region A17 and the eighteenth region A18. That is, the seventeenth region A17 and the eighteenth region A18 may be spaced apart from each other. The eleventh channel region CH11 may be disposed between the nineteenth region A19 and the twentieth region A20. That is, the nineteenth region A19 and the twentieth region A20 may be spaced apart from each other. The twelfth channel region CH12 may be disposed between the twenty-first region A21 and the twenty-second region A22. That is, the twenty-first region A21 and the twenty-second region A22 may be spaced apart from each other.

[0143] The thirteenth channel region CH13 may be disposed between the twenty-third region A23 and the twenty-fourth region A24. That is, the twenty-third region A23 and the twenty-fourth region A24 may be spaced apart from each other.

[0144] Active pattern ACT and Figure 3 The active patterns PACT may include substantially the same material and may be formed by the same process.

[0145] refer to Figure 6 and Figure 7 , the first gate electrode GE1 may be disposed on the active pattern ACT. The first gate electrode GE1 and Figure 3 The first gate electrode PGE1 may include the same material and may be formed through the same process.

[0146] The first gate electrode GE1 may include first, second, third, 1003, fourth, fifth, 1005, sixth, seventh, 1006, eighth, ninth, 1009, tenth, 1010, eleventh, and twelfth gate patterns 1011 and 1012 spaced apart from each other.

[0147] refer to Figure 8 and Fig. 9 , the second gate electrode GE2 may be disposed on the first gate electrode GE1. The second gate electrode GE2 may include a 2-1 sub-gate electrode SGE1, a 2-2 sub-gate electrode SGE2, a 2-3 sub-gate electrode SGE3, and a 2-4 sub-gate electrode SGE4.

[0148] The second gate electrode GE2 and Figure 3 The second gate electrode PGE2 may include substantially the same material and may be formed by the same process.

[0149] The 2-1 sub-gate electrode SGE1 , the 2-2 sub-gate electrode SGE2 , the 2-3 sub-gate electrode SGE3 , and the 2-4 sub-gate electrode SGE4 may be spaced apart from each other.

[0150] The 2-1 sub-gate electrode SGE1 may include a first portion SGA and a second portion SGB. The first portion SGA may extend in the first direction DR1. Also, the second portion SGB may extend in the second direction DR2.

[0151] The first transistor T1 may include at least a portion of the active pattern ACT, ie, the first channel region CH1 , the first area A1 , and the second area A2 , and a portion of the third gate pattern 1003 overlapping the first channel region CH1 of the active pattern ACT.

[0152] The second transistor T2 may include at least a portion of the active pattern ACT (ie, a ninth channel region CH9 , a portion of the sixteenth region A16 , and a portion of the seventeenth region A17 ) and a portion of the eighth gate pattern 1008 overlapping the ninth channel region CH9 of the active pattern ACT.

[0153] The third transistor T3 may include at least a portion of the active pattern ACT, ie, the tenth channel region CH10 , a portion of the seventeenth region A17 , and the eighteenth region A18 , and a portion of the seventh gate pattern 1007 overlapping the tenth channel region CH10 of the active pattern ACT.

[0154] The fourth transistor T4 may include at least a portion of the active pattern ACT, ie, the fourth channel region CH4 , the seventh region A7 , and the eighth region A8 , and a portion of the twelfth gate pattern 1012 overlapping the fourth channel region CH4 of the active pattern ACT.

[0155] The fifth transistor T5 may include at least a portion of the active pattern ACT, ie, the second channel region CH2 , the third region A3 , and the fourth region A4 , and a portion of the fourth gate pattern 1004 overlapping the second channel region CH2 of the active pattern ACT.

[0156] The sixth transistor T6 may include at least a portion of the active pattern ACT, ie, the seventh channel region CH7 , the thirteenth region A13 , and the fourteenth region A14 , and a portion of the first gate pattern 1001 overlapping the seventh channel region CH7 of the active pattern ACT.

[0157] The seventh transistor T7 may include at least a portion of the active pattern ACT, ie, the sixth channel region CH6 , the eleventh region A11 , and the twelfth region A12 , and a portion of the second gate pattern 1002 overlapping the sixth channel region CH6 of the active pattern ACT.

[0158] The eighth transistor T8 may include at least a portion of the active pattern ACT (ie, a portion of the eighth channel region CH8 , the fifteenth region A15 , and the sixteenth region A16 ) and a portion of the tenth gate pattern 1010 overlapping the eighth channel region CH8 of the active pattern ACT.

[0159] The ninth transistor T9 may include at least a portion of the active pattern ACT, ie, the twelfth channel region CH12 , the twenty-first region A21 , and the twenty-second region A22 , and a portion of the eleventh gate pattern 1011 overlapping the twelfth channel region CH12 of the active pattern ACT.

[0160] The tenth transistor T10 may include at least a portion of the active pattern ACT, ie, the thirteenth channel region CH13 , the twenty-third region A23 , and the twenty-fourth region A24 , and a portion of the seventh gate pattern 1007 overlapping the thirteenth channel region CH13 of the active pattern ACT.

[0161] The eleventh transistor T11 may include at least a portion of the active pattern ACT, ie, the fifth channel region CH5 , the ninth region A9 , and the tenth region A10 , and a portion of the fifth gate pattern 1005 overlapping the fifth channel region CH5 of the active pattern ACT.

[0162] The twelfth transistor T12 may include at least a portion of the active pattern ACT, ie, the third channel region CH3 , the fifth region A5 , and the sixth region A6 , and a portion of the fifth gate pattern 1005 overlapping the third channel region CH3 of the active pattern ACT.

[0163] The thirteenth transistor T13 may include at least a portion of the active pattern ACT, ie, the eleventh channel region CH11 , the nineteenth region A19 , and the twentieth region A20 , and a portion of the ninth gate pattern 1009 overlapping the eleventh channel region CH11 of the active pattern ACT.

[0164] The first capacitor C1 may include the 2-3 sub-gate electrode SGE3 and a portion of the eleventh gate pattern 1011 overlapping the 2-3 sub-gate electrode SGE3. The 2-3 sub-gate electrode SGE3 may be Figure 4 A first electrode of the first capacitor C1.

[0165] The second capacitor C2 may include the 2-2 sub-gate electrode SGE2 and a portion of the second gate pattern 1002 overlapping the 2-2 sub-gate electrode SGE2 .

[0166] The third capacitor C3 may include the 2-4 sub-gate electrode SGE4 and a portion of the seventh gate pattern 1007 overlapping the 2-4 sub-gate electrode SGE4 .

[0167] refer to Fig. 9 and Fig.10 , the source electrode SD may be disposed on the second gate electrode GE2.

[0168] The source electrode SD may include a first light emitting control clock line CLK1, a second light emitting control clock line CLK2, a first power supply voltage line VGL, a connecting line VGLC, a light emitting blocking signal line ESR, a second power supply voltage line VGH, a first source pattern 2001, a second source pattern 2002, a third source pattern 2003, a fourth source pattern 2004, a fifth source pattern 2005, a sixth source pattern 2006, a seventh source pattern 2007, an eighth source pattern 2008, a ninth source pattern 2009, a tenth source pattern 2010, an eleventh source pattern 2011, a twelfth source pattern 2012, a thirteenth source pattern 2013 and a fourteenth source pattern 2014.

[0169] The source electrode SD and Figure 3 The source electrode PSE and the drain electrode PDE may include substantially the same material and may be formed through the same process.

[0170] The first light emitting control clock signal may be applied to the first light emitting control clock line CLK1. The first light emitting control clock line CLK1 may extend in the first direction DR1. The second light emitting control clock signal may be applied to the second light emitting control clock line CLK2. The second light emitting control clock line CLK2 may extend in the first direction DR1.

[0171] The first power voltage may be applied to the first power voltage line VGL. The first power voltage line VGL may extend in the first direction DR1.

[0172] The connection line VGLC may be connected to the first power voltage line VGL. In addition, the connection line VGLC may extend in the second direction DR2.

[0173] The second power voltage may be applied to the second power voltage line VGH. The second power voltage line VGH may extend in the first direction DR1.

[0174] The second power supply voltage may be a voltage higher than the first power supply voltage. For example, the first power supply voltage may be a negative voltage, and the second power supply voltage may be a positive voltage.

[0175] The light emission preventing signal may be applied to the light emission preventing signal line ESR. The light emission preventing signal line ESR may extend in the first direction DR1.

[0176] refer to Figure 5 , Figure 6 , Figure 8 and Fig.11 , the second light emitting control clock signal applied through the second light emitting control clock line CLK2 may be applied to the gate electrode of the first transistor T1. In addition, the second light emitting control clock signal may be applied to the gate electrode of the fifth transistor T5.

[0177] The first power voltage applied through the first power voltage line VGL may be applied to the third area A3 of the fifth transistor T5 through the connection line VGLC. In addition, the first power voltage may be applied to the gate electrode of the twelfth transistor T12.

[0178] The first source pattern 2001 may be connected to the first region A1 of the active pattern ACT. The second source pattern 2002 may be connected to the third gate pattern 1003 and the seventh region A7. The third source pattern 2003 may be connected to the thirteenth region A13, the second gate pattern 1002, and the eleventh region A11.

[0179] The fourth source pattern 2004 may be connected to the second region A2 and the twelfth gate pattern 1012. The fifth source pattern 2005 may be connected to the fourth region A4, the eighth region A8, the ninth region A9, and the eighth gate pattern 1008. The sixth source pattern 2006 may be connected to the twelfth gate pattern 1012 and the fifth region A5.

[0180] The seventh source pattern 2007 may be connected to the sixth region A6 and the seventh gate pattern 1007. The eighth source pattern 2008 may be connected to the tenth region A10 and the second gate pattern 1002. The ninth source pattern 2009 may be connected to the seventh gate pattern 1007 and the seventeenth region A17.

[0181] The tenth source pattern 2010 may be connected to the eighteenth region A18 and the sixth gate pattern 1006. The eleventh source pattern 2011 may be connected to the twelfth gate pattern 1012, the tenth gate pattern 1010, and the nineteenth region A19. The twelfth source pattern 2012 may be connected to the fifteenth region A15 and the eleventh gate pattern 1011.

[0182] The thirteenth source pattern 2013 may be connected to the twelfth region A12 and the first gate pattern 1001. The fourteenth source pattern 2014 may be connected to the fourteenth region A14 and the eleventh gate pattern 1011.

[0183] Contact holes for connecting patterns provided at different electrode layers may be formed. For example, the first contact hole CNT1 may connect the 2-1 sub-gate electrode SGE1 to the second power supply voltage line VGH. Specifically, the second portion SGB of the 2-1 sub-gate electrode SGE1 may be connected to the second power supply voltage line VGH through the first contact hole CNT1.

[0184] In an embodiment, the first portion SGA of the 2-1 sub-gate electrode SGE1 may extend to be disposed between the first transistor T1 and the first power supply voltage line VGL. In addition, the first portion SGA may further extend to be disposed between the fifth transistor T5 and the first power supply voltage line VGL. In addition, the first portion SGA may further extend to be disposed between the twelfth transistor T12 and the first power supply voltage line VGL. The 2-1 sub-gate electrode SGE1 may be referred to herein as a “shielding pattern”.

[0185] In an embodiment, the second portion SGB of the 2-1 sub-gate electrode SGE1 may partially overlap the first source pattern 2001. In addition, the second portion SGB may partially overlap the light emission preventing signal line ESR.

[0186] refer to Fig.12 and Fig.13 In an embodiment, the third gate electrode GE3 may be disposed on the source electrode SD. The third gate electrode GE3 may include a first light emission control line E1 and a second light emission control line E2.

[0187] The first light emission control line E1 may be connected to the first electrode of the first transistor T1 in the second light emission control stage STEG2. The first light emission control line E1 may transmit a first light emission control signal to the first electrode of the first transistor T1.

[0188] In the second light emitting control stage STEG2, the second light emitting control line E2 may be connected via a thirteenth node (eg, Figure 4 The thirteenth node N13 of the second transistor T10 is connected to the second electrode of the ninth transistor T9. In addition, the second light emitting control line E2 can be connected to the first electrode of the tenth transistor T10 through the thirteenth node.

[0189] The second light emitting control line E2 may transmit a second light emitting control signal to a plurality of pixels disposed in a second row (eg, Figure 2 In addition, the second light emitting control line E2 can transmit the second light emitting control signal to the second light emitting control stage (eg, Figure 4 A third light emitting control stage adjacent to the second light emitting control stage STEG2).

[0190] Fig.14 It is shown Figure 4 Layout diagram of the first light emission control stage and the second light emission control stage.

[0191] refer to Fig.14, the 2-1 sub-gate electrode SGE1' included in the first light emission control stage STEG1 may include a first portion SGA' and a second portion SGB'. In an embodiment, the 2-1 sub-gate electrodes included in each of the plurality of light emission control stages may not be connected to each other. For example, the 2-1 sub-gate electrode SGE1' included in the first light emission control stage STEG1 may not be connected to the 2-1 sub-gate electrode SGE1 included in the second light emission control stage STEG2. For example, the first portion SGA' of the 2-1 sub-gate electrode SGE1' included in the first light emission control stage STEG1 may not be connected to the first portion SGA of the 2-1 sub-gate electrode SGE1 included in the second light emission control stage STEG2.

[0192] That is, the 2-1 sub-gate electrode included in each of the plurality of light emission control stages may include a first portion extending in the first direction DR1 and a second portion extending in the second direction DR2.

[0193] Fig.15 It is along Fig.13 A cross-sectional view taken along line II'.

[0194] exist Fig.15 In the description of Figure 3 The components are the same as the components, and the detailed description of the same components may be omitted.

[0195] refer to Fig.13 and Fig.15 , light emitting control driver (e.g., Figure 2 The light emission control driver 600 may include a substrate SUB, a barrier layer BAR, a buffer layer BUF, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, a via insulating layer VIA, an active pattern ACT, a first gate electrode GE1, a first power supply voltage line VGL, a fourth node N4, a connection line VGLC, and a 2-1 sub-gate electrode (e.g., Figure 8 The first part SGA of the 2-1 sub-gate electrode SGE1).

[0196] The active pattern ACT may be disposed on the buffer layer BUF. The active pattern ACT may include a second channel region CH2, a third region A3, and a fourth region A4.

[0197] A gate insulating layer GI may be disposed on the buffer layer BUF. The gate insulating layer GI may sufficiently cover the active pattern ACT.

[0198] The first gate electrode GE1 may be disposed on the gate insulating layer GI. The first gate electrode GE1 may overlap the second channel region CH2. In this case, the fifth transistor T5 may include an active pattern ACT and the first gate electrode GE1 overlapping the second channel region CH2 of the active pattern ACT.

[0199] The first interlayer insulating layer ILD1 may be disposed on the gate insulating layer GI. The first interlayer insulating layer ILD1 may sufficiently cover the first gate electrode GE1.

[0200] The first portion SGA of the 2-1 sub-gate electrode may be disposed on the first interlayer insulating layer ILD1. The first portion SGA may be disposed between the fifth transistor T5 and the first power supply voltage line VGL.

[0201] The second interlayer insulating layer ILD2 may be disposed on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may sufficiently cover the first portion SGA.

[0202] The connection line VGLC, the fourth node N4, and the first power supply voltage line VGL may be disposed on the second interlayer insulating layer ILD2. The connection line VGLC may be connected to the third area A3 of the active pattern ACT through a contact hole. In addition, the fourth node N4 may be connected to the fourth area A4 of the active pattern ACT through a contact hole. The fourth node N4 may have a Figure 4 The configuration of the fourth node N4 is substantially the same as the configuration.

[0203] The via insulating layer VIA may be disposed on the second interlayer insulating layer ILD2. The via insulating layer VIA may sufficiently cover the connection line VGLC, the fourth node N4, and the first power supply voltage line VGL. In addition, the via insulating layer VIA may have a substantially flat top surface without generating steps around the connection line VGLC, the fourth node N4, and the first power supply voltage line VGL.

[0204] Fig.16 It is along Fig.13 A cross-sectional view taken along line II-II'.

[0205] refer to Fig.13 and Fig.16 , 2-1 sub-gate electrode (for example, Figure 8 The second portion SGB of the 2-1 sub-gate electrode SGE1 may be disposed on the first interlayer insulating layer ILD1. In addition, the second power supply voltage line VGH may be disposed on the second interlayer insulating layer ILD2.

[0206] The second power voltage line VGH and the second portion SGB may be connected to each other through the first contact hole CNT1. Accordingly, the second power voltage applied through the second power voltage line VGH may be applied to the second portion SGB.

[0207] refer to Fig.13 , Fig.15 and Fig.16 As mentioned above, the first power supply voltage may be applied to the first power supply voltage line VGL. The first power supply voltage may be a negative voltage. Accordingly, positive charges may accumulate on the upper portion of the substrate SUB. That is, when a negative voltage is applied to the first power supply voltage line VGL, positive charges may accumulate on the upper portion of the substrate SUB.

[0208] In this case, positive charges may be accumulated not only on the upper portion of the substrate SUB overlapping the first power voltage line VGL but also on the upper portion of the substrate SUB overlapping the active pattern ACT. Thus, an electric field may be generated under the active pattern ACT.

[0209] Accordingly, the threshold voltage of each of the first transistor T1, the fifth transistor T5, and the twelfth transistor T12 adjacent to the first power voltage line VGL may drift. Specifically, the threshold voltage of each of the first transistor T1, the fifth transistor T5, and the twelfth transistor T12 may drift negatively. Accordingly, the output of the light emitting control signal such as the second light emitting control signal may decrease.

[0210] Each of the light emission control stages according to the embodiment may include a 2-1 sub-gate electrode SGE1. The 2-1 sub-gate electrode SGE1 may include a first portion SGA and a second portion SGB.

[0211] The first portion SGA may extend to be disposed between the first transistor T1 and the first power supply voltage line VGL. In addition, the first portion SGA may further extend to be disposed between the fifth transistor T5 and the first power supply voltage line VGL. In addition, the first portion SGA may further extend to be disposed between the twelfth transistor T12 and the first power supply voltage line VGL.

[0212] The second portion SGB may be connected to the second power voltage line VGH through the first contact hole CNT1. Accordingly, the second power voltage may be applied to the first portion SGA through the second portion SGB. As mentioned above, the second power voltage may be a positive voltage, and accordingly, a positive voltage may be applied to the first portion SGA.

[0213] Therefore, negative charges may be accumulated on the upper portion of the substrate SUB overlapping the first portion SGA. Positive charges may be prevented from being accumulated on the upper portion of the substrate SUB overlapping the active pattern ACT.

[0214] Accordingly, the threshold voltage of each of the first transistor T1, the fifth transistor T5, and the twelfth transistor T12 may be prevented from negatively drifting. Accordingly, the output of the light emitting control signal such as the second light emitting control signal may not be reduced.

[0215] In addition, by placing the lower metal under the active pattern ACT, positive charges may be prevented from being accumulated on the upper portion of the substrate SUB due to the first power voltage line VGL. In this case, an additional process and mask may be required to arrange the lower metal.

[0216] According to the embodiment, since the 2-1 sub-gate electrode SGE1 is provided, the threshold voltage of each of the first transistor T1, the fifth transistor T5, and the twelfth transistor T12 can be prevented from negatively drifting without the need for a lower metal. That is, the threshold voltage of each of the first transistor T1, the fifth transistor T5, and the twelfth transistor T12 can be prevented from negatively drifting without the need for an additional process and a mask.

[0217] Figure 8 , Fig.11 , Fig.13 , Fig.14 , Fig.15 and Fig.16 An example in which the shielding pattern is a portion of the second gate electrode GE2 is shown. However, the present disclosure is not limited thereto.

[0218] For example, the shielding pattern may be a part of the source electrode SD. In this case, the shielding pattern may be a part of the second power supply voltage line VGH. That is, the second power supply voltage line VGH may extend to be disposed between the first transistor T1 and the first power supply voltage line VGL. In addition, the second power supply voltage line VGH may further extend to be disposed between the fifth transistor T5 and the first power supply voltage line VGL. In addition, the second power supply voltage line VGH may further extend to be disposed between the twelfth transistor T12 and the first power supply voltage line VGL. Accordingly, the threshold voltage of each of the first transistor T1, the fifth transistor T5 and the twelfth transistor T12 may be prevented from negatively drifting.

[0219] For example, the shielding pattern may be a part of the first gate electrode GE1. In this case, the first gate electrode GE1 may be disposed between the first transistor T1 and the first power supply voltage line VGL. In addition, the first gate electrode GE1 may be disposed between the fifth transistor T5 and the first power supply voltage line VGL. In addition, the first gate electrode GE1 may be disposed between the twelfth transistor T12 and the first power supply voltage line VGL. In addition, the first gate electrode GE1 may be connected to the second power supply voltage line VGH through a contact hole. Accordingly, the threshold voltage of each of the first transistor T1, the fifth transistor T5, and the twelfth transistor T12 may be prevented from negatively drifting.

[0220] That is, according to the present disclosure, the position of the shielding pattern may be changed.

[0221] Fig.17 is a layout diagram showing a first light emission control stage and a second light emission control stage according to another embodiment.

[0222] In addition to the configuration of the 2-1 sub-gate electrode DSGE1', Fig.17 The first light emitting control stage DSTEG1 can be connected with Fig.14 The first light emission control stage STEG1 is substantially the same as the first light emission control stage STEG1. In addition, in addition to the configuration of the 2-1 sub-gate electrode DSGE1, Fig.17 The second light emitting control stage DSTEG2 can be connected with Fig.14 The second light emitting control stage STEG2 is basically the same.

[0223] refer to Fig.17 , the 2-1 sub-gate electrodes included in each of the plurality of light emission control stages may be connected to each other. That is, the 2-1 sub-gate electrodes included in each of the plurality of light emission control stages may be integrally formed.

[0224] For example, the 2-1 sub-gate electrode DSGE1' included in the first light emission control stage DSTEG1 may include a first portion DSGA' extending in the first direction DR1 and a second portion DSGB' extending in the second direction DR2. In addition, the 2-1 sub-gate electrode DSGE1 included in the second light emission control stage DSTGE2 may include only a portion extending in the first direction DR1.

[0225] The 2-1 sub-gate electrode DSGE1 of the second light emission control stage DSTEG2 may be a portion extending from the first portion DSGA′ of the first light emission control stage DSTEG1 .

[0226] That is, the 2-1 sub-gate electrode included in each of the plurality of light emission control stages except the first light emission control stage DSTEG1 may include only a portion extending in the first direction DR1 and not a portion extending in the second direction DR2.

[0227] The present disclosure can be applied to various display devices. For example, the present disclosure can be applied to various display devices such as display devices for vehicles, ships and aircraft, portable communication devices, display devices for exhibitions or information transmission, and medical display devices.

[0228] The foregoing is an illustration of the embodiments of the present disclosure and should not be construed as limiting the present disclosure. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope defined in the claims.

Claims

1. A display device, comprising: A display panel including pixels connected to light emitting control lines; as well as a light emission control driver, comprising a light emission control stage for providing a light emission control signal to the pixel through the light emission control line, Wherein, the light emitting control stage comprises: a first light emission control transistor including a first electrode connected to the light emission control line, a gate electrode connected to a first light emission control clock line, and a second electrode connected to a first node; a first power supply voltage line to which a first power supply voltage is applied; and A shield pattern extends between the first light emission control transistor and the first power supply voltage line and receives a power supply voltage higher than the first power supply voltage.

2. The display device according to claim 1, wherein: The light emission control stage further includes a second power supply voltage line to which a second power supply voltage higher than the first power supply voltage is applied, and The shielding pattern is connected to the second power voltage line through a contact hole.

3. The display device according to claim 2, wherein: The light emission control stage further includes a first capacitor including a first electrode connected to the second power supply voltage line and a second electrode connected to a second node.

4. The display device according to claim 3, wherein: The shielding pattern is disposed on the same layer as the second electrode of the first capacitor.

5. The display device according to any one of claims 1 to 4, wherein: The light emission control stage further includes a second light emission control transistor including a first electrode connected to the first power supply voltage line, a gate electrode connected to a third node, and a second electrode connected to a fourth node.

6. The display device according to claim 5, wherein: The shield pattern further extends between the second light emission control transistor and the first power supply voltage line.

7. The display device according to claim 6, wherein: The light emission control stage further includes a third light emission control transistor including a first electrode connected to a fifth node, a gate electrode connected to the first power supply voltage line, and a second electrode connected to a sixth node.

8. The display device according to claim 7, wherein: The shield pattern further extends between the third light emission control transistor and the first power supply voltage line.

9. A display device, comprising: an active pattern including a first region, a second region spaced apart from the first region, and a first channel region disposed between the first region and the second region; a first gate electrode, disposed on the active pattern; A second gate electrode, disposed on the first gate electrode and comprising a 2-1 sub-gate electrode and a 2-2 sub-gate electrode; A first light emitting control clock line, disposed on the second gate electrode and extending in a first direction; a first power supply voltage line, disposed on the second gate electrode, extending in the first direction and receiving a first power supply voltage; a second power supply voltage line disposed on the second gate electrode, extending in the first direction and receiving a second power supply voltage higher than the first power supply voltage; a light emitting control line, disposed on the first power supply voltage line, connected to the first area of ​​the active pattern and receiving a light emitting control signal; as well as a first light emission control transistor including the first channel region of the active pattern, the first area of ​​the active pattern, the second area of ​​the active pattern, and a portion of the first gate electrode overlapping the first channel region of the active pattern, The 2-1 sub-gate electrode extends between the first channel region of the active pattern and the first power supply voltage line.

10. The display device according to claim 9, wherein: The 2-1 sub-gate electrode includes a first portion extending in the first direction and a second portion extending in a second direction crossing the first direction.

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