Pixel driving circuit for field sequential display

Abstract

The invention discloses a pixel driving circuit for field sequential display. The pixel driving circuit comprises a reset pre-storage unit and a driving unit, the reset pre-storage unit comprises a first transistor, a third transistor and a pre-storage capacitor; the grid electrode of the first transistor is coupled to a row grid signal line, the first source and drain electrode of the first transistor is coupled to a data signal line, and the second source and drain electrode of the first transistor is coupled to the driving unit and the first source and drain electrode of the third transistor; a second source drain electrode of the third transistor is coupled to one end of a pre-storage capacitor, and the other end of the pre-storage capacitor is coupled to a common signal line; a gate of the third transistor is coupled to a reset signal line. The driving circuit has the advantages that the requirement for the voltage range of data signal line changes is greatly lowered, and therefore the power consumption of a driving chip and a control row gate signal line output unit is lowered.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel driving circuit for field sequential display. Background Art

[0002] In traditional field sequential or color sequential display driving technology, the backlight can only be turned on after the data signal voltage of all screens is written and the liquid crystal is deflected to a stable state, otherwise the screen will be chaotic. Therefore, the data signal voltage writing and liquid crystal deflection time will greatly compress the backlight turn-on time, resulting in difficulties in improving the brightness of the display, as well as difficulties in improving the refresh rate and resolution, increased power consumption and increased backlight material costs. Therefore, how to speed up the liquid crystal driving time and increase the backlight turn-on time is a very important issue.

[0003] A pre-storage capacitor is now set up so that the data signal voltage can be pre-stored in the pre-storage capacitor during the backlight emission time to store the data signal voltage required for the next picture; when switching pictures, the pixel electrode can read the corresponding data signal voltage in the pre-storage capacitor, thereby saving the time for writing the pixel data signal voltage and correspondingly increasing the backlight emission time.

[0004] However, this pixel circuit design faces the problem of voltage reduction associated with charge sharing. Assuming that the capacitance value of the pre-storage capacitor is the sum of the capacitance of the holding capacitor and the pixel electrode, the pixel electrode is at a common signal voltage of 0V before being reset. If the pixel electrode is to be charged to 5V, according to the principle of charge conservation, the pre-storage capacitor needs to be pre-charged to 10V to achieve this. Therefore, the pixel circuit design needs to increase the voltage supply range given by the data signal line to meet the liquid crystal operating voltage range, put forward higher requirements on the output voltage range of the driver chip, and greatly increase power consumption. When the driver chip does not meet the requirements, a larger pre-storage capacitor is required. When the pre-storage capacitor is much larger than the holding capacitor and the pixel electrode, the voltage drop will be smaller during charge sharing, but this will reduce the aperture ratio and increase the difficulty of pre-charging the pre-storage capacitor, which is not conducive to the realization of high refresh rate and high resolution.

[0005] Therefore, the present invention proposes a pixel driving circuit for field sequential display. Summary of the invention

[0006] The object of the present invention is to provide a pixel driving circuit for field sequential display, which realizes a circuit with a simple circuit structure and can reduce the required data signal voltage range.

[0007] The object of the present invention is to realize a pixel driving circuit for field sequential display through the following technical scheme, including a reset pre-storage unit and a driving unit; The reset pre-storage unit includes a first transistor, a third transistor and a pre-storage capacitor; the gate of the first transistor is coupled to a row gate signal line, the first source and drain of the first transistor are coupled to a data signal line, the second source and drain of the first transistor are coupled to a driving unit and a first source and drain of a third transistor; the second source and drain of the third transistor is coupled to one end of the pre-storage capacitor, and the other end of the pre-storage capacitor is coupled to a common signal line; the gate of the third transistor is coupled to the reset signal line.

[0008] Further, the driving unit includes a second transistor and a pixel electrode; The gate of the second transistor is coupled to the transfer signal line, the first source and drain of the second transistor are coupled to the second source and drain of the first transistor, the second source and drain of the second transistor are coupled to one end of the pixel electrode; the other end of the pixel electrode is coupled to the common signal line.

[0009] Furthermore, the driving unit further includes a holding capacitor; one end of the holding capacitor is coupled to the second source and drain of the second transistor, and the other end of the holding capacitor is coupled to the common signal line.

[0010] Furthermore, the driving timing of the pixel driving circuit is configured as follows: In the backlight-on stage of the Nth frame, the levels of the row gate signal line and the reset signal line are both changed to high levels, the first transistor and the third transistor are turned on, so that the data signal line writes the data signal voltage into the pre-storage capacitor through the first transistor and the third transistor, and after the writing is completed, the row gate signal, the reset signal line and the data signal line are all changed to low levels, and the first transistor and the third transistor are turned off; In the backlight off stage of the Nth frame, the levels of the row gate signal line and the transfer signal line both jump to a high level, the first transistor and the second transistor are turned on, so that the data signal line inputs a reset signal voltage through the first transistor and the second transistor to complete the reset of the pixel electrode. After the reset is completed, the row gate signal and the transfer signal line both jump to a low level, and the first transistor and the second transistor are turned off; After the reset is completed, the levels of the reset signal line and the transfer signal line both jump to a high level, the second transistor and the third transistor are turned on, and the data signal voltage of the pre-storage capacitor is transferred to the pixel capacitor through the second transistor and the third transistor. After the transfer is completed, the levels of the reset signal line and the transfer signal line both jump to a low level, and the second transistor and the third transistor are turned off.

[0011] Further, when the Nth frame is a positive polarity frame, the range of the reset signal voltage input by the data signal line to the pixel electrode is (Vcom, Vop_max+Vcom), where Vcom represents the common signal voltage and Vop_max represents the maximum grayscale corresponding voltage.

[0012] Further, when the Nth frame is a negative polarity frame, the range of the reset signal voltage input from the data signal line to the pixel electrode is (Vcom-Vop_max, Vcom).

[0013] The present invention has the following advantages: The present invention can reset the pixel electrodes in the positive polarity frame and the negative polarity frame to different potentials by multiplexing the reset function of the data signal line when resetting the pixel electrode; in the positive polarity frame, the voltage range of the reset signal input to the data signal line is (Vcom, Vop_max+Vcom), and the voltage range of the data signal that needs to be input to the pre-storage capacitor is (Vcom-Vop_max, Vcom+Vop_max); in the negative polarity frame, the voltage range of the reset signal input to the data signal line is (Vcom-Vop_max, Vcom), and the voltage range of the data signal line that needs to be output is (Vcom-Vop_max, Vcom+Vop_max), so when the present invention is adopted, the voltage variation range of the data signal line is (-Vop_max, +Vop_max), that is, 2*Vop_max, which greatly reduces the requirements on the voltage range of the data signal line, thereby reducing the power consumption of the driver chip and the control row gate signal line unit.

[0014] The present invention couples one end of the third transistor to the first transistor and the other end to the pre-storage capacitor; when the reset signal voltage is input to reset the pixel electrode, turning off the third transistor will not affect the pre-stored data signal voltage in the pre-storage capacitor, and at the same time, the potential of the pre-storage node and the potential of the pixel electrode can be changed to the corresponding reset signal voltage input by the data signal line, thereby reducing the difficulty of transfer in the transfer stage and reducing the requirements for the voltage range pre-stored in the pre-storage capacitor at the beginning.

[0015] Since the present invention reduces the requirement on the voltage range of the data signal line, the maximum value of the input data signal voltage is reduced, and a pre-storage capacitor with a large capacitance value is not needed, thereby removing the restriction on the capacitance value of the pre-storage capacitor. The capacitance of the pre-storage capacitor is positively correlated with the area of ​​the capacitor, so the area requirement for preparing the pre-storage capacitor is reduced, thereby improving the aperture ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A circuit diagram of the present invention; Figure 2 is a timing diagram of the present invention; Figure 3 This is a voltage change comparison diagram of the present invention. DETAILED DESCRIPTION

[0017] The present invention is further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0018] It should be noted that the directions or positional relationships indicated by "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use, or are the directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0019] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions in the embodiments may be combined with each other.

[0020] See also Figure 1 The present invention provides a pixel driving circuit for field sequential display, including a reset pre-storage unit and a driving unit; the reset pre-storage unit includes a first transistor T1, a third transistor T3 and a pre-storage capacitor Cs1; the gate of the first transistor T1 is coupled to the row gate signal line Scan, the first source and drain of the first transistor T1 are coupled to the data signal line Data, the second source and drain of the first transistor T1 are coupled to the first source and drain of the second transistor T2 and the first source and drain of the third transistor T3; the second source and drain of the third transistor T3 is coupled to one end of the pre-storage capacitor Cs1, and the other end of the pre-storage capacitor Cs1 is coupled to the common signal line Com; the gate of the third transistor T3 is coupled to the reset signal line Reset.

[0021] Further, the driving unit includes a second transistor T2, a pixel electrode Clc and a holding capacitor Cs2; the gate of the second transistor T2 is coupled to the transfer signal line Tran, the first source and drain of the second transistor T2 are coupled to the second source and drain of the first transistor T1, and the second source and drain of the second transistor T2 are coupled to one end of the pixel electrode Clc; the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the holding capacitor Cs2 is coupled to the second source and drain of the second transistor T2, and the other end of the holding capacitor Cs2 is coupled to the common signal line Com.

[0022] While working, refer to Figure 2 , the driving timing of the pixel driving circuit is configured: In the backlight-on stage of the Nth frame, the levels of the row gate signal line Scan and the reset signal line Reset both jump to a high level, the first transistor T1 and the third transistor T3 are turned on, so that the data signal line Data writes the data signal voltage into the pre-storage capacitor Cs1 through the first transistor T1 and the third transistor T3. After the writing is completed, the row gate signal Scan, the reset signal line Reset and the data signal line Data all jump to a low level, and the first transistor T1 and the third transistor T3 are turned off; In the backlight off stage of the Nth frame, the levels of the row gate signal line Scan and the transfer signal line Tran both jump to a high level, the first transistor T1 and the second transistor T2 are turned on, so that the data signal line Data completes the reset of the holding capacitor Cs2 and the pixel electrode Clc through the first transistor T1 and the second transistor T2. After the reset is completed, the row gate signal line Scan and the transfer signal line Tran both jump to a low level, and the first transistor T1 and the second transistor T2 are turned off; When the Nth frame is a positive polarity frame, the range of the reset signal voltage input by the data signal line Data to the pixel electrode Clc is (Vcom, Vop_max+Vcom), where Vcom represents the common signal voltage and Vop_max represents the voltage corresponding to the maximum grayscale; when the Nth frame is a negative polarity frame, the range of the reset signal voltage input by the data signal line Data to the pixel electrode Clc is (Vcom-Vop_max, Vcom); After resetting, the levels of the reset signal line Reset and the transfer signal line Tran jump to high level, the second transistor T2 and the third transistor T3 are turned on, and the data signal voltage of the pre-storage capacitor Cs1 is transferred to the pixel capacitor Clc through the second transistor T2 and the third transistor T3.

[0023] See also Figure 3, the voltage range changes of the prior art and the present invention are compared. First, in the prior art and the present invention, the capacitance value of the pre-storage capacitor Cs1 is equal to the sum of the holding capacitor Cs2 and the pixel electrode Clc (i.e., Cs1=Cs2+Clc), and the voltage difference between the working voltage of the pixel electrode Clc and the common signal voltage Vcom is in the range of (0, Vop_max ); Taking the pixel driving circuit of odd columns as an example, assuming that in the display stage of the Nth frame (N is a natural number), the pixel voltage of the odd columns is negative (Vpixel-Vcom≤0), then due to the requirement of liquid crystal polarity column inversion, the pixel voltage corresponding to the N+1th frame should be positive (Vpixel-Vcom≥0), and the working principle of the pre-storage method is now adopted. Therefore, at the display time of the Nth frame, the data signal voltage of the N+1th frame will be written to the pre-storage capacitor Cs1, so it is necessary to write a positive data signal voltage, that is, a voltage ≥Vcom. Therefore, the Nth frame corresponding to the data signal voltage that needs to be written is called a positive polarity frame, and the frame that writes a negative polarity voltage is called a negative polarity frame.

[0024] In the prior art, during the backlight off stage of the Nth frame (the Nth frame is a positive polarity frame), the reset signal line Reset is changed to a high level, the third transistor T3 is turned on, and the voltage of the pixel electrode Clc is reset to the common signal voltage Vcom; after the reset is completed, the transfer signal line Tran is changed to a low level, and the second transistor T2 transfers the data signal voltage on the pre-storage capacitor Cs1 to the pixel electrode Clc. Assuming that the working voltage Vpixel required by the pixel electrode Clc is Vop_max+Vcom (this is the maximum working voltage required by the pixel electrode Clc when the Nth frame is a positive polarity frame), the data signal voltage pre-written into the pre-storage capacitor Cs1 is Vcs1. According to the charge conservation principle: (Vcs1-(Vop_max+Vcom))*Cs1=((Vop_max+Vcom)-Vcom)*(Cs2+Clc); That is, Vcs1-Vop_max-Vcom=Vop_max, Vcs1= 2*Vop_max+Vcom.

[0025] Similarly, when the Nth frame is a negative polarity frame, when a negative polarity data signal voltage needs to be written into the pre-storage capacitor Cs1, the working voltage Vpixle required by the pixel electrode Clc is set to -Vop_max. According to the charge conservation principle, Vs1-(-Vop_max+Vcom)*Cs1=((-Vop_max+Vcom)-Vcom)*(Cs2+Clc); That is, Vs1+Vop_max-Vcom=-Vop_max, Vs1=-2*Vop_max+Vcom; therefore, the data signal voltage range required for the data signal line Data input is (-2*Vop_max+Vcom, 2*Vop_max+Vcom), that is, the data signal voltage variation range is 4*Vop_max.

[0026] Using the present invention: in the backlight off stage of the Nth frame, the levels of the row gate signal line Scan and the transfer signal line Tran jump to a high level, turn on the first transistor T1 and the second transistor T2, so that the data signal line Data completes the reset of the holding capacitor Cs2 and the pixel electrode Clc through the first transistor T1 and the second transistor T2; after the reset is completed, the levels of the reset signal line Reset and the transfer signal line Tran jump to a high level, the third transistor T3 and the second transistor T2 are turned on, and the data signal voltage on the pre-storage capacitor Cs1 is transferred to the pixel electrode Clc; Similarly, when the Nth frame is a positive polarity frame, the working voltage Vpixel required by the pixel electrode Clc is set to Vop_max+Vcom. At this time, when the pixel electrode Clc is reset, the voltage of the pixel electrode Clc is reset to the reset signal voltage Vop_max+Vcom by the data signal line Data. According to the charge conservation principle: (Vcs1-(Vop_max+Vcom))*Cs1=((Vop_max+Vcom)- (Vop_max +Vcom))*(Cs2+Clc), That is, Vcs1-Vop_max-Vcom=0, Vcs1= Vop_max+Vcom; When the Nth frame is a positive polarity frame, the minimum operating voltage Vpixel required by the pixel electrode Clc is Vcom. According to the charge conservation principle: (Vcs1-Vcom)*Cs1=(Vcom- (Vop_max +Vcom))*(Cs2+Clc), Vcs1-Vcom=Vcom-(Vop_max +Vcom), Vcs1=Vcom- Vop_max, that is, when the Nth frame is a positive polarity frame, the required data signal voltage range is (Vop_max+Vcom)- (Vcom- Vop_max)=2*Vop_max; Similarly, when a negative data signal voltage is written to the pre-storage capacitor Cs1 in the next frame, the same formula is used to calculate the working voltage required by the pixel electrode Clc in the negative polarity frame in the two cases of the minimum -Vop_max to the maximum working voltage Vcom. It can be deduced that the data signal voltage range is still (Vcom-Vop_max, Vop_max+Vcom). Therefore, for the pixel circuit adopted in the present invention, the overall range of the data signal line Data is 2*Vop_max.

[0027] The overall range of the data signal line Data in the prior art is 4*Vop_max, while the overall range of the data signal line Data in the present invention is 2*Vop_max. By resetting the pixel electrode Clc to different potentials, the data signal voltage range can be completely overlapped in the positive polarity and the negative polarity, thereby achieving a significant decrease in the data signal voltage range, which can further reduce the power consumption of the driving chip and the control row gate signal line output unit.

[0028] It can also be known from the charge sharing formula that in the existing driving circuit, when the absolute value of the difference between the capacitance of the pre-storage capacitor Cs1 and the sum of the holding capacitor Cs2 and the pixel electrode Clc is smaller, the charge sharing effect is worse, and a larger data signal voltage range is required, otherwise a larger pre-storage capacitor Cs1 and smaller holding charges Cs2 and pixel electrode Clc are required.

[0029] The size of the capacitor is positively correlated with the size of the overlapping region of the capacitor during the preparation process. When the pre-storage capacitor Cs1 increases, the corresponding required area will increase, which will affect the aperture ratio; but when the pixel electrode Clc and the holding capacitor Cs2 decrease, the pixel voltage Vpixel leaks more within a frame, and flickering problems are likely to occur. Therefore, this circuit has greater restrictions on the size of the pre-storage capacitor Cs1, the pixel electrode Clc and the holding capacitor Cs2.

[0030] When the present invention is adopted, the overall range of the data signal line Data is greatly reduced, so there is no need for such a large-capacity pre-storage capacitor Cs1, and the restriction on the capacitance value of the pre-storage capacitor is removed, so there is no need to occupy too much preparation area, which is more conducive to improving the aperture ratio and facilitating the realization of high refresh rate and high resolution.

[0031] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the invention, and these all belong to the protection scope of the invention.

Claims

1. A pixel driving circuit for field sequential display is characterized by: It includes a reset pre-storage unit and a drive unit; The reset pre-storage unit comprises a first transistor (T1), a third transistor (T3) and a pre-storage capacitor (Cs1); the gate of the first transistor (T1) is coupled to a row gate signal line (Scan), the first source and drain of the first transistor (T1) are coupled to a data signal line (Data), the second source and drain of the first transistor (T1) are coupled to a driving unit and the first source and drain of a third transistor (T3); the second source and drain of the third transistor (T3) are coupled to one end of the pre-storage capacitor (Cs1), and the other end of the pre-storage capacitor (Cs1) is coupled to a common signal line (Com); the gate of the third transistor (T3) is coupled to a reset signal line (Reset).

2. The pixel driving circuit for field sequential display according to claim 1 is characterized in that: The driving unit includes a second transistor (T2) and a pixel electrode (Clc); The gate of the second transistor (T2) is coupled to a transfer signal line (Tran), the first source and drain of the second transistor (T2) are coupled to the second source and drain of the first transistor (T1), the second source and drain of the second transistor (T2) are coupled to one end of a pixel electrode (Clc); and the other end of the pixel electrode (Clc) is coupled to a common signal line (Com).

3. The pixel driving circuit for field sequential display according to claim 2 is characterized in that: The driving timing of the pixel driving circuit is configured as follows: In the backlight-on stage of the Nth frame, the levels of the row gate signal line (Scan) and the reset signal line (Reset) both jump to a high level, the first transistor (T1) and the third transistor (T3) are turned on, so that the data signal line (Data) writes the data signal voltage into the pre-storage capacitor (Cs1) through the first transistor (T1) and the third transistor (T3), and after the writing is completed, the row gate signal (Scan), the reset signal line (Reset) and the data signal line (Data) all jump to a low level, and the first transistor (T1) and the third transistor (T3) are turned off; In the backlight off stage of the Nth frame, the levels of the row gate signal line (Scan) and the transfer signal line (Tran) both jump to a high level, the first transistor (T1) and the second transistor (T2) are turned on, so that the data signal line (Data) inputs a reset signal voltage through the first transistor (T1) and the second transistor (T2) to complete the reset of the pixel electrode (Clc), after the reset is completed, the row gate signal line (Scan) and the transfer signal line (Tran) both jump to a low level, and the first transistor (T1) and the second transistor (T2) are turned off; After the reset is completed, the levels of the reset signal line (Reset) and the transfer signal line (Tran) both jump to a high level, the third transistor (T3) and the second transistor (T2) are turned on, and the data signal voltage of the pre-storage capacitor (Cs1) is transferred to the pixel capacitor (Clc) through the second transistor (T2) and the third transistor (T3). After the transfer is completed, the levels of the reset signal line (Reset) and the transfer signal line (Tran) both jump to a low level, and the second transistor (T2) and the third transistor (T3) are turned off.

4. The pixel driving circuit for field sequential display according to claim 3 is characterized in that: When the Nth frame is a positive polarity frame, the reset signal voltage input by the data signal line (Data) to the pixel electrode (Clc) is in the range of (Vcom, Vop_max+Vcom), where Vcom represents the common signal voltage and Vop_max represents the voltage corresponding to the maximum grayscale.

5. The pixel driving circuit for field sequential display according to claim 3 is characterized in that: When the Nth frame is a negative polarity frame, the range of the reset signal voltage input by the data signal line (Data) to the pixel electrode (Clc) is (Vcom-Vop_max, Vcom).

6. The pixel driving circuit for field sequential display according to claim 2 is characterized in that: The driving unit further includes a holding capacitor (Cs2); One end of the holding capacitor (Cs2) is coupled to the second source-drain of the second transistor (T2), and the other end of the holding capacitor (Cs2) is coupled to the common signal line (Com).

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