In-memory computing circuit structure and data processing method applied to same

Abstract

The invention discloses an in-memory computing circuit structure and a data processing method applied to the in-memory computing circuit structure, and the in-memory computing circuit structure comprises a data module with multi-row and multi-column data, an operation module and a reference module with multi-row and multi-column data, wherein the data module comprises a plurality of rows of data units which can be connected in parallel, and each data unit uniquely corresponds to an address for storing data; the reference module is provided with a plurality of rows of reference units which can be connected in parallel, and the reference units and the data units are composed of the same standard units; and in response to a received predetermined logic instruction, the current source is input to the data module and the reference module, the operation module outputs a logic result according to data voltage information input by the data module and reference voltage information input by the reference module, and the predetermined logic instruction is executed according to the logic result. According to the invention, N-bit input logic can be realized without a median unit, the logic bit is linearly related to the line number of the reference unit in the reference module, and the operation is convenient and high in reliability.

Description

Technical Field

[0001] The present invention relates to the field of in-memory computing technology, and in particular to an in-memory computing circuit structure and a data processing method applied thereto. Background Art

[0002] As the size of semiconductor processes continues to shrink, Moore's Law slows down, and the increase in leakage current and interconnection delay become bottlenecks for traditional CMOS memory. Therefore, finding solutions for the next generation of storage technology has become the focus of integrated circuit research. Among them, resistive non-volatile memory is widely welcomed by the industry due to its near-zero static power consumption. Resistive non-volatile memory mainly includes resistive random access memory, phase change memory, and magnetic memory. Its main feature is to represent data through the high and low resistance states of the device. For example, high resistance represents data 1, and low resistance represents data 0, thereby obtaining negligible leakage current.

[0003] The resistance characteristics of resistive non-volatile memory also give it good in-memory computing expansion characteristics. By opening multiple word lines, the resistor devices can be connected in parallel to achieve unit coupling, and by setting multi-level reference resistors, Boolean logic operations can be realized by relying on the original read circuit. The combination of non-volatile memory and in-memory computing is expected to break through the bottleneck of traditional CMOS memory and von Neumann architecture and achieve more excellent computing performance. However, many in-memory computing designs are currently in a relatively theoretical state, and multi-level reference resistors greatly reduce the reliability of operations. At the same time, in the existing resistor device parallel-configured reference resistor type in-memory computing schemes, the design of reference resistors is relatively cumbersome, requiring more devices to be connected in series and parallel, or adjusting the resistance through transistors. These schemes make the reference module occupy a larger area, and the resistance margin is small, and the reliability is poor. Summary of the invention

[0004] In view of this, the present invention provides an in-memory computing circuit structure and a data processing method applied thereto to solve at least one of the above-mentioned problems.

[0005] According to a first aspect of the present invention, there is provided an in-memory computing circuit structure, the in-memory computing circuit structure comprising: a data module having multiple rows and columns of data, an operation module, and a reference module having multiple rows and columns of data; wherein the data module comprises multiple rows of data units that can be connected in parallel, each data unit uniquely corresponding to an address for storing data; the reference module comprises multiple rows of reference units that can be connected in parallel, the reference units and the data units being composed of the same standard units;

[0006] In response to a received predetermined logic instruction, a current source is input to the data module and the reference module to generate data voltage information and reference voltage information respectively, wherein the predetermined logic instruction is a multi-input address logic instruction or a single-input address logic instruction;

[0007] The operation module outputs a logic result according to the data voltage information input by the data module and the reference voltage information input by the reference module, and executes the predetermined logic instruction according to the logic result, wherein the reference voltage information includes: high-resistance reference voltage information and low-resistance reference voltage information.

[0008] Preferably, at least one row of the plurality of rows of reference cells comprises: a high resistance cell and a low resistance cell.

[0009] Specifically, the in-memory computing circuit structure can perform 1-N bit input logic operations, and the in-memory computing circuit structure includes: two upper and lower sub-arrays and a computing module group;

[0010] Each subarray includes: a reference module having N rows and N+1 columns of reference cells and a data module having at least N+1 columns of data;

[0011] The operation module group includes N operation modules, each operation module has input port 1, input port 2 and input port 3;

[0012] Each column of data in the data module shares a set of operation modules;

[0013] The input ports 1 of the N operation modules of a group of operation modules shared by each column of data are all data voltage information of the column of data, the input port 2 of the nth operation module of the group of operation modules is the reference voltage information generated by the nth column reference unit of the reference module, and the input port 3 of the nth operation module of the group of operation modules is the reference voltage information generated by the n+1th column reference unit of the reference module, wherein 1≤n≤N.

[0014] Furthermore, the in-memory computing circuit structure also includes: a switch unit, which is connected to the data module and the reference module respectively, and after the switch unit is activated, the current source is connected to allow the current source to be input to the data module and the reference module.

[0015] According to a second aspect of the present invention, there is provided a data processing method applied to the above-mentioned in-memory computing circuit structure, the method comprising:

[0016] Receiving a predetermined logic instruction, wherein the predetermined logic instruction is a multi-input address logic instruction or a single-input address logic instruction;

[0017] According to the predetermined logic instruction, corresponding column data in the data module and at least one row of reference cells in the reference module are respectively selected, wherein the corresponding column data and the at least one row of reference cells both include: standard cell resistors, and the at least one row of reference cells includes: high resistance cells and low resistance cells;

[0018] According to the data voltage information of the corresponding column data and the reference voltage information of the at least one reference unit, the operation module outputs a logic result and executes the predetermined logic instruction according to the logic result, wherein the reference voltage information includes: high-resistance reference voltage information and low-resistance reference voltage information.

[0019] Preferably, the method comprises: presetting the resistance state information of each standard cell resistor in each reference cell.

[0020] Further, after receiving the predetermined logic instruction, the method further includes:

[0021] According to the current flowing into the corresponding column data, the corresponding column data outputs data voltage information;

[0022] The reference module outputs reference voltage information according to a current flowing into the at least one reference cell.

[0023] Specifically, according to the data voltage information of the corresponding column data and the reference voltage information of the at least one reference unit, the operation module outputs a logic result including:

[0024] The operation module outputs a logic result according to the resistance state information of the corresponding column data, the data voltage information, the resistance state information of the at least one reference cell and the reference voltage information.

[0025] According to a third aspect of the present invention, there is provided an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the program.

[0026] According to a fourth aspect of the present invention, there is provided a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0027] It can be seen from the above technical solution that the in-memory calculation circuit structure in this technical solution can realize N-bit input logic without the help of a median unit, and the number of logic bits is linearly related to the number of reference unit rows in the reference module, which is convenient to operate and has high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 is a circuit diagram of an in-memory computing circuit structure according to an embodiment of the present invention;

[0030] Figure 2 is an exemplary diagram of an in-memory computing circuit array structure according to an embodiment of the present invention;

[0031] Figure 3 According to an embodiment of the present invention Figure 2 Schematic diagram of the operation module group used in;

[0032] Figure 4A , Figure 4B , Figure 4C is a circuit diagram of an in-memory calculation circuit structure for 2-bit input logic according to an embodiment of the present invention;

[0033] Figure 5A , Figure 5B , Figure 5C is a circuit diagram of an in-memory calculation circuit structure for 3-bit input logic according to an embodiment of the present invention;

[0034] Figure 6 is an exemplary diagram of a circuit array when a maximum of 3-bit input logic is executed according to an embodiment of the present invention;

[0035] Figure 7 is a schematic diagram of an operation module group consisting of three operation modules according to an embodiment of the present invention;

[0036] Figure 8 is a flow chart of a data processing method applied to an in-memory computing circuit structure according to an embodiment of the present invention;

[0037] Fig. 9 It is a schematic block diagram of the system structure of the electronic device 600 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] In view of the fact that the current resistor device parallel-configured reference resistor type in-memory calculation scheme has the problem of cumbersome reference resistor design, requiring more devices to be connected in series and parallel, or adjusting the resistance through transistors, all of which result in the reference resistor module occupying a large area, and the resistance margin is small, and the reliability is poor. Based on this, an embodiment of the present invention provides an in-memory calculation circuit structure, which does not require a median reference resistor, nor does it require adjusting the transistor size. The in-memory calculation function can be realized by connecting standard unit resistors in parallel with the data unit structure and process. The standard unit resistor is a unit manufactured using the same semiconductor and device process, and is composed of a selection transistor and a resistor device. The resistor device can realize the switching between the high resistance state and the low resistance state by electrical methods. In a chip, the standard unit resistor has the same high and low resistance characteristics, that is, the high resistance of all standard unit resistors is the same, and the low resistance is also the same. The circuit is simple to implement, occupies a small area, has high scalability, and high reliability. The following is a detailed description of the embodiments of the present invention in conjunction with the accompanying drawings.

[0040] Figure 1 is a circuit diagram of an in-memory computing circuit structure according to an embodiment of the present invention. Figure 1 As shown, the in-memory computing circuit structure includes: a data module with multiple rows and columns of data, an operation module and a reference module with multiple rows and columns of data. The data module includes multiple rows of data units that can be connected in parallel, and each data unit uniquely corresponds to an address for storing data; the reference module includes: multiple rows of reference units that can be connected in parallel, wherein the reference unit is composed of standard unit resistors that are the same as the data unit structure and process, and no special design and process are required, wherein at least one row of reference units in the multiple rows of reference units includes: a high-resistance unit (the device is in a high-resistance state) and a low-resistance unit (the device is in a low-resistance state). As shown Figure 1 As shown, the first row of reference cells includes: a high resistance cell and a low resistance cell. The resistance state information of the resistance device in each reference cell can be preset.

[0041] See also Figure 1The in-memory calculation circuit structure shown in the figure operates as follows: first, the in-memory calculation circuit receives a predetermined logic instruction, which at least includes the address and logic type of the operation data; then, in response to the address of the operation data in the predetermined logic instruction, the data unit of the corresponding address in the data module is activated, and the current source is input to the data unit; at the same time, in response to the logic type in the predetermined logic instruction, the corresponding reference unit in the reference module is activated, and the current source is input to the reference module. The operation module outputs a logic result according to the data voltage information input by the data module and the reference voltage information input by the reference module, wherein the reference voltage information includes: high-resistance reference voltage information generated by the high-resistance unit column and low-resistance reference voltage information generated by the low-resistance unit column.

[0042] In this actual operation, the predetermined logic instruction may include: a multi-input address logic instruction or a single-input address logic instruction, wherein the multi-input address logic instruction is a logic instruction with 2 to N input addresses, where N is the number of reference unit rows of the reference module, and N≥2.

[0043] Specifically, Figure 1 As shown, the left side is a data module with 2^k rows, which can show two resistance states: high and low (H / L). The high resistance state (HRs) is defined as data 1 and the low resistance state (LRs) is defined as data 0. The right side is a reference module, where R 0,0 For HRs, R 0,1 are LRs, all of which are fixed values; R i,0 =R i,1 (1≤i≤N-1), the resistance state is fixed according to the operation performed; the middle is the operation module, after the signal SAE changes from 0 to 1, Q is the read data, and QB is the inverse of Q.

[0044] The operation module is composed of an analog voltage adder and a comparator. The analog voltage adder can realize V IN+ =2V data , and V IN- =V refH +V refL ; Comparator to V IN+ and V IN- For comparison, if V IN+ >V IN- , then Q is 1, QB is 0; if V IN+ <V IN- , then Q is 0 and QB is 1. Figure 1 A specific implementation of the operation module is shown. The initial states of the signals SAE, SA0, SA1 and SA2 are all 0. Step 1: The signal SAE changes from 0 to 1, and the signal SA0 changes from 0 to 1. V IN+ =V data , VIN- =V refH ; Step 2: Signal SA0 changes from 1 to 0, signal SA1 changes from 0 to 1, V IN+ =2V data , V IN- =V refH +V refL ; Step 3: Signal SA2 changes from 0 to 1, the comparator works, and Q and QB get the result; Step 4: Signals SAE, SA0, SA1 and SA2 all return to the initial state.

[0045] When performing a read operation (corresponding to the single-input address logic instruction above), WL i (0≤i≤2^k-1) is activated in one row, WL ref,0 Activate R 0,0 With R 0,1 , Q is for reading the selected data, and QB is for reading the opposite of the selected data.

[0046] When executing M (2≤M≤N) input logic operations (corresponding to the above multi-input address logic instructions), WL i (0≤i≤2^k-1) activated M rows, WL ref,0 ~WL ref,M-1 Activate R i,0 With R i,1 , 0≤i≤M-1.

[0047] Specifically, for the logical proposition "the selected M bits of data are all 1", R i,0 With R i,1 (1≤i≤M-1) are all set as HRs. If Q is 1, the proposition is true, and if Q is 0, the proposition is false.

[0048] For the logical proposition "Among the selected M bits of data, there are at least m bits of data 1 (2≤m≤M-1)", R i,0 With R i,1 (1≤i≤m-1) is set as HRs, R i,0 With R i,1 (m≤i≤M-1) is set as LRs, if Q is 1, the proposition is true, and if Q is 0, the proposition is false.

[0049] For the logical proposition "There is at least one bit of data 1 among the selected M bits of data", R i,0 With R i,1 (1≤i≤M-1) are all set as LRs, if Q is 1, the proposition is true, and if Q is 0, the proposition is false.

[0050] In one embodiment, the in-memory computing circuit structure can perform 1 to N bit input logic operations. At this time, the in-memory computing circuit structure includes: two upper and lower sub-arrays and an operation module group, wherein each sub-array includes: a data module with N+1 columns of data units, a reference module with N rows and N+1 columns of reference units, and each column of data in the data module shares a set of operation module groups consisting of N operation modules.

[0051] Figure 2 is an example diagram of an in-memory computing circuit array structure according to an embodiment of the present invention. Figure 2 As shown, the minimum array that can perform the highest N-bit input logic operation can be composed of two upper and lower sub-arrays and a computing module group, each sub-array has at least N+1 columns of data and N rows and N+1 columns of reference units, each column of data shares a computing module group consisting of N computing modules, each computing module includes three input ports, namely, data voltage input port 1, low-resistance reference voltage information input port 2, and high-resistance reference voltage information input port 3 (hereinafter referred to as input port 1, input port 2, and input port 3, respectively). For a computing module group shared by a column of data, the input ports 1 of the N computing modules are all used to input the data voltage information of the column of data, the input port 2 of the nth (1≤n≤N) computing module among the N computing modules is used to input the reference voltage information generated by the nth column of the reference unit in the reference module, and the input port 3 of the nth (1≤n≤N) computing module among the N computing modules is used to input the reference voltage information generated by the nth column of the reference unit in the reference module, and the input port 3 of the nth (1≤n≤N) computing module among the N computing modules is used to input the reference voltage information generated by the n+1th column of the reference unit in the reference module.

[0052] Figure 2 In, TG 0,i (0≤i≤N),TG D0,i (0≤i≤N),TG R1,i (0≤i≤N),TG R0,i (0≤i≤N),TG D1,i (0≤i≤N),TG 1,i (0≤i≤N) is a switch unit. When the switch unit is activated, the current source is connected, and the current source is input to the data module and the reference module. In this embodiment, considering that the reference module performs all N-bit input logic operations (there are at least n 1s in the N-bit input, and n is 0 to N), the reference module is set to have N rows of reference units; in actual applications, if the reference module does not need to perform all input logic operations, the reference module can be set to have less than N rows of reference units. The number of columns of data possessed by the data module is greater than the number of rows of reference units possessed by the reference module.

[0053] Figure 3 yes Figure 2 A schematic diagram of the operation module group used in Figure 3As shown, the operation module group is shared by a column of data.

[0054] For the reference module configuration, R 0,i,j =R 1,i,j (0≤i≤N-1, 0≤j≤N), R 0,i,j =LRs(0≤i≤N-1, 0≤j≤i), R 0,i,j =HRs(0≤i≤N-1, i+1≤j≤N).

[0055] When performing a read operation on the upper subarray, TG 0,i (0≤i≤N),TG D0,i (0≤i≤N),TG R0,0 TG R0,1 Activate, WL i (0≤i≤2^k-1) is activated in one row, WL ref0,0 Activate R 0,0,0 With R 0,0,1 (i.e., the first row of reference cells), Q 0,i (0≤i≤N) is the value of the selected data in each column of the upper subarray, Q 1,i (0≤i≤N) is the inverse of the selected data in each column of the upper subarray.

[0056] When performing the logic operation of the M (2≤M≤N) inputs of the upper subarray, TG 0,i (0≤i≤N),TG D0,i (0≤i≤N),TG R0,i (0≤i≤M+1),TG 1,i (0≤i≤M+1) activation, WL i (0≤i≤2^k-1) activated M rows, WL ref0,i Activate R 0,i,j (0≤i≤M-1,0≤j≤M),S i (0≤i≤M-1) is activated, Q i,j (0≤i≤2M-1, 0≤j≤N) is the result of all logical operations on the selected data in each column of the upper subarray.

[0057] When performing a read operation on the lower sub-array, TG 1,i (0≤i≤N),TG D1,i (0≤i≤N),TG R1,0 TG R1,1 Activate, WL i (2^k≤i≤2^(k+1)-1) is activated in one row, WL ref1,0 Activate R 1,0,0 With R 1,0,1 , Q 0,i (0≤i≤N) is the value of the selected data in each column of the upper subarray, Q1,i (0≤i≤N) is the inverse of the selected data in each column of the upper subarray.

[0058] When performing the M (2≤M≤N) input logic operation of the lower subarray, TG 1,i (0≤i≤N),TG D1,i (0≤i≤N),TG R1,i (0≤i≤M+1),TG 0,i (0≤i≤M+1) activation, WL i (2^k≤i≤2^(k+1)-1) activated M rows, WL ref1,i Activate R 1,i,j (0≤i≤M-1,0≤j≤M),S i (0≤i≤M-1) is activated, Q i,j (0≤i≤2M-1, 0≤j≤N) is the result of all logical operations on the selected data in each column of the lower subarray.

[0059] It can be seen from the above description that the in-memory computing circuit structure provided in the embodiment of the present invention can realize N-bit input logic without the help of a median unit, and the number of logic bits is linearly related to the number of reference unit rows in the reference module, which is convenient to operate and has high reliability.

[0060] In order to better understand the present invention, the following Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C as well as Figure 6 The circuit array example structure shown in the figure describes an example. In this example, N=3, k=9, and the read operation and 2-bit input logic (see Figure 4A , Figure 4B , Figure 4C ) and 3-bit input logic (see Figure 5A , Figure 5B , Figure 5C ).

[0061] (I) 2-bit input logic

[0062] like Figure 4A As shown, when performing a read operation, WL i (0≤i≤511) is activated in one row, WL ref,0 Activate R 0,0 (HRs) and R 0,1 (LRs), current source I data flows through the selected data unit and generates a voltage V data , current source I refH Flowing through R 0,0 Generated voltage V refH, current source I refL Flowing through R 0,1 Generated voltage V refL . V IN+ =2V data , V IN- =V refH +V refL For one bit of data, V data Either because the data bit is high impedance and equal to V refH , or equal to V because the data bit is low impedance refL ; For two-bit data, since the data bit has three conditions: HH / HL / LL, V data There will also be three corresponding situations.

[0063] If the selected data cell is in the high resistance state HRs, V data =V refH , V IN+ =2V refH >V refH +V refL =V IN- , Q reads 1. If the selected data cell is in the low resistance state LRs, V data =V refL , V IN+ =2V refL <V refH +V refL =V IN- , Q reads 0.

[0064] like Figure 4B , Figure 4C As shown, when performing a 2-input logic operation, WL i (0≤i≤511) 2 rows are activated, WL ref,0 With WL ref,1 Activate R 0,0 (HRs), R 0,1 (LRs), R 1,0 With R 1,1 .

[0065] like Figure 4B As shown, when performing a 2-input AND / NOT operation logic, R 1,0 With R 1,1 Configured as HRs. Current source I data Flows through the selected 2 parallel data cells, generating a voltage V data , current source I refH Flowing through R 0,0 With R 1,0 Generated voltage V refH , which is the voltage generated by HRs in parallel with HRs, hereinafter referred to as V HH , current source IrefL Flowing through R 0,1 With R 1,1 Generated voltage V refL , which is the voltage generated by LRs in parallel with HRs, hereinafter referred to as V LH . V IN+ =2V data , V IN- =V HH +V LH If both 2-bit data units are HRs, then V data =V HH , V IN+ =2V HH >V HH +V LH =V IN- , Q reads 1, QB reads 0. If the 2-bit data unit is 1-bit HRs and 1-bit LRs respectively, then V data =V LH , V IN+ =2V LH <V HH +V LH =V IN- , Q reads 0, QB reads 1. If both 2-bit data units are LRs, then V data =V LL , V IN+ =2V LL <V HH +V LH =V IN- , Q reads 0, QB reads 1. Thus, Q implements 2-input AND logic, and QB implements 2-input NAND logic.

[0066] like Figure 4C As shown, when performing 2-input OR / OR NOT logic operation, R 1,0 With R 1,1 Configured as LRs. Current source I data Flows through the selected 2 parallel data cells, generating a voltage V data , current source I refH Flowing through R 0,0 With R 1,0 Generated voltage V refH , which is the voltage generated by LRs in parallel with HRs, hereinafter referred to as V LH , current source I refL Flowing through R 0,1 With R 1,1 Generated voltage V refL , which is the voltage generated by connecting LRs in parallel, hereafter referred to as V LL . V IN+ =2V data , V IN- =VLH +V LL If both 2-bit data units are HRs, then V data =V HH , V IN+ =2V HH >V LH +V LL =V IN- , Q reads 1, QB reads 0. If the 2-bit data unit is 1-bit HRs and 1-bit LRs respectively, then V data =V LH , V IN+ =2V LH >V LH +V LL = VIN-, Q reads 1, QB reads 0. If both 2-bit data cells are LRs, then V data =V LL , V IN+ =2V LL <V LH +V LL =V IN- , Q reads 0, QB reads 1. Thus, Q implements 2-input OR logic, and QB implements 2-input OR NOT logic.

[0067] (II) 3-bit input logic

[0068] like Figure 5A , Figure 5B , Figure 5C As shown, when performing a 3-input logic operation, WL i (0≤i≤511) is activated 3 rows, WL ref,0 , WL ref,1 With WL ref,2 Activate R 0,0 (HRs), R 1,0 , R 2,0 , R 0,1 (LRs), R 1,1 With R 2,1 .

[0069] like Figure 5A As shown, when performing a 3-input AND / NOT operation logic, R 1,0 , R 2,0 , R 1,1 With R 2,1 Configured as HRs. Current source I data Flows through the selected 3 parallel data cells, generating a voltage V data , current source I refH Flowing through R 0,0 , R 1,0 With R 2,0 Generated voltage V refH, which is the voltage generated by HRs in parallel HRs in parallel HRs, hereinafter referred to as V HHH , current source I refL Flowing through R 0,1 , R 1,1 With R 2,1 Generated voltage V refL , which is the voltage generated by LRs in parallel with HRs in parallel, hereinafter referred to as V LHH . V IN+ =2V data , V IN- =V HHH +V LHH If the 3-bit data units are all HRs, then V data =V HHH , V IN+ =2V HHH >V HHH +V LHH =V IN- , Q reads 1, QB reads 0. If the 3-bit data unit is 2-bit HRs and 1-bit LRs, then V data =V LHH , V IN+ =2V LHH <V HHH +V LHH =V IN- , Q reads 0, QB reads 1. If the 3-bit data units are 1-bit HRs and 2-bit LRs, or all 3-bit data units are LRs, then V data <V LHH , V IN+ <2V LHH <V HHH +V LHH =V IN- , Q reads 0, QB reads 1. Thus, Q implements 3-input AND logic, and QB implements 3-input NAND logic.

[0070] like Figure 5B As shown, when executing the 3-input large number / large number not operation logic, R 1,0 With R 1,1 Configured as HRs, R 2,0 With R 2,1 Configured as LRs. Current source I data Flows through the selected 3 parallel data cells, generating a voltage V data , current source I refH Flowing through R 0,0 , R 1,0 With R 2,0 Generated voltage V refH , which is the voltage generated by LRs in parallel with HRs in parallel, hereinafter referred to as V LHH , current source IrefL Flowing through R 0,1 , R 1,1 With R 2,1 Generated voltage V refL , which is the voltage generated by LRs in parallel with LRs in parallel with HRs, hereinafter referred to as V LLH . V IN+ =2V data , V IN- =V LHH +V LLH If the 3-bit data units are all HRs, then V data =V HHH , V IN+ =2V HHH >V LHH +V LLH =V IN- , Q reads 1, QB reads 0. If the 3-bit data unit is 2-bit HRs and 1-bit LRs, then V data =V LHH , V IN+ =2V LHH >V LHH +V LLH =V IN- , Q reads 1, QB reads 0. If the 3-bit data unit is 1-bit HRs and 2-bit LRs, then V data =V LLH , V IN+ =2V LLH <V LHH +V LLH =V IN- , Q reads 0, QB reads 1. If the 3-bit data units are all LRs, then V data =V LLL , V IN+ =2V LLL <V LHH +V LLH =V IN- , Q reads 0, QB reads 1. Thus, Q implements 3-input large number logic, and QB implements 3-input large number NOT logic.

[0071] like Figure 5C As shown, when executing 3-input OR / OR NOT logic, R 1,0 , R 2,0 , R 1,1 With R 2,1 Configured as LRs. Current source I data Flows through the selected 3 parallel data cells, generating a voltage V data , current source I refH Flowing through R 0,0 , R 1,0 With R 2,0Generated voltage V refH , which is the voltage generated by LRs in parallel with LRs in parallel with HRs, hereinafter referred to as V LLH , current source I refL Flowing through R 0,1 , R 1,1 With R 2,1 Generated voltage V refL , which is the voltage generated by connecting LRs in parallel with LRs in parallel, hereinafter referred to as V LLL . V IN+ =2V data , V IN- =V LLH +V LLL If the 3-bit data units are all HRs, or 2-bit HRs and 1-bit LR, then V data >V LLH , V IN+ >2V LLH >V LLH +V LLL =V IN- , Q reads 1, QB reads 0. If the 3-bit data unit is 1-bit HRs and 2-bit LRs, then V data =V LLH , V IN+ =2V LLH >V LLH +V LLL =V IN- , Q reads 1, QB reads 0. If the 3-bit data units are all LRs, then V data =V LLL , V IN+ =2V LLL <V LLH +V LLL =V IN- , Q reads 0, QB reads 1. Thus, Q implements 3-input OR logic, and QB implements 3-input OR NOT logic.

[0072] See also Figure 6 As shown, in this example, the minimum array that performs the highest 3-bit input logic operation consists of two upper and lower sub-arrays, each sub-array has 4 columns of data and 3 rows of reference cells, and each column of data shares a set of Figure 7 The illustrated operation module group consists of three operation modules.

[0073] For the reference module configuration, R 0,i,j =R 1,i,j (0≤i≤2, 0≤j≤3), R 0,i,j =LRs(0≤i≤2, 0≤j≤i), R 0,i,j =HRs(0≤i≤2, i+1≤j≤3).

[0074] When performing a read operation on the upper subarray, TG 0,i (0≤i≤3),TG D0,i (0≤i≤3),TG R0,0 TG R0,1 Activate, WL i (0≤i≤511) is activated in one row, WL ref0,0 Activate R 0,0,0 With R 0,0,1 , Q 0,i (0≤i≤3) is the value of the selected data in each column of the upper subarray, Q 1,i (0≤i≤3) is the inverse of the selected data in each column of the upper subarray.

[0075] When performing a 2-input logic operation on the upper subarray, TG 0,i (0≤i≤3),TG D0,i (0≤i≤3),TG R0,i (0≤i≤3),TG 1,i (0≤i≤3) activation, WL i (0≤i≤511) 2 rows are activated, WL ref0,i Activate R 0,i,j (0≤i≤1, 0≤j≤2), S i (0≤i≤1) is activated, Q i,j (0≤i≤3, 0≤j≤3) are respectively the OR / NOR, AND / NAND (or / not, and and / not) operation results of the selected data in each column of the upper subarray.

[0076] When performing a 3-input logic operation on the upper subarray, TG 0,i (0≤i≤3),TG D0,i (0≤i≤3),TG R0,i (0≤i≤4),TG 1,i (0≤i≤4) activation, WL i (0≤i≤511) is activated 3 rows, WL ref0,i Activate R 0,i,j (0≤i≤2, 0≤j≤3), S i (0≤i≤2) is activated, Q i,j (0≤i≤5, 0≤i≤3) are respectively the OR / NOR, MAJ / NMAJ, AND / NAND (or / or not, large number / large number not, and / and not) operation results of the selected data in each column of the upper subarray.

[0077] When performing a read operation on the lower sub-array, TG 1,i (0≤i≤3),TG D1,i (0≤i≤3),TG R1,0 TG R1,1Activate, WL i (512≤i≤1023) is activated in one row, WL ref1,0 Activate R 1,0,0 With R 1,0,1 , Q 0,i (0≤i≤3) is the value of the selected data in each column of the lower subarray, Q 1,i (0≤i≤3) is the inverse of the selected data in each column of the lower subarray.

[0078] When performing a 2-input logic operation on the lower subarray, TG 1,i (0≤i≤3),TG D1,i (0≤i≤3),TG R1,i (0≤i≤3),TG 0,i (0≤i≤3) activation, WL i (512≤i≤1023) 2 rows are activated, WL ref1,i Activate R 1,i,j (0≤i≤1, 0≤j≤2), S i (0≤i≤1) is activated, Q i,j (0≤i≤3, 0≤j≤3) are the OR / NOR, AND / NAND operation results of the selected data in each column of the lower subarray.

[0079] When performing a 3-input logic operation on the lower subarray, TG 1,i (0≤i≤3),TG D1,i (0≤i≤3),TG R1,i (0≤i≤4),TG 0,i (0≤i≤4) activation, WL i (512≤i≤1023) 3 rows are activated, WL ref1,i Activate R 1,i,j (0≤i≤2, 0≤j≤3), S i (0≤i≤2) is activated, Q i,j (0≤i≤5, 0≤i≤3) are the OR / NOR, MAJ / NMAJ, and AND / NAND operation results of the selected data in each column of the lower subarray.

[0080] It can be seen from the above description that the embodiment of the present invention realizes logic operation through two reference voltages, avoids the use of median resistors, requires a very small number of reference units, and has high reliability and strong scalability.

[0081] Based on similar inventive concepts, an embodiment of the present invention also provides a data processing method applied to the above-mentioned in-memory computing circuit structure.

[0082] Figure 8 is a flow chart of the data processing method, such as Figure 8 As shown, the method includes:

[0083] Step 801: Receive a predetermined logic instruction, wherein the predetermined logic instruction is a multi-input address logic instruction or a single-input address logic instruction.

[0084] Step 802, selecting corresponding column data in the data module and at least one row of reference cells in the reference module respectively according to the predetermined logic instruction, wherein the corresponding column data and the at least one row of reference cells both include standard cell resistors, and the at least one row of reference cells includes high resistance cells and low resistance cells.

[0085] In one embodiment, the resistance state information of each standard cell resistor in each reference cell may be preset.

[0086] Step 803, the operation module outputs a logic result according to the data voltage information of the corresponding column data and the reference voltage information of the at least one reference unit, and executes the predetermined logic instruction according to the logic result, wherein the reference voltage information includes: high-resistance reference voltage information and low-resistance reference voltage information.

[0087] Specifically, according to the current flowing into the corresponding column data, the corresponding column data outputs data voltage information; according to the current flowing into the at least one reference unit, the reference module outputs reference voltage information.

[0088] In actual operation, the operation module may output a logic result according to the resistance state information of the corresponding column data, the data voltage information, the resistance state information of the at least one reference cell, and the reference voltage information.

[0089] By selecting the corresponding column data in the data module and at least one row of reference cells in the reference module according to the received predetermined logic instructions, and then the operation module outputs a logic result according to the data voltage information of the corresponding column data and the reference voltage information of the at least one reference cell, and the predetermined logic instruction is executed according to the logic result, the in-memory calculation circuit structure in the embodiment of the present invention can realize N-bit input logic without the help of a median unit, and the number of logic bits is linearly related to the number of reference cell rows in the reference module, and the operation is convenient and reliable.

[0090] The specific execution process of the above steps can be found in the description of the above embodiments, which will not be repeated here.

[0091] This embodiment also provides an electronic device, which may be a desktop computer, a tablet computer, a mobile terminal, etc., but this embodiment is not limited thereto. In this embodiment, the electronic device may be implemented with reference to the above method embodiment and the embodiment of the in-memory computing circuit structure, the contents of which are incorporated herein, and the repeated parts are not repeated.

[0092] Fig. 9 FIG. 6 is a schematic block diagram of a system structure of an electronic device 600 according to an embodiment of the present invention. Fig. 9 As shown, the electronic device 600 may include a central processor 100 and a memory 140; the memory 140 is coupled to the central processor 100. It should be noted that this figure is exemplary; other types of structures may also be used to supplement or replace this structure to implement telecommunication functions or other functions.

[0093] In one embodiment, the data processing function may be integrated into the central processing unit 100. The central processing unit 100 may be configured to perform the following control:

[0094] A predetermined logic instruction is received, wherein the predetermined logic instruction is a multi-input address logic instruction or a single-input address logic instruction.

[0095] According to the predetermined logic instruction, corresponding column data in the data module and at least one row of reference cells in the reference module are respectively selected, wherein the corresponding column data and the at least one row of reference cells both include standard cell resistors, and the at least one row of reference cells includes high resistance cells and low resistance cells.

[0096] According to the data voltage information of the corresponding column data and the reference voltage information of the at least one reference unit, the operation module outputs a logic result and executes the predetermined logic instruction according to the logic result, wherein the reference voltage information includes: high-resistance reference voltage information and low-resistance reference voltage information.

[0097] From the above description, it can be seen that the electronic device provided in the embodiment of the present application selects the corresponding column data in the data module and at least one row of reference cells in the reference module according to the received predetermined logic instructions, and then the operation module outputs a logic result according to the data voltage information of the corresponding column data and the reference voltage information of the at least one reference cell, and executes the predetermined logic instruction according to the logic result. The in-memory calculation circuit structure in the embodiment of the present application can realize N-bit input logic without the help of a median unit, and the number of logic bits is linearly related to the number of reference cell rows in the reference module, and the operation is convenient and reliable.

[0098] In another embodiment, the in-memory computing circuit structure may be configured separately from the central processing unit 100. For example, the in-memory computing circuit structure may be configured as a chip connected to the central processing unit 100 to implement data processing functions under the control of the central processing unit.

[0099] like Fig. 9As shown, the electronic device 600 may further include: a communication module 110, an input unit 120, an audio processing unit 130, a display 160, and a power supply 170. It is worth noting that the electronic device 600 does not necessarily have to include Fig. 9 In addition, the electronic device 600 may also include Fig. 9 For components not shown, reference may be made to the prior art.

[0100] like Fig. 9 As shown, the central processor 100 is sometimes also referred to as a controller or an operation control, and may include a microprocessor or other processor devices and / or logic devices. The central processor 100 receives inputs and controls the operations of various components of the electronic device 600.

[0101] The memory 140 may be, for example, one or more of a cache, a flash memory, a hard drive, a removable medium, a volatile memory, a non-volatile memory or other suitable devices. The above-mentioned information related to the failure may be stored, and a program for executing the relevant information may also be stored. The CPU 100 may execute the program stored in the memory 140 to implement information storage or processing.

[0102] The input unit 120 provides input to the CPU 100. The input unit 120 is, for example, a key or a touch input device. The power supply 170 is used to provide power to the electronic device 600. The display 160 is used to display display objects such as images and text. The display may be, for example, an LCD display, but is not limited thereto.

[0103] The memory 140 may be a solid-state memory, such as a read-only memory (ROM), a random access memory (RAM), a SIM card, etc. It may also be a memory that saves information even when the power is off, can be selectively erased, and is provided with more data, examples of which are sometimes referred to as EPROMs, etc. The memory 140 may also be some other type of device. The memory 140 includes a buffer memory 141 (sometimes referred to as a buffer). The memory 140 may include an application / function storage unit 142, which is used to store application programs and function programs or processes for executing the operation of the electronic device 600 through the central processor 100.

[0104] The memory 140 may also include a data storage unit 143 for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit 144 of the memory 140 may include various drivers for communication functions of the electronic device and / or for executing other functions of the electronic device (such as messaging applications, address book applications, etc.).

[0105] The communication module 110 is a transmitter / receiver 110 that transmits and receives signals via an antenna 111. The communication module (transmitter / receiver) 110 is coupled to the central processor 100 to provide input signals and receive output signals, which may be the same as the case of a conventional mobile communication terminal.

[0106] Based on different communication technologies, multiple communication modules 110 may be provided in the same electronic device, such as a cellular network module, a Bluetooth module and / or a wireless LAN module. The communication module (transmitter / receiver) 110 is also coupled to a speaker 131 and a microphone 132 via an audio processor 130 to provide an audio output via the speaker 131 and receive an audio input from the microphone 132, thereby realizing a common telecommunication function. The audio processor 130 may include any suitable buffer, decoder, amplifier, etc. In addition, the audio processor 130 is also coupled to the central processor 100, so that the sound can be recorded on the local machine through the microphone 132, and the sound stored on the local machine can be played through the speaker 131.

[0107] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned data processing method are implemented.

[0108] To summarize, an embodiment of the present invention provides an in-memory computing circuit structure and a data processing method applied thereto. The in-memory computing circuit structure can realize N-bit input logic without the aid of a median unit, and the number of logic bits is linearly related to the number of reference unit rows in the reference module. The operation is convenient and the reliability is high.

[0109] The preferred embodiments of the present invention are described above with reference to the accompanying drawings. Many features and advantages of these embodiments are clear from this detailed description, and therefore the claims are intended to cover all such features and advantages of these embodiments that fall within their true spirit and scope. In addition, since many modifications and changes are easily conceivable to those skilled in the art, it is not intended to limit the embodiments of the present invention to the precise structure and operation illustrated and described, but all suitable modifications and equivalents falling within its scope may be covered.

[0110] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0111] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0112] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0113] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0114] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. An in-memory computing circuit structure, characterized in that: The in-memory computing circuit structure comprises: a data module having multiple rows and columns of data, an operation module and a reference module having multiple rows and columns of data; wherein the data module comprises multiple rows of data units that can be connected in parallel, and each data unit uniquely corresponds to an address for storing data; the reference module comprises multiple rows of reference units that can be connected in parallel, and the reference units and the data units are composed of the same standard units; In response to a received predetermined logic instruction, a current source is input to the data module and the reference module to generate data voltage information and reference voltage information respectively, wherein the predetermined logic instruction is a multi-input address logic instruction or a single-input address logic instruction; The operation module outputs a logic result according to the data voltage information input by the data module and the reference voltage information input by the reference module, and executes the predetermined logic instruction according to the logic result, wherein the reference voltage information includes: high-resistance reference voltage information and low-resistance reference voltage information.

2. The in-memory computing circuit structure according to claim 1, characterized in that: At least one of the multiple rows of reference cells includes: a high resistance cell and a low resistance cell.

3. The in-memory computing circuit structure according to claim 1, characterized in that: The in-memory computing circuit structure can perform 1-N bit input logic operations, and the in-memory computing circuit structure includes: two upper and lower sub-arrays and a computing module group; Each subarray includes: a reference module having N rows and N+1 columns of reference cells and a data module having at least N+1 columns of data; The operation module group includes N operation modules, each operation module has input port 1, input port 2 and input port 3; Each column of data in the data module shares a set of operation modules; The input port 1 of the N operation modules of a group of operation modules shared by each column of data is the data voltage information of the column of data, the input port 2 of the nth operation module of the group of operation modules is the reference voltage information generated by the nth column of the reference module, and the input port 3 of the nth operation module of the group of operation modules is the reference voltage information generated by the n+1th column of the reference module, where 1≤n≤N.

4. The in-memory computing circuit structure according to claim 1, characterized in that: The in-memory computing circuit structure also includes: a switch unit, which is connected to the data module and the reference module respectively. After the switch unit is activated, the current source is connected so that the current source is input to the data module and the reference module.

5. A data processing method applied to the in-memory computing circuit structure according to any one of claims 1 to 4, characterized in that: The method comprises: Receiving a predetermined logic instruction, wherein the predetermined logic instruction is a multi-input address logic instruction or a single-input address logic instruction; According to the predetermined logic instruction, corresponding column data in the data module and at least one row of reference cells in the reference module are respectively selected, wherein the corresponding column data and the at least one row of reference cells both include: standard cell resistors, and the at least one row of reference cells includes: high resistance cells and low resistance cells; According to the data voltage information of the corresponding column data and the reference voltage information of the at least one reference unit, the operation module outputs a logic result and executes the predetermined logic instruction according to the logic result, wherein the reference voltage information includes: high-resistance reference voltage information and low-resistance reference voltage information.

6. The data processing method of the in-memory computing circuit structure according to claim 5, characterized in that: The method comprises: The resistance state information of each standard cell resistor in each reference cell is preset.

7. The data processing method of the in-memory computing circuit structure according to claim 5, characterized in that: After receiving the predetermined logic instruction, the method further includes: According to the current flowing into the corresponding column data, the corresponding column data outputs data voltage information; The reference module outputs reference voltage information according to a current flowing into the at least one reference cell.

8. The data processing method of the in-memory computing circuit structure according to claim 7, characterized in that: According to the data voltage information of the corresponding column data and the reference voltage information of the at least one reference unit, the operation module outputs a logic result including: The operation module outputs a logic result according to the resistance state information of the corresponding column data, the data voltage information, the resistance state information of the at least one reference cell and the reference voltage information.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the method according to any one of claims 5 to 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 5 to 8 are implemented.

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