Etching method for STI (Shallow Trench Isolation) process and STI process
By combining reactive ion etching and atomic layer etching in the STI process, the problem of damage to silicon layer in semiconductor device manufacturing is solved, and the stability and efficiency of device quality and quality are achieved.
Patent Information
- Application Number
- CN202310940728.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-28
- Publication Date
- 2025-02-14
AI Technical Summary
During semiconductor device manufacturing, as the device size shrinks, the damage to the silicon layer caused by the reactive ion etching (RIE) process becomes serious, affecting device quality, especially during the preparation of small-size (nano-scale) devices.
The trench is etched by a combination of reactive ion etching and atomic layer etching. When the etching reaches a certain depth but does not reach the design depth, switch to atomic layer etching to avoid damage to the silicon layer.
It effectively avoids damage to the silicon layer, ensures the quality and quality stability of semiconductor devices, and avoids leakage faults and connector leakage problems caused by silicon damage.
Smart Images
Figure CN119446910A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to an etching method for a STI process and an STI process. Background Art
[0002] In the semiconductor device manufacturing process, the shallow trench isolation (STI) process is the mainstream device isolation structure. The main steps of the STI process are: depositing a silicon nitride layer on a silicon wafer, forming an isolation oxide layer, applying photoresist, exposing and developing to expose an etching window, etching away the oxide layer (silicon oxide), etching away the silicon nitride and part of the silicon to form a trench, growing an oxide layer in the trench, filling the trench, and removing the silicon nitride layer and silicon oxide layer.
[0003] Among them, the trench is formed by etching. The current STI process is completed by reactive ion etching (RIE) process, which uses plasma generated by the equipment to bombard the silicon wafer to form a trench. When the etched trench is deep, such as Figure 1 As shown in the figure, since plasma bombardment can cause damage to the silicon layer on the sidewall of the trench, when the size of the semiconductor device is large, the quality problem caused by the damage to the silicon layer caused by the RIE process is not obvious and can be ignored. However, with the development, the size of semiconductor devices is gradually reduced, and the damage to the silicon layer will cause quality problems in the prepared semiconductor devices.
[0004] Therefore, in the process of preparing small-sized (nanoscale) semiconductor devices, in order to solve the quality problem of semiconductor devices caused by damaged silicon layers, wet cleaning is used to remove the damaged silicon layers after the grooves are prepared. Although the damaged silicon layers can be removed by wet cleaning, the target groove width and groove depth of the prepared semiconductor devices will be significantly different, which will affect the quality of the semiconductor devices. In the case of a single chip, leakage failures may occur due to increased junction leakage. Summary of the invention
[0005] The object of the present invention is to provide an etching method for STI process and STI process. The etching method adopts a combination of reactive ion etching and atomic layer etching, and will not cause the problem of silicon layer damage when etching the groove.
[0006] The present invention is achieved through the following technical solutions:
[0007] The etching method used in the STI process etches the groove by first performing reactive ion etching and then performing atomic layer etching.
[0008] In the prior art, a reactive ion etching process (RIE process) is directly used to form grooves by bombarding a silicon wafer with plasma, which may cause silicon damage.
[0009] The present invention etches the groove by first performing reactive ion etching and then performing atomic layer etching. The reactive ion etching of the present invention adopts the existing technology. The difference from the existing technology is that when the groove is etched to a certain depth by the existing reactive ion etching process and has not reached the designed depth, the groove is etched by atomic layer etching.
[0010] The present application designs the above-mentioned method of combining reactive ion etching with atomic layer etching to perform trench etching based on the applicant's discovery that:
[0011] When the depth of the trench is large, if plasma bombardment is used entirely on the silicon wafer (semiconductor substrate), silicon damage will occur when etching to the last depth. However, atomic layer etching is used before silicon damage occurs, which can effectively avoid silicon damage.
[0012] The etching method described in the present invention is based on the existing STI process, which can avoid silicon damage and the degree of change of the entire process is not large. On the basis of the existing reactive ion etching process, the groove etching is performed by combining reactive ion etching with atomic layer etching, which will not cause a significant increase in cost.
[0013] As for when to use atomic layer etching, it is determined according to the actual design depth. Different design depths have different critical points for switching from reactive ion etching process to atomic layer etching process.
[0014] Furthermore, a reactive ion etching process is used to etch the remaining The remaining portion of the groove is then etched using an atomic layer etching process.
[0015] Furthermore, when the etching depth is designed to When the reactive ion etching process is used, the remaining The remaining portion of the groove is then etched using an atomic layer etching process.
[0016] Furthermore, when the etching depth is designed to When the reactive ion etching process is used, the remaining The remaining portion of the groove is then etched using an atomic layer etching process.
[0017] Further, the atomic layer etching comprises the following steps:
[0018] S1. Silicon etching: placing a silicon wafer after ion etching to form a groove in a vacuum chamber, introducing a reactive gas and an inert gas into the vacuum chamber, and reacting the reactive gas with the surface silicon of the inner wall of the groove to form free radicals on the silicon surface; wherein the reactive gas is a gas containing HBr or Cl2; the inert gas includes N2, He or Ar, and the specific inert gas can be any one of N2, He and Ar;
[0019] The corrosion of silicon surface by HBr or Cl2 in the reactive gas can form free radicals, which is convenient for subsequent stripping by external force;
[0020] S2. First purification: byproducts generated by silicon etching and unreacted reactive gases are discharged from the vacuum chamber by suction, and the specific suction method can be pump suction;
[0021] S3, stripping free radicals: introducing an ionized gas capable of transmitting energy into the vacuum chamber, and stripping the free radicals formed in step S1 by the gas, the gas used includes H2, Ne, Ar, He, Xe or Kr;
[0022] S4, second purification: the free radicals and gases stripped in step S3 are discharged from the vacuum chamber by suction, and the specific suction method can be pump suction;
[0023] Steps S1-S4 are repeated until the designed trench depth is etched.
[0024] Preferably, the gas used in step S3 is H2. H2 can not only be ionized and transmit energy to strip the free radicals formed in step S1, but also remove HBr or Cl2 that is not reacted and discharged in step S1.
[0025] Furthermore, reactive ion etching and atomic layer etching are performed in the same device or in different devices.
[0026] An STI process includes the following steps:
[0027] Step 1: forming a mask structure on a silicon wafer;
[0028] Step 2: coating photoresist on the mask structure, and forming a window area for trench etching after development;
[0029] Step 3: Use the above etching method to complete the groove etching.
[0030] In the trench etching of step three of the above-mentioned STI process, a combination of reactive ion etching and atomic layer etching is used as an etching method, so that the silicon layer will not be damaged when etching the trench.
[0031] Compared with the prior art, the present invention has the following advantages and beneficial effects:
[0032] 1. The present invention uses atomic layer etching to etch the groove when the existing reactive ion etching process is used to etch the groove to a certain depth but the designed depth is not reached, which can effectively avoid the problem of silicon damage.
[0033] 2. The etching method of the present invention is based on the existing STI process, which can effectively avoid silicon damage caused by etching a deep trench without significantly increasing the modification cost.
[0034] 3. The present invention can minimize the leakage fault problem of semiconductor devices caused by silicon damage in the existing STI process by introducing the atomic layer etching process, and can ensure the quality stability of semiconductor devices by ensuring the overall quality of silicon wafers. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:
[0036] Figure 1 A schematic diagram of etching a groove using an RIE process in the prior art;
[0037] Figure 2 is a process flow chart of the etching method of the present invention;
[0038] Figure 3 It is a process flow chart of atomic layer etching of the present invention;
[0039] Figure 4 This is a process flow chart of the STI process described in Example 2. DETAILED DESCRIPTION
[0040] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.
[0041] Embodiment 1:
[0042] like Figure 2 As shown in FIG. 1 , the etching method used for the STI process is to etch the groove by first performing reactive ion etching and then performing atomic layer etching. The critical point for switching from the reactive ion etching process to the atomic layer etching process is different for different design depths. For example, the reactive ion etching process is used to etch until the remaining depth of the design depth is Then, the remaining portion of the groove is etched using an atomic layer etching process; for example, when the etching depth is designed to be When the reactive ion etching process is used, the remaining Then use the atomic layer etching process to etch the remaining part of the groove; for example: when the etching depth is designed to be When the reactive ion etching process is used, the remaining The remaining portion of the groove is then etched using an atomic layer etching process.
[0043] In this embodiment, the groove is etched by first performing reactive ion etching and then performing atomic layer etching. The reactive ion etching in this embodiment adopts the existing technology. The difference from the existing technology is that when the groove is etched to a certain depth by the existing reactive ion etching process and has not reached the designed depth, the groove is etched by atomic layer etching, which can effectively avoid silicon damage caused by a large groove etching depth.
[0044] At the same time, since the etching method of this embodiment is based on the existing STI process, it can avoid silicon damage and the degree of change of the entire process is not large. On the basis of the existing reactive ion etching process, the groove etching is performed by combining reactive ion etching with atomic layer etching, which will not lead to a significant increase in cost.
[0045] In a specific case, the etching depth is For illustration, reactive ion etching adopts the existing technology, which specifically includes the following steps:
[0046] Step 1: Chemical etching, oxidation and physical etching are performed in sequence until the depth is
[0047] In the second step, chemical etching, physical etching and oxidation are performed in sequence until the depth is
[0048] The third step is to perform chemical etching, physical etching and oxidation in sequence until the depth is
[0049] Since the above-mentioned reactive ion etching is a prior art, the chemical etching parameters, oxidation parameters and physical etching parameters in the first step, the second step and the third step are not described in detail.
[0050] The design depth of this case is Reactive ion etching to It's over, that is, there is still An atomic layer etching process is required to etch the remaining trench depth.
[0051] The existing process of directly using reactive ion etching to complete the entire trench etching includes the following steps:
[0052] Step 1: Chemical etching, oxidation and physical etching are performed in sequence until the depth is
[0053] In the second step, chemical etching, physical etching and oxidation are performed in sequence until the depth is
[0054] The third step is to perform chemical etching, physical etching and oxidation in sequence until the depth is
[0055] Reactive ion etching is used to complete the entire The result of left and right groove etching is that silicon damage is generated in the final stage of groove etching. If the silicon damage is not processed, it will affect the quality of the prepared semiconductor device. If a wet cleaning process is used to remove the silicon damage, it will cause significant differences in the target groove width and groove depth of the prepared semiconductor device. This significant difference will affect the quality of the semiconductor device. In the case of a single chip, leakage failures may occur due to increased junction leakage.
[0056] Therefore, this embodiment adopts a method of first performing reactive ion etching and then performing atomic layer etching to etch the groove, so as to solve the above problem.
[0057] like Figure 3 As shown, the atomic layer etching of this embodiment includes the following steps:
[0058] S1. Silicon etching: placing a silicon wafer after ion etching to form a groove in a vacuum chamber, introducing a reactive gas and an inert gas into the vacuum chamber, and reacting the reactive gas with the surface silicon of the inner wall of the groove to form free radicals on the silicon surface; wherein the reactive gas is a gas containing HBr or Cl2; the inert gas includes N2, He or Ar, and the specific inert gas can be any one of N2, He and Ar;
[0059] The corrosion of silicon surface by HBr or Cl2 in the reactive gas can form free radicals, which is convenient for subsequent stripping by external force.
[0060] S2. First purification: byproducts generated by silicon etching and unreacted reactive gases are discharged from the vacuum chamber by suction. The specific suction method can be pump suction.
[0061] S3, stripping free radicals: introducing an ionized gas capable of transmitting energy into the vacuum chamber, and stripping the free radicals formed in step S1 by the gas, the gas used includes H2, Ne, Ar, He, Xe or Kr; the gas used can be any one of H2, Ne, Ar, He, Xe and Kr, preferably H2, which can not only be ionized and capable of transmitting energy, but also strip the free radicals formed in step S1, and H2 can remove HBr or Cl2 that is not reacted and not discharged in step S1.
[0062] S4, second purification: the free radicals and gases stripped in step S3 are discharged from the vacuum chamber by suction, and the specific suction method can be pump suction.
[0063] Steps S1-S4 are repeated until the designed trench depth is etched.
[0064] This embodiment can minimize the leakage failure problem of semiconductor devices caused by silicon damage in the existing STI process by introducing the atomic layer etching method (ALE method) process, and can ensure the quality stability of semiconductor devices by ensuring the overall quality of silicon wafers.
[0065] In this embodiment, the reactive ion etching and atomic layer etching are performed in the same device or in different devices.
[0066] Embodiment 2:
[0067] like Figure 4 As shown, an STI process includes the following steps:
[0068] Step 1: forming a mask structure on a silicon wafer;
[0069] Specifically: the mask structure of this embodiment includes a silicon nitride layer and an isolation oxide layer, and the specific preparation process is as follows:
[0070] A silicon nitride layer of a certain thickness is first formed on a silicon wafer (semiconductor substrate) by chemical deposition. If there is a silicon oxide layer left on the surface of the silicon wafer from a previous process, the silicon oxide layer is first removed and then the silicon nitride layer is formed;
[0071] A silicon oxide layer is deposited on the silicon nitride layer formed above, and the silicon oxide layer and the silicon nitride layer serve as hard mask layers for trench etching.
[0072] Step 2: Coat photoresist on the mask structure. The thickness of the photoresist can be determined as needed. After development, a window area for trench etching is formed.
[0073] Step 3: Use the etching method described in Example 1 to complete the groove etching;
[0074] The grooves are etched by first performing reactive ion etching and then performing atomic layer etching; that is, when the grooves are etched to a certain depth using the existing reactive ion etching process and have not reached the designed depth, the grooves are etched by atomic layer etching, which can effectively avoid silicon damage caused by a large groove etching depth.
[0075] In a specific etching scheme:
[0076] Reactive ion etching, comprising the following steps:
[0077] Step 1: Chemical etching, oxidation and physical etching are performed in sequence until the depth is
[0078] In the second step, chemical etching, physical etching and oxidation are performed in sequence until the depth is
[0079] The third step is to perform chemical etching, physical etching and oxidation in sequence until the depth is
[0080] Atomic layer etching includes the following steps:
[0081] S1. Silicon etching: placing the silicon wafer after ion etching to form a groove in a vacuum chamber, introducing reactive gas and inert gas into the vacuum chamber, and the reactive gas reacts with the surface silicon of the inner wall of the groove to form free radicals on the silicon surface; wherein the reactive gas is a gas containing HBr or Cl2;
[0082] S2, first purification: by-products produced by silicon etching and unreacted reactive gases are discharged from the vacuum chamber by suction;
[0083] S3, stripping free radicals: introducing an ionized gas capable of transmitting energy into the vacuum chamber, and stripping the free radicals formed in step S1 by the gas, the gas used includes H2, Ne, Ar, He, Xe or Kr;
[0084] S4, second purification: the free radicals and gases stripped in step S3 are discharged from the vacuum chamber by suction;
[0085] Steps S1-S4 are repeated until the designed trench depth is etched.
[0086] Step 4: Remove the mask structure:
[0087] After the oxide layer is grown in the trench or the trench is filled, the silicon oxide protective layer and the silicon nitride layer are removed in sequence, and the trench filling material and the substrate are retained.
[0088] It should be understood that the present invention can be implemented in different forms, and should not be interpreted as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layer and the zone may be exaggerated, and the same reference numerals represent the same elements from beginning to end. It should be understood that when an element or layer is referred to as "on ... ", "adjacent to ... ", "connected to " or "coupled to " other elements or layers, it can be directly on other elements or layers, adjacent to it, connected or coupled to other elements or layers, or there can be an intervening element or layer. On the contrary, when an element is referred to as "directly on ... ", "directly adjacent to ... ", "directly connected to " or "directly coupled to " other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, zones, layers and / or parts, these elements, components, zones, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.
[0089] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. An etching method for STI process, characterized in that: The grooves are etched by first performing reactive ion etching and then performing atomic layer etching.
2. The etching method for STI process according to claim 1, characterized in that: Reactive ion etching process is used to etch to the designed depth remaining The remaining portion of the groove is then etched using an atomic layer etching process.
3. The etching method for STI process according to claim 2, characterized in that: When the etching depth is designed to When the reactive ion etching process is used, the remaining The remaining portion of the groove is then etched using an atomic layer etching process.
4. The etching method for STI process according to claim 2, characterized in that: When the etching depth is designed to When the reactive ion etching process is used, the remaining The remaining portion of the groove is then etched using an atomic layer etching process.
5. The etching method for STI process according to claim 1, characterized in that: The atomic layer etching comprises the following steps: S1. Silicon etching: placing the silicon wafer after ion etching to form a groove in a vacuum chamber, introducing reactive gas and inert gas into the vacuum chamber, and the reactive gas reacts with the surface silicon of the inner wall of the groove to form free radicals on the silicon surface; wherein the reactive gas is a gas containing HBr or Cl2; S2, first purification: by-products produced by silicon etching and unreacted reactive gases are discharged from the vacuum chamber by suction; S3, stripping free radicals: introducing ionized gas capable of transmitting energy into the vacuum chamber, and stripping the free radicals formed in step S1 by the gas; S4, second purification: the free radicals and gases stripped in step S3 are discharged from the vacuum chamber by suction; Steps S1-S4 are repeated until the designed trench depth is etched.
6. The etching method for STI process according to claim 5, characterized in that: The inert gas in step S1 includes N2, He or Ar.
7. The etching method for STI process according to claim 5, characterized in that: The gas used in step S3 includes H2, Ne, Ar, He, Xe or Kr.
8. The etching method for STI process according to claim 7, characterized in that: The gas used in step S3 is H2.
9. The etching method for STI process according to any one of claims 1 to 8, characterized in that: Reactive ion etching and atomic layer etching are performed in the same equipment or in different equipment.
10. A STI process, characterized in that: The following steps are involved: Step 1: forming a mask structure on a silicon wafer; Step 2: coating photoresist on the mask structure, and forming a window area for trench etching after development; Step 3: Complete the groove etching using the etching method described in any one of claims 1 to 9.