Preparation method of integrated packaging structure for realizing wafer back power supply
By using thin silicon oxide layers and nano-silicon through-holes in the preparation of integrated packaging structures, the problems of low device reliability and high production costs caused by epitaxial silicon germanium are solved, and more efficient back-side power supply and higher yield.
Patent Information
- Application Number
- CN202310949480.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-28
- Publication Date
- 2025-02-14
AI Technical Summary
In the existing integrated packaging structure preparation technology with back-powered power, it is necessary to use an epitaxial silicon germanium layer that is difficult to control, resulting in low device reliability, high production cost, and easy damage to the wafer when removing the silicon germanium layer.
By providing the first and second substrates and forming a thin layer of silicon oxide bonding to the front side of the first substrate on one side of the second substrate, the active region and STI trench are formed on the back side of the first substrate, and the rear side of the first substrate is reduced to form an active region and a STI trench. , an inverted trapezoidal buried power rail is formed, and a thin layer of silicon oxide is used as a stop layer during the debonding process, and finally a nano-silicon through-hole is formed on the back of the first substrate to achieve back power supply.
Without the need to grow epitaxial silicon germanium, the production process is easier to control, reducing production costs and the possibility of wafer damage, thereby improving productivity.
Smart Images
Figure CN119446915A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a method for preparing an integrated packaging structure for realizing power supply on the back side of a wafer. Background Art
[0002] In existing integrated circuits, the power transmission network is generally set on the front side of the wafer, so as to provide a steady supply of power and reference voltage (i.e., VDD and VSS) to the active devices on the chip through the power transmission network. However, there is also a signal network in the front area of the wafer. As the size of integrated circuits gradually decreases, it is becoming increasingly difficult to arrange the power transmission network and the signal network to coexist on the front side of the chip.
[0003] In order to optimize the power supply capability to active devices, the existing solution is to provide power supply by wiring from the back side of the wafer. The principle of back side wiring power supply is to separate the power supply transmission network from the signal network by transferring the entire power supply transmission network to the back side of the wafer. In this process, the power rail moves downward to become a buried power rail, which is more conducive to releasing interconnected wiring resources and reducing wiring congestion in the back-end process. In addition, it can provide lower resistance local current distribution and improve power transmission performance.
[0004] At present, the commonly used preparation process of the back wiring power supply device is as follows: first, a layer of germanium silicon layer is epitaxially grown on the front side of the wafer, and then a silicon layer is epitaxially grown again on the surface of the germanium silicon layer, and active areas, STI grooves, and buried power rails and other devices are prepared on the epitaxial silicon layer, and the wafer with the device is bonded to another wafer on the front side, and the germanium silicon layer can be used as a stop layer during wafer grinding, and the back side of the wafer with the device is thinned to the germanium silicon layer and the germanium silicon layer is removed by a wet etching process, and finally a nano silicon via connected to the buried power rail is prepared on the back side of the wafer. However, due to the relatively high technical requirements of the epitaxial germanium silicon layer, it is not easy to control it in the actual production process, so that the reliability of the device is low. In addition, the epitaxial germanium silicon layer also has relatively high requirements for equipment, which in turn increases the production cost in disguise, and it is easy to cause the surface of the wafer to be uneven when removing the germanium silicon layer, thereby damaging the wafer, which further reduces the reliability of the device. Summary of the invention
[0005] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a method for preparing an integrated packaging structure that can power the back side of the wafer, so as to solve the problems that the existing preparation technology of the integrated packaging structure that can power the back side must use an epitaxial germanium silicon layer technology that is difficult to control, resulting in low device reliability and high production cost, and easy damage to the wafer when removing the germanium silicon layer.
[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing an integrated packaging structure for powering the back side of a wafer, the preparation method comprising:
[0007] Providing a first substrate and a second substrate, wherein the first substrate comprises a front surface and a back surface that are oppositely arranged, and forming a second silicon oxide thin layer on one side of the second substrate and bonding it to the front surface of the first substrate;
[0008] Performing a thinning process on the back side of the first substrate, and forming an active area and a plurality of STI trenches on the back side of the thinned first substrate;
[0009] forming an inverted trapezoidal buried power rail on the first substrate, wherein the buried power rail is located between the STI trenches and one end of the buried power rail is distributed in the active area;
[0010] Providing a third substrate and forming a third silicon oxide thin layer on the third substrate, and performing secondary bonding between the third silicon oxide thin layer and the active area;
[0011] performing a debonding process on the second substrate to remove the second substrate to expose the second silicon oxide thin layer;
[0012] removing the second silicon oxide thin layer and forming a nano-through silicon via on the first substrate, wherein the nano-through silicon via penetrates the first substrate and is electrically connected to the buried power rail, thereby realizing back-side power supply;
[0013] Optionally, the second substrate may also be a glass substrate, and the glass substrate is temporarily bonded to the first substrate by bonding adhesive.
[0014] Optionally, a first silicon oxide thin layer may also be formed on the front surface of the first substrate, and the first silicon oxide thin layer is bonded to the second silicon oxide thin layer.
[0015] Optionally, after the first substrate is bonded to the second substrate, hydrogen ions may be implanted by an ion implantation process to form a hydrogen-rich layer in the first substrate, and the first substrate may be heated to 400-600°C so that the first substrate breaks in the hydrogen-rich layer, thereby obtaining the first substrate having a certain thickness, wherein the implantation depth of the hydrogen-rich layer is 250μm-750μm.
[0016] Optionally, the hydrogen ion implantation energy for forming the hydrogen-rich layer is 20 MeV to 60 MeV and the hydrogen ion implantation dose is 4e14 / cm 2 ~6e14 / cm 2 .
[0017] Optionally, after the hydrogen-rich layer is broken, the method further includes performing a high-temperature annealing process at a temperature of at least 1100° C. on the remaining first substrate to drive out remaining hydrogen ions, and performing a chemical mechanical polishing process on the remaining first substrate to obtain a flat and smooth surface.
[0018] Optionally, the process for forming the nano-through silicon via includes one of a laser drilling process, a mechanical drilling process, a deep reactive ion etching process, and a light-assisted electrochemical etching process.
[0019] Optionally, after forming the nano-silicon via, the step of forming a dielectric protection layer and a metal interconnection in the nano-silicon via is also included, wherein the top of the metal interconnection is flush with the top of the dielectric protection layer and the bottom of the metal interconnection is electrically connected to the buried power rail.
[0020] Optionally, the metal interconnect and the buried power rail include refractory metals such as tungsten or ruthenium.
[0021] Optionally, the process of removing the second silicon oxide thin layer includes an anisotropic dry etching process, an isotropic wet etching process or a chemical mechanical polishing process.
[0022] As described above, a method for preparing an integrated packaging structure for powering the back side of a wafer according to the present invention has the following beneficial effects: a first substrate is bonded to a second substrate to support the first substrate, so that the first substrate will not be damaged when the thickness of the first substrate is precisely controlled by a direct thinning process or by forming a hydrogen-rich layer. Then, an active area, an STI groove and a buried power rail are prepared on the front side of the first substrate and then bonded to a third substrate. At this time, a debonding process is performed on the second substrate to recycle and reuse the second substrate. During the debonding process, the second oxide The silicon thin layer and the first silicon oxide thin layer can be used as stop layers to prevent damage to the first substrate. Finally, a nano-silicon through-hole filled with metal interconnects that is electrically connected to the buried power rail is formed on the back side of the first substrate, thereby realizing back-side wiring power supply of the device. Compared with the existing preparation technology of back-side power-supply integrated packaging structure, there is no need to grow an epitaxial germanium silicon layer as a stop layer for thinning the substrate wafer. Therefore, the actual production process is easier to control and can reduce production costs. In addition, there is no need to remove the germanium silicon layer, so the possibility of damage to the substrate wafer can be reduced, thereby greatly improving the production yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 Shown is a flow chart of the steps of a method for preparing an integrated packaging structure for powering the back side of a wafer according to the present invention.
[0024] Figure 2It shows a cross-sectional schematic diagram of bonding between a first substrate and a second substrate in the method for preparing an integrated packaging structure for realizing wafer backside power supply of the present invention.
[0025] Figure 3 It is a cross-sectional schematic diagram showing the formation of a hydrogen-rich layer in a first substrate in the method for preparing an integrated packaging structure for realizing wafer backside power supply of the present invention.
[0026] Figure 4 It is a schematic cross-sectional view of the method for preparing an integrated packaging structure for realizing wafer backside power supply according to the present invention after the first substrate is thinned.
[0027] Figure 5 It is a cross-sectional schematic diagram showing the formation of STI grooves in the method for preparing an integrated packaging structure for realizing wafer backside power supply according to the present invention.
[0028] Figure 6 It is a cross-sectional schematic diagram showing the formation of a buried power rail in the method for preparing an integrated packaging structure for powering the back side of a wafer according to the present invention.
[0029] Figure 7 It is a cross-sectional schematic diagram showing the inversion of the first substrate in the method for preparing an integrated packaging structure for realizing wafer backside power supply of the present invention.
[0030] Figure 8 It is a cross-sectional schematic diagram showing the third substrate and the first substrate after secondary bonding in the method for preparing an integrated packaging structure for realizing wafer backside power supply of the present invention.
[0031] Fig. 9 It is a cross-sectional schematic diagram showing the debonding of the second substrate in the method for preparing the integrated packaging structure for realizing wafer backside power supply of the present invention.
[0032] Fig.10 It shows a cross-sectional schematic diagram of forming nano-silicon vias on a first substrate in the method for preparing an integrated packaging structure for realizing wafer backside power supply of the present invention.
[0033] Fig.11 The cross-sectional schematic diagram shows the formation of metal interconnects in the method for preparing an integrated packaging structure for powering the back side of a wafer according to the present invention.
[0034] Component number description
[0035] 101, first substrate; 1011, front side; 1012, back side; 102, second substrate; 1021, second silicon oxide layer; 103, hydrogen-rich layer; 104, active area; 105, STI trench; 106, buried power rail; 107, third substrate; 1071, third silicon oxide layer; 108, nano-silicon via; 109, metal interconnect; 110, dielectric protection layer; S1 to S6, steps. DETAILED DESCRIPTION
[0036] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0037] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
[0038] It should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the above components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.
[0039] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limitations of the present invention. As used herein, unless the context otherwise clearly indicates, the singular form "a (kind / person)" is also intended to include the plural form. It will also be understood that when the terms "comprise" and its variations, "include" and its variations are used in this specification, the stated features, wholes, steps, operations, elements and / or components are indicated, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations are not excluded.
[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.
[0041] See also Figures 1 to 11 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0042] See also Figures 1 to 11 The present invention provides a method for preparing an integrated packaging structure for powering the back side of a wafer, such as Figure 1 As shown, it is shown as a step flow chart of the preparation method, comprising the following steps:
[0043] S1: providing a first substrate 101 and a second substrate 102, wherein the first substrate 101 includes a front surface 1011 and a back surface 1012 arranged opposite to each other, and forming a second silicon oxide thin layer 1021 on one side of the second substrate 102 and bonding the second silicon oxide thin layer 1021 to the front surface 1011 of the first substrate 101;
[0044] S2: performing a thinning process on the back side 1012 of the first substrate 101 , and forming an active region 104 and a plurality of STI trenches 105 on the thinned back side 1012 of the first substrate 101 ;
[0045] S3: forming an inverted trapezoidal buried power rail 106 on the first substrate 101 , wherein the buried power rail 106 is located between the STI trenches 105 and one end of the buried power rail 106 is distributed in the active area 104 ;
[0046] S4: providing a third substrate 107 and forming a third silicon oxide thin layer 1071 on the third substrate 107, and performing secondary bonding between the third silicon oxide thin layer 1071 and the active region 104;
[0047] S5: performing a debonding process on the second substrate 102 to remove the second substrate 102 to expose the second silicon oxide thin layer 1021;
[0048] S6: removing the second silicon oxide thin layer 1021 and forming a nano-silicon via 108 on the first substrate 101 , wherein the nano-silicon via 108 penetrates the first substrate 101 and is electrically connected to the buried power rail 106 , thereby realizing power supply on the back side 1012 .
[0049] The following is a further introduction to the preparation method of the integrated packaging structure for powering the wafer back side 1012 in conjunction with the accompanying drawings, as follows:
[0050] In step S1, see Figure 1 and Figure 2 , providing a first substrate 101 and a second substrate 102, wherein the first substrate 101 includes a front side 1011 and a back side 1012 arranged opposite to each other, and forming a second silicon oxide thin layer 1021 on one side of the second substrate 102 and bonding to the front side 1011 of the first substrate 101.
[0051] Optionally, the first substrate 101 includes but is not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other semiconductors and a multilayer structure composed of these semiconductors, and its shape can be circular, square or any other desired shape. The second substrate 102 in the present invention is used as a supporting substrate to provide support for the first substrate 101. The second substrate 102 includes but is not limited to one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate. There is no excessive restriction on the type of the second substrate 102 here, and it can be selected according to needs.
[0052] Specifically, in this embodiment, the first substrate 101 is a bare silicon (Si) wafer, and the second substrate 102 is a bare silicon (Si) wafer or a glass substrate. When the second substrate 102 is a bare silicon (Si) wafer, a second silicon oxide thin layer 1021 is also formed on one side of the second substrate 102. The material of the second substrate 102 is consistent with that of the first substrate 101, so as to achieve a better bonding effect. Optionally, a first silicon oxide thin layer may also be formed on the front surface 1011 of the first substrate 101, wherein the first silicon oxide thin layer is bonded to the second silicon oxide thin layer 1021, which can improve the bonding strength between the first substrate 101 and the second substrate 102. When the second substrate 102 is subsequently subjected to a thinning process, the region where the first silicon oxide thin layer and the second silicon oxide thin layer 1021 are bonded can be used as a stop layer for the thinning process, thereby preventing damage to the first substrate 101. The method for forming the first silicon oxide thin layer and the second silicon oxide thin layer 1021 may be in the form of depositing silicon dioxide.
[0053] When the second substrate 102 is a glass substrate, bonding glue is applied on one side of the second substrate 102, and bonding glue is also applied on the front side 1011 of the first substrate 101, so that the first substrate 101 and the second substrate 102 are temporarily bonded by the bonding glue. When bonding with the bonding glue, the debonding process is simpler when the second substrate 102 is subsequently debonded.
[0054] In step S2, see Figure 1 , Figure 4 and Figure 5 , a thinning process is performed on the back side 1012 of the first substrate 101 and an active region 104 and a plurality of STI trenches 105 are formed on the thinned back side 1012 of the first substrate 101 .
[0055] As an example, after the first substrate 101 is bonded to the second substrate 102, an ion implantation process may be used to implant hydrogen ions to form a hydrogen-rich layer 103 in the first substrate 101, and the first substrate 101 may be heated to 400-600°C so that the first substrate 101 breaks in the hydrogen-rich layer 103, thereby obtaining the first substrate 101 having a certain thickness, wherein the implantation depth of the hydrogen-rich layer 103 is 250μm-750μm.
[0056] Specifically, Figure 3 As shown, a hydrogen ion implantation process is performed on the front surface 1011 of the first substrate 101 to form a hydrogen-rich layer 103 in the first substrate 101. The implantation depth of the hydrogen-rich layer 103 is 250 μm to 750 μm, such as 250 μm, 500 μm or 750 μm. The depth of the hydrogen-rich layer 103 in the first substrate 101 can be selected as needed, and no excessive restrictions are made here. Then, a high-temperature annealing process is performed on the first substrate 101. Under the action of high-temperature annealing, the first substrate 101 is broken at the hydrogen-rich layer 103, thereby obtaining a first substrate 101 with a certain thickness, and the remaining first substrate 101 can be used for the preparation of subsequent devices. Optionally, the temperature during high-temperature annealing is 400 to 600°C, such as 400°C, 500°C or 600°C. The temperature during high-temperature annealing can be selected as needed, and no excessive restrictions are made here.
[0057] As an example, the implantation energy of hydrogen ions for forming the hydrogen-rich layer 103 is 20 MeV to 60 MeV, such as 20 MeV, 40 MeV or 60 MeV, and the implantation dose of hydrogen ions is 4e14 / cm 2 ~6e14 / cm 2 , such as 4e14 / cm 2 , 5e14 / cm 2 or 6e14 / cm 2The implantation energy and the implantation dose of hydrogen ions for forming the hydrogen-rich layer 103 can be selected as required and are not excessively limited herein.
[0058] As an example, after the hydrogen-rich layer 103 breaks, the remaining first substrate 101 is subjected to high-temperature annealing at a temperature of at least 1100°C. During this process, the remaining hydrogen ions on the first substrate 101 are removed by the high-temperature annealing, and then the remaining first substrate 101 is subjected to a chemical mechanical polishing process to obtain a flat and smooth surface, which is facilitating the subsequent preparation of devices.
[0059] like Figure 4 As shown, in another embodiment, the first substrate 101 may be subjected to a thinning process, such as a mechanical grinding process or a chemical mechanical polishing process, so as to obtain a first substrate 101 with a certain thickness for subsequent device preparation.
[0060] like Figure 5 As shown, after the first substrate 101 is subjected to a thinning process, an active area 104 is formed on the front side 1011 of the first substrate 101, and then a trench isolation process is performed in the active area 104 to form a plurality of STI trenches 105. In this process, the shape of the STI trenches 105 finally formed can be controlled by controlling etching parameters. The plurality of STI trenches 105 obtained by the above process are independent structures. In addition, oxide is filled in the STI trenches 105 to isolate the active area 104. The type of oxide may be silicon dioxide or other types.
[0061] In step S3, see Figure 1 and Figure 6 , an inverted trapezoidal buried power rail 106 is formed on the first substrate 101 , wherein the buried power rail 106 is located between the STI trenches 105 and one end of the buried power rail 106 is distributed in the active area 104 .
[0062] Specifically, in this embodiment, when forming a plurality of STI grooves 105, an initial power rail groove is reserved on the active area 104, wherein the initial power rail groove exposes the first substrate 101, and then the exposed first substrate 101 is etched using a patterned mask process to form a power rail groove located in the first substrate 101, and a conductive material is filled in each power rail groove to form a buried power rail 106, such as Figure 6 Optionally, after forming the buried power rail 106, a sputtering deposition process is further performed on the active area 104, so that the initial power rail groove is re-sealed to achieve the effect that the buried power rail 106 is completely enclosed by the active area 104. Figure 6As shown, the buried power rail 106 is located between the STI trenches 105 , one end of the buried power rail 106 is distributed in the active region 104 , and the other end of the buried power rail 106 is distributed in the first substrate 101 .
[0063] Alternatively, if Figure 7 As shown, after the buried power rail 106 is formed, the first substrate 101 is also inverted 180 degrees to facilitate bonding of the first substrate 101 with the third substrate 107 .
[0064] In step S4, see Figure 1 and Figure 8 , providing a third substrate 107 and forming a third silicon oxide thin layer 1071 on the third substrate 107 , and performing secondary bonding between the third silicon oxide thin layer 1071 and the active region 104 .
[0065] A third substrate 107 is provided to perform secondary bonding of the third substrate 107 to the first substrate 101. Optionally, the third substrate 107 includes but is not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other semiconductors and a multilayer structure composed of these semiconductors.
[0066] Preferably, the third substrate 107 is a bare silicon (Si) wafer, so that the material of the third substrate 107 is consistent with the material of the first substrate 101, so as to alleviate the thermal mismatch and lattice mismatch when the first substrate 101 is bonded to the third substrate 107, thereby improving the reliability of the final device. A third silicon oxide thin layer 1071 is formed by a thermal oxidation process on one side of the third substrate 107 bonded to the first substrate 101. The method for forming the third silicon oxide thin layer 1071 can be in the form of depositing silicon dioxide, wherein the formed third silicon oxide thin layer 1071 can improve the bonding effect between the third substrate 107 and the first substrate 101.
[0067] In step S5, refer to Figure 1 and Fig. 9 , performing a debonding process on the second substrate 102 to remove the second substrate 102 to expose the second silicon oxide thin layer 1021.
[0068] Specifically, Fig. 9As shown, after the third substrate 107 is bonded to the first substrate 101, the second substrate 102 is thinned or debonded to remove the second substrate 102, exposing the second silicon oxide layer 1021. When the second substrate 102 is a bare silicon (Si) wafer, the second silicon oxide layer 1021 at the bonding interface between the first substrate 101 and the second substrate 102 can serve as a thinning stop layer, thereby not causing damage to the first substrate 101.
[0069] In another embodiment, when the second substrate 102 is a glass substrate, since the first substrate 101 and the second substrate 102 are bonded by bonding adhesive, when the second substrate 102 is debonded, the debonded second substrate 102 can be recycled, thereby reducing production costs. Figure 1 and Fig.10 , remove the second silicon oxide thin layer 1021 and form a nano-silicon via 108 on the first substrate 101, wherein the nano-silicon via 108 penetrates the first substrate 101 and is electrically connected to the buried power rail 106, thereby realizing power supply on the back side 1012.
[0070] After the second substrate 102 is thinned or debonded to remove the second substrate 102, the second silicon oxide thin layer 1021 is removed to form a nano silicon via 108 on the first substrate 101, and the formed nano silicon via 108 penetrates the first substrate 101 and is electrically connected to the buried power rail 106, thereby realizing wiring power supply from the back side of the wafer 1012. Optionally, the process of removing the second silicon oxide thin layer 1021 includes an anisotropic dry etching process, an isotropic wet etching process or a chemical mechanical polishing process. In this embodiment, the chemical mechanical polishing process is selected to achieve accurate removal of the second silicon oxide thin layer 1021.
[0071] As an example, the process for forming the nano-silicon via 108 includes one of a laser drilling process, a mechanical drilling process, a deep reactive ion etching process, and a light-assisted electrochemical etching process. Specifically, in this embodiment, the nano-silicon via 108 is formed by controlling the etching parameters of the deep reactive ion etching process.
[0072] As an example, after forming the nano-silicon via 108, the step of forming a dielectric protection layer 110 and a metal interconnection 109 in the nano-silicon via 108 is also included, wherein the top of the metal interconnection 109 is flush with the top of the dielectric protection layer 110 and the bottom of the metal interconnection 109 is electrically connected to the buried power rail 106.
[0073] Specifically, Fig.11As shown, a dielectric protection layer 110 is first formed in the nano silicon via 108, and the dielectric protection layer 110 covers the two side walls of the nano silicon via 108 and the first substrate 101, and a seed layer is formed in the nano silicon via 108, and the seed layer covers the dielectric protection layer 110 and the bottom wall of the nano silicon via 108, and finally a metal interconnection 109 begins to grow on the bottom wall of the nano silicon via 108, and the bottom of the metal interconnection 109 is electrically connected to the buried power rail 106, and a planarization process is performed on the protruding metal interconnection 109, so that the top of the metal interconnection 109 is flush with the top of the dielectric protection layer 110. In this embodiment, the metal interconnection 109 and the buried power rail 106 include refractory metals such as tungsten or ruthenium or any other suitable metal.
[0074] In summary, the present invention provides a method for preparing an integrated packaging structure for powering the back side of a wafer, wherein a first substrate is bonded to a second substrate to support the first substrate, so that the first substrate will not be damaged when the thickness of the first substrate is precisely controlled by a direct thinning process or by forming a hydrogen-rich layer. Then, an active area, an STI groove, and a buried power rail are prepared on the front side of the first substrate and then bonded to a third substrate. At this time, a debonding process is performed on the second substrate to recycle and reuse the second substrate. During the debonding process, the second silicon oxide thin layer is The first silicon oxide thin layer can be used as a stop layer to prevent damage to the first substrate. Finally, a nano-silicon via filled with metal interconnects is formed on the back of the first substrate and electrically connected to the buried power rail, thereby realizing the back wiring power supply of the device. Compared with the existing preparation technology of the integrated packaging structure with back power supply, there is no need to grow an epitaxial germanium silicon layer as a stop layer for thinning the substrate wafer. Therefore, the actual production process is easier to control and can reduce production costs. In addition, there is no need to remove the germanium silicon layer, so the possibility of damage to the substrate wafer can be reduced, thereby greatly improving the production yield. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0075] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing an integrated packaging structure for realizing back-side power supply of a wafer, characterized in that: The preparation method comprises: Providing a first substrate and a second substrate, wherein the first substrate comprises a front surface and a back surface that are oppositely arranged, and forming a second silicon oxide thin layer on one side of the second substrate and bonding it to the front surface of the first substrate; Performing a thinning process on the back side of the first substrate, and forming an active area and a plurality of STI trenches on the back side of the thinned first substrate; forming an inverted trapezoidal buried power rail on the first substrate, wherein the buried power rail is located between the STI trenches and one end of the buried power rail is distributed in the active area; Providing a third substrate and forming a third silicon oxide thin layer on the third substrate, and performing secondary bonding between the third silicon oxide thin layer and the active area; performing a debonding process on the second substrate to remove the second substrate to expose the second silicon oxide thin layer; The second silicon oxide thin layer is removed and a nano-through silicon via is formed on the first substrate, wherein the nano-through silicon via penetrates the first substrate and is electrically connected to the buried power rail, thereby realizing back side power supply.
2. The preparation method according to claim 1, characterized in that: The second substrate may also be a glass substrate, and the glass substrate is temporarily bonded to the first substrate by bonding adhesive.
3. The preparation method according to claim 1, characterized in that: A first silicon oxide thin layer may also be formed on the front surface of the first substrate, and the first silicon oxide thin layer is bonded to the second silicon oxide thin layer.
4. The preparation method according to claim 1, characterized in that: After the first substrate is bonded to the second substrate, hydrogen ions may be implanted by an ion implantation process to form a hydrogen-rich layer in the first substrate, and the first substrate may be heated to 400-600° C. so that the first substrate breaks in the hydrogen-rich layer, thereby obtaining the first substrate having a certain thickness, wherein the implantation depth of the hydrogen-rich layer is 250 μm-750 μm.
5. The preparation method according to claim 4, characterized in that: The hydrogen ion implantation energy for forming the hydrogen-rich layer is 20 MeV to 60 MeV and the hydrogen ion implantation dose is 4e14 / cm 2 ~6e14 / cm 2 .
6. The preparation method according to claim 4, characterized in that: After the hydrogen-rich layer is broken, the method further includes performing a high-temperature annealing process at a temperature of at least 1100° C. on the remaining first substrate to drive out remaining hydrogen ions, and performing a chemical mechanical polishing process on the remaining first substrate to obtain a flat and smooth back surface.
7. The preparation method according to claim 1, characterized in that: The process of forming the nano-through silicon via includes one of a laser drilling process, a mechanical drilling process, a deep reactive ion etching process, and a light-assisted electrochemical etching process.
8. The preparation method according to claim 1, characterized in that: After forming the nano-silicon via, the method further includes forming a dielectric protection layer and a metal interconnection in the nano-silicon via, wherein the top of the metal interconnection is flush with the top of the dielectric protection layer and the bottom of the metal interconnection is electrically connected to the buried power rail.
9. The preparation method according to claim 8, characterized in that: The metal interconnects and the buried power rails include refractory metals such as tungsten or ruthenium.
10. The preparation method according to claim 1, characterized in that: The process of removing the second silicon oxide thin layer includes an anisotropic dry etching process, an isotropic wet etching process or a chemical mechanical polishing process.