Packaging substrate structure and preparation method thereof

Abstract

The invention provides a packaging substrate structure and a preparation method thereof. The preparation method comprises the following steps: providing a core plate layer; forming a multilayer substrate adding layer covering two opposite surfaces of the core plate layer and electrically connected with the core plate layer; providing an interconnection structure layer which comprises a bottom circuit layer, a bottom dielectric layer and a middle interconnection layer; pressing the interconnection structure layer in a preset area of the substrate adding layer in an inverted manner to obtain a required substrate structure layer; solder mask layers are formed on the two opposite faces of the substrate structure layer, contact holes are formed in the preset positions of the solder mask layers, and at least one contact hole exposes the conductive part of the interconnection structure layer. According to the invention, packaging with finer lines, lighter and lighter weight and higher line density can be realized, and signal transmission loss can be substantially reduced at the same time. Besides, the packaging substrate structure has high design flexibility, and the thickness and the circuit density of the interconnection structure layer can be accurately controlled by adjusting the thickness, the number of layers and the circuit design of each dielectric layer and each circuit layer so as to meet specific packaging requirements.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to a packaging substrate structure and a preparation method thereof. Background Art

[0002] In the past few decades, the global semiconductor industry has developed rapidly following Moore's Law, but now Moore's Law is also facing some problems: First, the reduction in the size of a single transistor in a chip is approaching the physical limit, limiting the further reduction of the chip size; second, when the gate width is less than 5 nanometers, a tunnel effect will occur, and electrons will pass through the channel on their own, causing "0" and "1" logical errors; in addition, the increase in transistor integration leads to an increase in power consumption per unit area, which causes a rise in temperature and affects the performance of the transistor. At the same time, the design and manufacturing costs of chips with 3-nanometer to 5-nanometer processes have also increased significantly.

[0003] Advanced packaging is considered to be the key to surpassing Moore's Law and improving chip performance. Advanced packaging, also known as high-density packaging, improves chip performance by shortening I / O spacing and interconnection length, increasing I / O density. Compared with traditional packaging, advanced packaging has higher memory bandwidth, energy efficiency and performance, as well as thinner chip thickness, and can achieve multi-chip, heterogeneous integration, and high-speed interconnection between chips. In addition, with the rapid development of AI, the application scope of advanced packaging technology is becoming more and more extensive, covering multiple fields such as mobile devices, high-performance computing, and the Internet of Things.

[0004] Advanced packaging technology integrates multiple chips on a packaging substrate to form a 2.5D or 3D packaging structure. In this packaging method, the silicon-based intermediate layer plays a key role. By being embedded in the packaging substrate and serving as a bridge between the packaging substrate and the integrated chip, it significantly improves the wiring density of the packaging substrate, achieves higher integration and smaller wiring spacing. However, there are many challenges in the technical solution using a silicon-based intermediate layer in the prior art. For example, the thermal expansion coefficients between the silicon-based intermediate layer and the materials of each layer of the packaging substrate are different. During the thermal pressing process, the packaging substrate is prone to warping, and excessive substrate warping usually leads to poor contact between the packaging substrate and the silicon-based intermediate layer or the solder joints on the circuit board, seriously affecting the reliability of the product. In addition, the preparation process of the silicon-based intermediate layer is also relatively complicated and the process cost is high.

[0005] Therefore, how to provide a new method for preparing a packaging substrate structure to effectively avoid packaging substrate warping while achieving high-precision circuit layout and significantly reduce process costs has become an important technical problem that technical personnel in this field need to solve urgently.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a packaging substrate structure and a preparation method thereof, so as to solve the problems of packaging substrate warping and high cost in the prior art.

[0008] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a packaging substrate structure, comprising the following steps:

[0009] A core board layer is provided, the core board layer includes a core board and a core board circuit layer, the core board includes a first surface and a second surface arranged opposite to each other, a plurality of core board through holes are formed in the core board, the plurality of core board through holes are arranged at intervals and penetrate the core board, the core board circuit layer includes a core board conductive circuit located on the first surface and the second surface of the core board and a core board conductive column filled in the core board through hole;

[0010] A multi-layer substrate build-up layer is formed covering two opposite sides of the core layer and electrically connected to the core layer, wherein the substrate build-up layer includes a build-up dielectric layer and a build-up circuit layer, a build-up blind hole is formed in the build-up dielectric layer, and the build-up circuit layer includes a build-up conductive circuit located on the upper surface of the build-up dielectric layer and a build-up conductive column filled in the build-up blind hole;

[0011] Providing an interconnection structure layer, the interconnection structure layer comprising a bottom wiring layer, a bottom dielectric layer and an intermediate interconnection layer, the bottom dielectric layer covers the bottom wiring layer, a blind hole is formed in the bottom dielectric layer to expose the bottom wiring layer, the intermediate interconnection layer is located on the bottom dielectric layer and is electrically connected to the bottom wiring layer through the blind hole;

[0012] Flip-chip pressing the interconnection structure layer onto a preset area of ​​the substrate build-up layer on the second surface side of the core board to obtain a desired substrate structure layer;

[0013] A solder resist layer is formed on two opposite sides of the substrate structure layer, and contact holes are formed at preset positions of the solder resist layer, wherein at least one of the contact holes exposes the conductive portion of the interconnection structure layer.

[0014] Optionally, forming a multi-layer substrate build-up layer covering two opposite sides of the core layer comprises the following steps:

[0015] Forming a build-up dielectric layer on two opposite sides of the core layer, and patterning the build-up dielectric layer to form the build-up blind hole penetrating the build-up dielectric layer;

[0016] forming a build-up conductive layer, wherein the build-up conductive layer covers the build-up dielectric layer and fills the build-up blind hole;

[0017] Patterning the build-up conductive layer to obtain the build-up conductive circuit, and the portion of the build-up conductive layer filled into the build-up blind hole serves as the build-up conductive column;

[0018] The steps of preparing the build-up dielectric layer and the build-up circuit layer are repeated until the required number of build-up layers of the substrate are completed.

[0019] Optionally, after forming the multi-layer substrate build-up layers covering two opposite sides of the core layer, the following steps are further included:

[0020] A groove is formed in the multi-layer substrate build-up layer on the second surface side of the core board, the groove opens from the top surface of the multi-layer substrate build-up layer and extends downward to a preset depth to expose the build-up circuit layer.

[0021] Optionally, the interconnection structure layer is flip-chip pressed into the groove, and a surface of the interconnection structure layer away from the bottom surface of the groove is not lower than a top surface of the groove.

[0022] Optionally, the interconnection structure layer is flip-chip pressed into the groove, and a surface of the interconnection structure layer away from the bottom surface of the groove is lower than a top surface of the groove.

[0023] Optionally, before forming the solder resist layer, the following steps are also included:

[0024] forming a dielectric material layer, wherein the dielectric material layer is located on two opposite sides of the substrate structure layer, and the dielectric material layer fills the groove and covers the interconnection structure layer;

[0025] Forming an opening in the dielectric material layer, wherein the opening exposes the bottom wiring layer in the interconnection structure layer and the build-up conductive wiring in the substrate structure layer;

[0026] A conductive interconnection is formed, a portion of which fills the opening to be electrically connected to the bottom wiring layer and the build-up conductive wiring.

[0027] Optionally, the intermediate interconnect layer includes multiple intermediate line layers and multiple intermediate dielectric layers, and the intermediate line layer includes intermediate conductive plugs and intermediate conductive lines connected in sequence from bottom to top, wherein the intermediate conductive plugs located at the bottom layer are filled with the blind holes, and the intermediate conductive lines located at the bottom layer are located on the bottom dielectric layer.

[0028] Optionally, forming the interconnect structure layer comprises the following steps:

[0029] Providing a supporting substrate, and forming a separation layer on the supporting substrate;

[0030] forming the bottom wiring layer;

[0031] forming the bottom dielectric layer covering the bottom wiring layer, and forming the blind hole in the bottom dielectric layer;

[0032] forming a first intermediate conductive layer, wherein the first intermediate conductive layer covers the bottom dielectric layer and fills the blind hole;

[0033] Graphically processing the first intermediate conductive layer to obtain the bottom intermediate conductive line, and the portion of the first intermediate conductive layer filled into the blind hole serves as the bottom intermediate conductive plug;

[0034] forming a first intermediate dielectric layer on the intermediate conductive circuit;

[0035] Forming a blind hole in the first intermediate dielectric layer to expose the bottom intermediate conductive line;

[0036] forming a second intermediate conductive layer, wherein the second intermediate conductive layer covers the first intermediate dielectric layer and fills the blind holes in the first intermediate dielectric layer;

[0037] The second intermediate conductive layer is patterned to obtain a second intermediate conductive line, and a portion of the second intermediate conductive layer filled into the blind hole serves as a second intermediate conductive plug.

[0038] Optionally, the method further includes forming a top dielectric layer on the topmost intermediate circuit layer by using a vacuum pressing method.

[0039] Optionally, before lamination, a step of forming an adhesive film layer on the surface of the interconnection structure layer by vacuum lamination is also included.

[0040] Optionally, the method further includes forming a conductive connection portion, wherein the conductive connection portion is filled in the contact hole on the second surface side of the core board and extends to the surface of the solder resist layer.

[0041] The present invention also provides a packaging substrate structure, comprising:

[0042] A core plate layer, wherein the core plate layer comprises a core plate and a core plate circuit layer, wherein the core plate comprises a first surface and a second surface arranged opposite to each other, wherein a plurality of core plate through holes are arranged in the core plate, wherein the plurality of core plate through holes are arranged at intervals and penetrate the core plate, and wherein the core plate circuit layer comprises a core plate conductive circuit located on the first surface and the second surface of the core plate and a core plate conductive column filled in the core plate through hole;

[0043] A multi-layer substrate build-up layer, covering two opposite sides of the core layer and electrically connected to the core layer, the substrate build-up layer includes a build-up dielectric layer and a build-up circuit layer, the build-up dielectric layer is provided with a build-up blind hole, the build-up circuit layer includes a build-up conductive circuit located on the upper surface of the build-up dielectric layer and a build-up conductive column filled in the build-up blind hole;

[0044] An interconnection structure layer, the interconnection structure layer comprising a bottom wiring layer, a bottom dielectric layer and an intermediate interconnection layer, the bottom dielectric layer covers the bottom wiring layer, and the bottom dielectric layer is provided with a blind hole exposing the bottom wiring layer, the intermediate interconnection layer is located on the bottom dielectric layer and is electrically connected to the bottom wiring layer through the blind hole;

[0045] The interconnection structure layer is flip-chip pressed onto a preset area of ​​the substrate build-up layer on the second surface side of the core board;

[0046] The solder resist layer is located on two opposite sides of the substrate structure layer obtained by laminating the interconnect structure layer and the multiple substrate build-up layers. Contact holes are arranged at preset positions of the solder resist layer, and at least one of the contact holes exposes the conductive part of the interconnect structure layer.

[0047] Optionally, it further includes a groove, which is located in the multi-layer substrate build-up layer on the second surface side of the core board, and the groove opens from the top surface of the multi-layer substrate build-up layer and extends downward to a preset depth to expose the build-up layer circuit layer.

[0048] Optionally, the interconnection structure layer is flip-chip pressed into the groove, and a surface of the interconnection structure layer away from the bottom surface of the groove is not lower than a top surface of the groove.

[0049] Optionally, the interconnection structure layer is flip-chip pressed into the groove, and a surface of the interconnection structure layer away from the bottom surface of the groove is lower than a top surface of the groove.

[0050] Optionally, a glue film layer is provided on the surface of the interconnection structure layer, and the interconnection structure layer and the substrate build-up layer are bonded via the glue film layer.

[0051] Optionally, a conductive connecting portion is further included, wherein the conductive connecting portion is filled in the contact hole on the second surface side of the core board and extends to the surface of the solder resist layer.

[0052] As described above, the present invention provides a package substrate structure and a preparation method thereof, the preparation method comprising the following steps: providing a core board layer; forming a multilayer substrate build-up layer covering two opposite sides of the core board layer and electrically connected to the core board layer; providing an interconnection structure layer, the interconnection structure layer comprising a bottom wiring layer, a bottom dielectric layer and an intermediate interconnection layer, the bottom dielectric layer covers the bottom wiring layer, and a blind hole exposing the bottom wiring layer is formed in the bottom dielectric layer, the intermediate interconnection layer is located on the bottom dielectric layer and is electrically connected to the bottom wiring layer through the blind hole; the interconnection structure layer is flip-chip pressed on a preset area of ​​the substrate build-up layer to obtain the required substrate structure layer; solder resist layers are formed on two opposite sides of the substrate structure layer, and contact holes are formed at preset positions of the solder resist layers, at least one contact hole exposing the conductive part of the interconnection structure layer. The present invention provides a package substrate structure and a preparation method thereof, by flip-chip pressing / embedding / burying the substrate-free interconnection structure layer into the multilayer substrate build-up layer, a finer circuit, thinner and higher circuit density packaging is achieved, while significantly reducing signal transmission loss. The interconnection structure layer of the present invention effectively replaces the traditional silicon-based intermediate layer, and has the advantages of simple preparation process, easy independent preparation, low production cost, etc., and can effectively avoid the warping problem. At the same time, the interconnection structure layer adopts a board-level preparation method, and can be directly cut into unit sizes after preparation. Compared with the wafer-level preparation of the silicon-based intermediate layer, it effectively improves the material utilization rate. In addition, the packaging substrate structure of the present invention has a high degree of design flexibility. By adjusting the thickness, number of layers and circuit design of each dielectric layer and each circuit layer, the thickness and circuit density of the interconnection structure layer can be accurately controlled to meet specific packaging requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 Shown is a process flow chart of a method for preparing a packaging substrate structure of the present invention.

[0054] Figure 2 Shown is a schematic structural diagram of a core board layer provided in Example 1 of the method for preparing a packaging substrate structure of the present invention.

[0055] Figure 3 It is a schematic diagram showing the structure obtained after forming a build-up dielectric layer on two opposite sides of the core layer in the method for preparing the packaging substrate structure of the present invention in Example 1.

[0056] Figure 4 It is a schematic diagram showing the structure obtained after forming a build-up circuit layer on the build-up dielectric layer in the first embodiment of the method for preparing the package substrate structure of the present invention.

[0057] Figure 5 It is a schematic diagram of the structure obtained after forming a multi-layer substrate covering two opposite sides of the core layer in the first embodiment of the method for preparing the packaging substrate structure of the present invention.

[0058] Figure 6 The schematic diagram of the structure obtained after providing a supporting substrate and forming a separation layer on the supporting substrate is shown in the first embodiment of the method for preparing the packaging substrate structure of the present invention.

[0059] Figure 7 It is a schematic diagram of the structure obtained after forming a bottom wiring layer on the separation layer in the first embodiment of the method for preparing the packaging substrate structure of the present invention.

[0060] Figure 8 It is a schematic diagram of the structure obtained after forming a bottom dielectric layer covering the bottom circuit layer in the first embodiment of the method for preparing the packaging substrate structure of the present invention.

[0061] Fig. 9 It is a schematic diagram showing the structure obtained after the middle circuit layer of the bottom layer is formed on the bottom dielectric layer in the first embodiment of the method for preparing the packaging substrate structure of the present invention.

[0062] Fig.10 It is a schematic diagram showing the structure obtained after forming the second intermediate circuit layer on the first intermediate dielectric layer in the first embodiment of the method for preparing the package substrate structure of the present invention.

[0063] Fig.11 It is a schematic diagram showing the structure obtained after forming a third intermediate circuit layer on the second intermediate dielectric layer in the first embodiment of the method for preparing the package substrate structure of the present invention.

[0064] Fig.12 It is a schematic diagram showing the structure obtained after forming a top dielectric layer on the topmost intermediate circuit layer in the first embodiment of the method for preparing the packaging substrate structure of the present invention.

[0065] Fig.13 It is a schematic diagram of a structure obtained after forming a glue film layer on the surface of the interconnection structure layer according to an example of the method for preparing the package substrate structure of the present invention in the first embodiment.

[0066] Fig.14 Another example of the method for preparing the package substrate structure of the present invention in the first embodiment is shown, which is a schematic diagram of the structure obtained after forming a glue film layer on the surface of the interconnection structure layer.

[0067] Fig.15 It is a schematic structural diagram of the substrate structure layer obtained after the interconnection structure layer is flip-chip pressed onto the build-up dielectric layer in the first embodiment of the method for preparing the package substrate structure of the present invention.

[0068] Fig.16Shown is a schematic diagram of the structure obtained after the preparation method of the packaging substrate structure of the present invention forms a solder resist layer on two opposite sides of the substrate structure layer in Example 1, and forms contact holes at preset positions of the solder resist layer, and at least one of the contact holes reveals the conductive part of the interconnect structure layer.

[0069] Fig.17 Shown is a schematic diagram of the structure obtained after the preparation method of the packaging substrate structure of the present invention forms a conductive connection part, a first solder ball electrically connected to the conductive connection part, and a second solder ball filled in the contact hole on the first surface side of the core board in Example 1.

[0070] Fig.18 It is a schematic diagram of the structure obtained after forming a groove in the multi-layer substrate build-up layer on the second surface side of the core board in the preparation method of the packaging substrate structure of the present invention in Example 2.

[0071] Fig.19 It is a schematic diagram of the structure of the substrate structure obtained by flip-chip pressing the interconnection structure layer into the groove in Example 2 of the preparation method of the packaging substrate structure of the present invention, and the side of the interconnection structure layer away from the bottom surface of the groove is not lower than the top surface of the groove.

[0072] Fig. 20 Shown is a schematic diagram of the structure obtained after the preparation method of the packaging substrate structure of the present invention forms a solder resist layer on two opposite sides of the substrate structure layer in Example 2, and forms contact holes at preset positions of the solder resist layer, and at least one of the contact holes reveals the conductive part of the interconnect structure layer.

[0073] Fig.21 The schematic diagram shows the structure obtained after the preparation method of the packaging substrate structure of the present invention forms a conductive connection part, a first solder ball electrically connected to the conductive connection part, and a second solder ball filled in the contact hole on the first surface side of the core board in Example 2.

[0074] Fig. 22 The schematic diagram of the structure of the substrate structure obtained by flip-chip pressing the interconnection structure layer into the groove in Example 3 of the preparation method of the packaging substrate structure of the present invention, wherein the side of the interconnection structure layer away from the bottom surface of the groove is lower than the top surface of the groove.

[0075] Fig.23 It is a schematic diagram showing the structure obtained after forming the dielectric material layer in the third embodiment of the method for preparing the packaging substrate structure of the present invention.

[0076] Fig.24Shown is a schematic diagram of the structure obtained after the preparation method of the packaging substrate structure of the present invention forms an opening in the dielectric material layer in Example 3, and the opening reveals the bottom circuit layer in the interconnect structure layer and the build-up conductive circuit in the substrate structure layer.

[0077] Fig.25 It is a schematic diagram of the structure obtained after forming the conductive interconnection part in the third embodiment of the method for preparing the package substrate structure of the present invention.

[0078] Fig.26 Shown is a schematic diagram of the structure obtained after the preparation method of the packaging substrate structure of the present invention forms a solder resist layer on two opposite sides of the substrate structure layer in Example 3, and forms contact holes at preset positions of the solder resist layer, and at least one of the contact holes reveals the conductive part of the interconnect structure layer.

[0079] Fig. 27 The schematic diagram shows the structure obtained after the preparation method of the packaging substrate structure of the present invention forms a conductive connection part, a first solder ball electrically connected to the conductive connection part, and a second solder ball filled in the contact hole on the first surface side of the core board in Example 3.

[0080] Component number description

[0081] 1 Substrate structure layer

[0082] 11 Core layer

[0083] 111 Core board

[0084] 1111 First Surface

[0085] 1112 Second Surface

[0086] 1113 Core board through hole

[0087] 112 core circuit layer

[0088] 1121 Core board conductive circuit

[0089] 1122 Core board conductive column

[0090] 12 Substrate layer

[0091] 121 Build-up dielectric layer

[0092] 1211 Add-on blind vias

[0093] 122 Add-on circuit layer

[0094] 1221 Add-on conductive circuit

[0095] 1222 Addition layer conductive column

[0096] 13 Interconnection structure layer

[0097] 131 Support substrate

[0098] 132 Separation Layer

[0099] 133 Metal seed layer

[0100] 134 Bottom Line Layer

[0101] 135 bottom dielectric layer

[0102] 1351 Blind hole

[0103] 136 Intermediate interconnect layer

[0104] 1361 Intermediate Line Layer

[0105] 13611 Intermediate conductive plug

[0106] 13612 Intermediate conductive circuit

[0107] 1362 Intermediate dielectric layer

[0108] 137 Top dielectric layer

[0109] 14 Grooves

[0110] 15 Dielectric material layer

[0111] 151 Opening

[0112] 152 Conductive interconnect

[0113] 2 Solder mask

[0114] 21 Contact hole

[0115] 3 Film layer

[0116] 4 Conductive connection

[0117] 5. First solder ball

[0118] 6 Second solder ball

[0119] Steps S1 to S5 DETAILED DESCRIPTION

[0120] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0121] See also Figures 1 to 27 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0122] Embodiment 1

[0123] This embodiment provides a method for preparing a packaging substrate structure. Figure 1 , shown as a process flow chart of the method, comprising the following steps:

[0124] S1: Provide a core board layer, the core board layer includes a core board and a core board circuit layer, the core board includes a first surface and a second surface arranged opposite to each other, a plurality of core board through holes are formed in the core board, the plurality of core board through holes are arranged at intervals and penetrate the core board, the core board circuit layer includes a core board conductive circuit located on the first surface and the second surface of the core board and a core board conductive column filled in the core board through hole;

[0125] S2: forming a multi-layer substrate build-up layer covering two opposite surfaces of the core layer and electrically connected to the core layer, wherein the substrate build-up layer comprises a build-up dielectric layer and a build-up circuit layer, wherein a build-up blind hole is formed in the build-up dielectric layer, and the build-up circuit layer comprises a build-up conductive circuit located on the upper surface of the build-up dielectric layer and a build-up conductive column filled in the build-up blind hole;

[0126] S3: providing an interconnection structure layer, the interconnection structure layer comprising a bottom wiring layer, a bottom dielectric layer and an intermediate interconnection layer, the bottom dielectric layer covers the bottom wiring layer, a blind hole exposing the bottom wiring layer is formed in the bottom dielectric layer, the intermediate interconnection layer is located on the bottom dielectric layer and is electrically connected to the bottom wiring layer through the blind hole;

[0127] S4: flip-chip pressing the interconnection structure layer onto a preset area of ​​the substrate build-up layer on the second surface side of the core board to obtain a desired substrate structure layer;

[0128] S5: forming solder resist layers on two opposite sides of the substrate structure layer, and forming contact holes at preset positions of the solder resist layers, wherein at least one of the contact holes exposes a conductive portion of the interconnect structure layer.

[0129] The specific implementation of each of the above steps is described in detail below with reference to the structure diagram.

[0130] First, see Figure 2, execute the step S1: provide a core board layer 11, the core board layer 11 includes a core board 111 and a core board circuit layer 112, the core board 111 includes a first surface 1111 and a second surface 1112 arranged opposite to each other, a plurality of core board through holes 1113 are formed in the core board 111, the plurality of core board through holes 1113 are arranged at intervals and penetrate the core board 111, the core board circuit layer 112 includes a core board conductive circuit 1121 located on the first surface 1111 and the second surface 1112 of the core board 111 and a core board conductive column 1122 filled in the core board through hole 1113.

[0131] Specifically, the core plate through hole 1113 is formed by mechanical drilling, laser drilling or other suitable methods.

[0132] Specifically, a core conductive material layer may be formed on the first surface 1111 and the second surface 1112 of the core plate 111 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, evaporation, magnetron sputtering, electroplating, chemical plating or other suitable methods, and the core conductive material layer fills the core through hole 1113. Afterwards, the core conductive material layer is patterned by conventional photolithography and etching processes to obtain the core conductive circuit 1121, and the portion of the core conductive material layer filled in the core through hole 1113 serves as the core conductive column 1122.

[0133] Specifically, the material of the core board conductive material layer includes copper, aluminum, nickel, gold, silver, titanium or other suitable conductive materials.

[0134] Please see again Figure 3-Figure 5 , execute the step S2: form a multi-layer substrate build-up layer 12 covering the two opposite sides of the core board layer 11 and electrically connected to the core board layer 11, the substrate build-up layer 12 includes a build-up layer dielectric layer 121 and a build-up layer circuit layer 122, a build-up layer blind hole 1211 is formed in the build-up layer dielectric layer 121, the build-up layer circuit layer 122 includes a build-up layer conductive circuit 1221 located on the upper surface of the build-up layer dielectric layer 121 and a build-up layer conductive column 1222 filled in the build-up layer blind hole 1211.

[0135] As an example, forming a multi-layer substrate build-up layer 12 covering two opposite sides of the core layer 11 includes the following steps:

[0136] (1) Figure 3 As shown, a build-up dielectric layer 121 is formed on two opposite sides of the core layer 11, and the build-up dielectric layer 121 is patterned to form the build-up blind hole 1211 penetrating the build-up dielectric layer 121;

[0137] (2) forming a build-up conductive layer, wherein the build-up conductive layer covers the build-up dielectric layer 121 and fills the build-up blind hole 1211 (not shown);

[0138] (3) Figure 4 As shown, the build-up conductive layer is patterned to obtain the build-up conductive circuit 1221 , and the portion of the build-up conductive layer filled into the build-up blind hole 1211 serves as the build-up conductive column 1222 ;

[0139] (4) Figure 5 As shown, the steps of preparing the build-up dielectric layer 121 and the build-up circuit layer 122 are repeated until the required number of build-up layers 12 of the substrate are completed.

[0140] Specifically, a lamination method, such as vacuum lamination, can be used to form the build-up dielectric layer 121 with good bonding force on two opposite sides of the core layer 11. The material of the build-up dielectric layer 121 includes at least one of epoxy resin-based polymer material, nitrogen-containing polymer material, Ajinomoto deposited film (ABF), polyimide material (PI), fluorine-containing polymer material, polymaleimide triazine resin polymer, and polyphenylene ether. The thickness of the build-up dielectric layer 121 is not excessively limited here.

[0141] Specifically, the method of forming the build-up layer blind via 1211 includes mechanical drilling, laser drilling, plasma etching or other suitable methods.

[0142] Specifically, after forming the build-up blind via 1211 , desmearing is performed to remove smear caused by high temperature generated by the cutting friction of the drill bit during the drilling process.

[0143] Specifically, the material of the build-up conductive layer includes copper, aluminum, nickel, gold, silver, titanium or other suitable conductive materials.

[0144] Specifically, the build-up conductive layer may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, evaporation, magnetron sputtering, electroplating, chemical plating or other suitable methods. Afterwards, the build-up conductive layer is patterned by photolithography and etching processes to obtain the build-up conductive circuit 1221.

[0145] Please see again Figure 6-Figure 12 , perform the step S3: provide an interconnection structure layer 13, the interconnection structure layer 13 includes a bottom wiring layer 134, a bottom dielectric layer 135 and an intermediate interconnection layer 136, the bottom dielectric layer 135 covers the bottom wiring layer 134, and a blind hole 1351 is formed in the bottom dielectric layer 135 to expose the bottom wiring layer 134, the intermediate interconnection layer 136 is located on the bottom dielectric layer 135 and is electrically connected to the bottom wiring layer 134 through the blind hole 1351.

[0146] As an example, the intermediate interconnect layer 136 includes a multi-layer intermediate line layer 1361 and a multi-layer intermediate dielectric layer 1362, and the intermediate line layer 1361 includes an intermediate conductive plug 13611 and an intermediate conductive line 13612 connected in sequence from bottom to top, wherein the intermediate conductive plug 13611 located at the bottom layer is filled with the blind hole 1351, and the intermediate conductive line 13612 located at the bottom layer is located on the bottom dielectric layer 135.

[0147] As an example, forming the interconnect structure layer 13 includes the following steps:

[0148] (1) Figure 6 As shown, a support substrate 131 is provided, and a separation layer 132 is formed on the support substrate 131;

[0149] (2) Figure 7 As shown, the bottom wiring layer 134 is formed on the separation layer 132;

[0150] (3) Figure 8 As shown, the bottom dielectric layer 135 covering the bottom wiring layer 134 is formed, and the blind hole 1351 is formed in the bottom dielectric layer 135;

[0151] (4) forming a first intermediate conductive layer, wherein the first intermediate conductive layer covers the bottom dielectric layer 135 and fills the blind hole 1351 (not shown);

[0152] (5) Fig. 9 As shown, the first intermediate conductive layer is patterned to obtain the bottom intermediate conductive line 13612, and the portion of the first intermediate conductive layer filled into the blind hole 1351 serves as the bottom intermediate conductive plug 13611;

[0153] (6) forming a first intermediate dielectric layer 1362 on the intermediate conductive line 13612 (not shown);

[0154] (7) forming a blind hole in the first intermediate dielectric layer 1362 to expose the bottom intermediate conductive line 13612 (not shown);

[0155] (8) forming a second intermediate conductive layer, wherein the second intermediate conductive layer covers the first intermediate dielectric layer 1362 and fills the blind holes in the first intermediate dielectric layer 1362 (not shown);

[0156] (9) Fig.10As shown, the second-layer intermediate conductive layer is patterned to obtain a second-layer intermediate conductive line 13612 , and the portion of the second-layer intermediate conductive layer filled into the blind hole serves as a second-layer intermediate conductive plug 13611 .

[0157] Specifically, the support substrate 131 includes any one of a glass substrate, a metal substrate, a polymer substrate, a ceramic substrate or a semiconductor substrate. The support substrate 131 plays a supporting role, and the thickness of the support substrate 131 ranges from 100 to 700 microns. In this embodiment, the support substrate 131 uses a glass substrate, which has low cost and is easy to form a separation layer 132 on the surface, and is also conducive to reducing the difficulty of the subsequent stripping process.

[0158] As an example, the separation layer 132 includes polyimide (PI), acrylic resin or other suitable adhesive materials.

[0159] Specifically, the method of forming the separation layer 132 includes a lamination method, a coating method or other suitable methods. In this embodiment, the separation layer 132 is formed by a lamination method, and the material of the separation layer 132 is PI.

[0160] As an example, Figure 7 As shown, before forming the bottom wiring layer 134, a step of forming a metal seed layer 133 on the separation layer 132 by using methods such as physical vapor deposition or chemical copper deposition is also included.

[0161] Specifically, the material of the metal seed layer 133 includes at least one of copper, tungsten and titanium.

[0162] Specifically, in one example, forming the bottom wiring layer 134 includes the following steps: forming the bottom wiring layer 134 on the metal seed layer 133 by methods such as evaporation or magnetron sputtering; then, forming an anti-etching layer on the bottom wiring layer 134, and patterning the anti-etching layer by exposure and development processes; then, based on the patterned anti-etching layer and through a flash etching process, the bottom wiring layer 134 and the metal seed layer 133 are patterned to form a patterned bottom wiring layer 134.

[0163] In another example, forming the bottom wiring layer 134 may also include the following steps: forming an anti-etching layer on the metal seed layer 133, and patterning the anti-etching layer through exposure and development processes; then forming the bottom wiring layer 134 on the anti-etching layer by methods such as evaporation or magnetron sputtering; finally, removing the anti-etching layer, and peeling off the bottom wiring layer 134 on the anti-etching layer while removing the anti-etching layer, and retaining the bottom wiring layer 134 of the desired pattern on the surface of the metal seed layer 133 to form a patterned bottom wiring layer 134.

[0164] Specifically, the material of the bottom wiring layer 134 includes at least one of copper, aluminum, nickel, gold, silver and titanium.

[0165] As an example, the minimum line width range of the bottom wiring layer 134 is ≤2 microns, and the minimum spacing range of the bottom wiring layer 134 is ≤2 microns.

[0166] Specifically, the method of forming the bottom dielectric layer 135 includes lamination, coating, chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the bottom dielectric layer 135 includes silicon dioxide, silicon nitride, poly(p-oxadiazole) (PBO), PI, prepreg with glass fiber (PP) or other suitable dielectric materials.

[0167] Specifically, the blind hole 1351 can be formed by photolithography and etching process or by laser drilling process or mechanical drilling process. In this embodiment, the blind hole 1351 is preferably formed by laser drilling process.

[0168] Specifically, the method for forming the first intermediate conductive layer includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, evaporation, magnetron sputtering, electroplating, chemical plating or other suitable methods. In this embodiment, the first intermediate conductive layer is preferably formed by electroplating or chemical plating.

[0169] Specifically, the material of the first intermediate conductive layer includes at least one of copper, aluminum, nickel, gold, silver and titanium.

[0170] As an example, before forming the first intermediate conductive layer, a step of forming a seed layer on the inner wall of the blind hole 1351 is also included.

[0171] Specifically, the material of the seed layer includes at least one of copper, tungsten and titanium. The seed layer can effectively improve the efficiency and performance of electroplating or chemical plating of the first intermediate conductive layer, and can effectively enhance the bonding strength between the first intermediate conductive layer and the bottom wiring layer 134.

[0172] Specifically, the method for patterning the first intermediate conductive layer includes conventional photolithography and etching processes.

[0173] Specifically, the method for forming the first intermediate dielectric layer 1362 includes lamination, coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable methods. The material of the first intermediate dielectric layer 1362 includes silicon dioxide, silicon nitride, PBO, PI, PP or other suitable dielectric materials.

[0174] Specifically, the blind holes in the first intermediate dielectric layer 1362 may be formed by photolithography and etching processes or by laser drilling processes or mechanical drilling processes.

[0175] Specifically, the second intermediate conductive layer can be formed by the method of forming the first intermediate conductive layer. The material of the second intermediate conductive layer includes at least one of copper, aluminum, nickel, gold, silver and titanium. The method of patterning the second intermediate conductive layer includes conventional photolithography and etching processes.

[0176] As an example, step (9) further includes the step of repeating steps (6) to (9) at least once.

[0177] Specifically, Fig.11 , which is a schematic diagram of a structure obtained after forming a third intermediate circuit layer 1361 on a second intermediate dielectric layer 1362, that is, a schematic diagram of a structure obtained after forming a third intermediate conductive circuit 13612 and a third intermediate conductive plug 13611 filled with a blind hole in the second intermediate dielectric layer 1362. It should be noted that, in this embodiment, the intermediate interconnection layer 136 is formed by forming three layers of the intermediate circuit layer 1361 and two layers of the intermediate dielectric layer 1362, but is not limited thereto.

[0178] As an example, Fig.12 As shown, it also includes the step of forming a top dielectric layer 137 on the topmost intermediate circuit layer 1361 by using a vacuum pressing method.

[0179] Specifically, the top dielectric layer 137 is made of silicon dioxide, silicon nitride, PBO, PI, PP or other suitable dielectric materials.

[0180] Please see again Figure 13-Figure 15 , perform the step S4: flip-chip press-bond the interconnection structure layer 13 to a preset area of ​​the substrate build-up layer 12 on the second surface 1112 side of the core board 111 to obtain the required substrate structure layer 1.

[0181] As an example, before lamination, a step of forming an adhesive film layer 3 on the surface of the interconnection structure layer 13 by using a vacuum lamination method is also included.

[0182] As an example, the material of the adhesive film layer 3 includes DAF, and the thickness of the DAF is in the range of 5 micrometers to 20 micrometers.

[0183] Specifically, in one example, Fig.13 As shown, the top surface of the interconnection structure layer 13 is the middle circuit layer 1361, and the adhesive film layer 3 covers the middle circuit layer 1361. In another example, as Fig.14As shown, the top surface of the interconnect structure layer 13 is a top dielectric layer 137 , and the adhesive film layer 3 covers the top dielectric layer 137 .

[0184] As an example, before lamination, a step of cutting the interconnect structure layer 13 into unit sizes by using a laser cutting process is also included.

[0185] As an example, Fig.15 As shown, the interconnection structure layer 13 is flip-chip pressed onto the build-up dielectric layer 121 by using a hot pressing process to obtain the required substrate structure layer 1 .

[0186] Specifically, the adhesive film layer 3 faces the surface of the multi-layer substrate build-up layer 12 and is bonded to the build-up dielectric layer 121 .

[0187] It should be noted that Figure 15 is an example in which the top surface of the interconnection structure layer 13 is the middle circuit layer 1361 and the adhesive film layer 3 covers the middle circuit layer 1361. However, as mentioned above, in fact, the top surface of the interconnection structure layer 13 can also be the top dielectric layer 137, and is not limited thereto.

[0188] As an example, the method for preparing the package substrate structure further includes a step of removing the support substrate 131 .

[0189] Specifically, the support substrate 131 is removed before flip-chip laminating the interconnect structure layer 13 to the build-up dielectric layer 121 or after laminating.

[0190] Specifically, in one example, before lamination, the support substrate 131 and the separation layer 132 may be removed by laser removal, mechanical stripping, chemical stripping, plasma stripping, heat treatment or other suitable methods. In another example, after lamination, that is, after laminating the interconnect structure layer 13 on the substrate build-up layer 12, the support substrate 131 and the separation layer 132 may be removed by laser removal, mechanical stripping, chemical stripping, plasma stripping, heat treatment or other suitable methods. In this embodiment, it is preferred that the support substrate 131 and the separation layer 132 be removed after laminating the interconnect structure layer on the substrate build-up layer 12 to avoid potential contamination or oxidation risk of the bottom wiring layer 134 by the external environment.

[0191] Please see again Figure 16-Figure 17 , perform the step S5: forming a solder resist layer 2 on two opposite sides of the substrate structure layer 1, and forming contact holes 21 at preset positions of the solder resist layer 2, at least one of the contact holes 21 exposing the conductive portion of the interconnect structure layer 13.

[0192] As an example, the material of the solder resist layer 2 includes dry film type solder resist.

[0193] Specifically, Fig.16 As shown, the solder resist layer 2 can be formed on two opposite sides of the substrate structure layer 1 by vacuum pressing, and the contact hole 21 can be formed by exposing and developing the solder resist layer 2.

[0194] As an example, Fig.17 As shown, the step of forming a conductive connection portion 4 is also included. The conductive connection portion 4 is filled in the contact hole 21 on the second surface 1112 side of the core board 111 and extends to the surface of the solder resist layer 2.

[0195] As an example, the conductive connection portion 4 is electrically connected to the circuit layer exposed by the contact hole 21 .

[0196] Specifically, the conductive connection portion 4 is electrically connected to the build-up circuit layer 122 and the bottom circuit layer 134 located on the second surface 1112 side of the core board 111. The area where the conductive connection portion 4 is electrically connected to the build-up circuit layer 122 located on the second surface 1112 side of the core board 111 is a low-density connection area, and the area where the conductive connection portion 4 is electrically connected to the bottom circuit layer 134 located on the second surface 1112 side of the core board 111 is a high-density connection area.

[0197] As an example, the step of forming a first solder ball 5 electrically connected to the conductive connection part 4 is also included.

[0198] As an example, the method further includes a step of flip-chip bonding at least two chips to the first solder balls 5 (not shown).

[0199] Specifically, each chip includes two different types of bumps, which are high-density bumps and low-density bumps. When the chip is flip-chip bonded to the first solder ball 5, the high-density bumps are correspondingly connected to the high-density connection area, and the low-density bumps are correspondingly connected to the low-density connection area.

[0200] As an example, the step of forming a second solder ball 6 is also included, and the second solder ball 6 is filled in the contact hole 21 on the first surface 1111 side of the core board 111, and the second solder ball 6 is electrically connected to the build-up circuit layer 122 located on the first surface 1111 side of the core board 111.

[0201] Specifically, in this embodiment, a printing process is used to print solder in the contact hole 21 on the first surface 1111 side of the core board 111, and the solder is reflowed by heat through a reflow process to form the second solder ball 6. The solder includes any one of tin solder, silver solder and gold-tin alloy solder.

[0202] As an example, a metal connection layer (not shown) is further formed between the second solder ball 6 and the build-up circuit layer 122 .

[0203] Specifically, in this embodiment, the metal connection layer is formed by electroplating, chemical plating or other suitable methods, and the material of the metal connection layer includes at least one of nickel, palladium and gold.

[0204] The present embodiment provides a method for preparing a packaging substrate structure, which realizes high-density interconnection of two or more chips by flip-chip bonding an interconnection structure layer without a substrate on a multi-layer substrate build-up layer. Compared with the traditional silicon-based intermediate layer technology, the interconnection structure layer in the present embodiment has no substrate, has a thinner thickness and a smaller thermal expansion coefficient, thereby significantly reducing the risk of warping of the packaging substrate structure and effectively improving product reliability. At the same time, the present embodiment also avoids the process complexity problems in the preparation of the silicon-based intermediate layer (such as using the CMP process to thin the silicon substrate, etc.), effectively simplifies the production process and reduces production costs. In addition, the present embodiment does not need to form grooves in the core layer, which further simplifies the process flow. The present embodiment is particularly suitable for the packaging of low-power and low-density (I / O pin number) chips, and can form a smaller number of circuit layers to obtain a compact and thin chip packaging structure.

[0205] Embodiment 2

[0206] This embodiment provides a method for preparing a packaging substrate structure. Figure 18-Figure 21 As shown, the method for preparing the package substrate structure in this embodiment is basically the same as the method for preparing the package substrate structure in the first embodiment, except that:

[0207] After forming the multi-layer substrate build-up layer 12 covering two opposite sides of the core layer 11, the following steps are also included:

[0208] like Fig.18 As shown, a groove 14 is formed in the multi-layer substrate build-up layer 12 on the second surface 1112 side of the core board 111 . The groove 14 opens from the top surface of the multi-layer substrate build-up layer 12 and extends downward to a preset depth to expose the build-up circuit layer 122 .

[0209] Specifically, the method for forming the groove 14 includes laser processing, mechanical processing, photolithography etching or other suitable methods. In this embodiment, the groove 14 is preferably formed by photolithography and etching. In the process of forming the groove 14 by photolithography and etching, the build-up circuit layer 122 can be used as an etching stop layer to facilitate accurate control of the depth of the groove 14.

[0210] As an example, Fig.19As shown, the interconnection structure layer 13 is flip-chip pressed into the groove 14 , and a side of the interconnection structure layer 13 away from the bottom surface of the groove 14 is not lower than the top surface of the groove 14 .

[0211] The other steps of the method for preparing the package substrate in this embodiment are the same as the other steps of the method for preparing the package substrate in Embodiment 1. Please refer to Embodiment 1 for details, which will not be described again here.

[0212] The present embodiment provides a method for preparing a packaging substrate structure, which realizes high-density interconnection of two or more chips by flip-chip embedding a substrate-free interconnection structure layer into the groove of a multi-layer substrate layer. The interconnection structure layer formed in the present embodiment is thin in thickness, avoiding the need to form deeper grooves, which not only effectively reduces the risk of asymmetric packaging substrate structure, but also helps to reduce the overall weight of the packaging substrate structure, and promotes the development of chip packaging towards miniaturization and lightweight. In addition, the present embodiment is suitable for high-power and high-density chip packaging that requires multiple line layers. The present embodiment can maintain the compactness and reliability of the packaging structure while ensuring the interconnection density. In addition, the design of directly forming a solder mask on the back of the interconnection structure layer in the present embodiment can effectively reduce dielectric loss, reduce delays in the signal transmission process, and significantly improve signal transmission efficiency and reliability.

[0213] Embodiment 3

[0214] This embodiment provides a method for preparing a packaging substrate structure. Figure 22-Figure 27 As shown, the preparation method of the package substrate structure in this embodiment is basically the same as the preparation method of the package substrate structure in the second embodiment, and the difference is that:

[0215] As an example, Fig. 22 As shown, the interconnection structure layer 13 is flip-chip pressed into the groove 14 , and a surface of the interconnection structure layer 13 away from the bottom surface of the groove 14 is lower than the top surface of the groove 14 .

[0216] As an example, before forming the solder resist layer 2, the following steps are also included:

[0217] (1) Fig.23 As shown, a dielectric material layer 15 is formed, and the dielectric material layer 15 is located on two opposite sides of the substrate structure layer 1, and the dielectric material layer 15 fills the groove 14 and covers the interconnection structure layer 13;

[0218] (2) Fig.24 As shown, an opening 151 is formed in the dielectric material layer 15, and the opening 151 exposes the bottom wiring layer 134 in the interconnection structure layer 13 and the build-up conductive circuit 1221 in the substrate structure layer 1;

[0219] (3) Fig.25 As shown, a conductive interconnect 152 is formed, a portion of which fills the opening 151 to be electrically connected to the bottom wiring layer 134 and the build-up conductive wiring 1221 .

[0220] Specifically, the dielectric material layer 15 includes at least one of epoxy resin-based polymer materials, nitrogen-containing polymer materials, ABF, PI, fluorine-containing polymer materials, polymaleimide triazine resin polymers, and polyphenylene ether.

[0221] Specifically, the opening 151 is formed by mechanical drilling, laser drilling or other suitable methods.

[0222] Specifically, the opening 151 formed in the dielectric material layer 15 close to the groove 14 side simultaneously exposes the bottom wiring layer 134 in the interconnect structure layer 13 and the build-up layer conductive circuit 1221 in the substrate structure layer 1, so that the conductive interconnection portion 152 filling the opening 151 is electrically connected to the bottom wiring layer 134 and the build-up layer conductive circuit 1221; and the opening 151 formed in the dielectric material layer 15 away from the groove 14 side only exposes the build-up layer conductive circuit 1221 in the substrate structure layer 1, so that the conductive interconnection portion 152 filling the opening 151 is electrically connected to the build-up layer conductive circuit 1221.

[0223] As an example, before forming the conductive interconnection 152 , a step of forming a conductive seed layer (not shown) on the inner wall of the opening 151 by electroplating or chemical plating is also included.

[0224] Specifically, the material of the conductive seed layer includes at least one of copper, tungsten and titanium.

[0225] Specifically, the material of the conductive interconnection 152 includes at least one of copper, aluminum, nickel, gold, silver and titanium.

[0226] As an example, before forming the solder resist layer 2 , a step of forming an external conductive circuit 16 on the dielectric material layer 15 is also included.

[0227] As an example, the external conductive line 16 is located on the dielectric material layer 15 away from the groove 14 .

[0228] Specifically, the external conductive circuit 16 is located on the dielectric material layer 15 on the first surface 1111 side of the core board 111 .

[0229] As an example, the material of the external conductive circuit 16 and the build-up conductive circuit 1221 is the same.

[0230] Specifically, the material of the external conductive circuit 16 includes copper, aluminum, nickel, gold, silver, titanium or other suitable conductive materials.

[0231] As an example, the external conductive trace 16 and the conductive interconnect 152 are formed by the same process step.

[0232] Specifically, in this embodiment, after the external conductive circuit 16 and the conductive interconnection portion 152 are formed simultaneously, the solder resist layer 2 is formed on two opposite sides of the substrate structure layer 1 by vacuum pressing.

[0233] As an example, the conductive interconnection portion 152 is electrically connected to the conductive connection portion 4 .

[0234] The other steps of the method for preparing the package substrate in this embodiment are the same as the other steps of the method for preparing the package substrate in Embodiment 2. Please refer to Embodiment 1 and Embodiment 2 for details, which will not be described again here.

[0235] The present embodiment provides a method for preparing a packaging substrate structure, which not only realizes high-density interconnection of two or more chips, but also significantly improves the packaging integration by flipping and embedding the substrate-free interconnection structure layer in the groove. The complete embedding of this interconnection intermediate layer effectively enhances the electromagnetic shielding performance of the packaging substrate structure and reduces the interference of external signals, thereby ensuring the efficiency and stability of signal transmission. In addition, the thickness of the interconnection structure layer formed in this embodiment is relatively thin, which reduces the requirement for the depth of the groove, thereby effectively reducing the risk of asymmetry in the packaging substrate structure and improving the reliability of the overall structure. The present embodiment is particularly suitable for high-power and high-density chip packaging, and can meet the requirements of multiple line layers while obtaining a thin and light chip packaging structure.

[0236] Embodiment 4

[0237] like Fig.17As shown, this embodiment provides a package substrate structure, which is obtained by the preparation method of embodiment 1, and the package substrate structure includes: a core board layer 11, a multi-layer substrate build-up layer 12, an interconnection structure layer 13 and a solder resist layer 2, wherein the core board layer 11 includes a core board 111 and a core board circuit layer 112, the core board 111 includes a first surface 1111 and a second surface 1112 arranged opposite to each other, and a plurality of core board through holes 1113 are arranged in the core board 111, and the plurality of core board through holes 1113 are arranged at intervals and The core board 111 is penetrated, and the core board circuit layer 112 includes a core board conductive circuit 1121 located on the first surface 1111 and the second surface 1112 of the core board 111 and a core board conductive column 1122 filled in the core board through hole 1113; the multi-layer substrate build-up layer 12 covers the opposite sides of the core board layer 11 and is electrically connected to the core board layer 11, and the substrate build-up layer 12 includes a build-up layer dielectric layer 121 and a build-up layer circuit layer 122, and the build-up layer dielectric layer 121 is provided with a build-up layer blind hole 1211, and the build-up layer circuit layer 122 is provided with a build-up layer blind hole 1211. The layer circuit layer 122 includes a build-up conductive circuit 1221 located on the upper surface of the build-up dielectric layer 121 and a build-up conductive column 1222 filled in the build-up blind hole 1211; the interconnection structure layer 13 includes a bottom circuit layer 134, a bottom dielectric layer 135 and an intermediate interconnection layer 136, the bottom dielectric layer 135 covers the bottom circuit layer 134, and the bottom dielectric layer 135 is provided with a blind hole 1351 (not shown) exposing the bottom circuit layer 134, the intermediate interconnection layer 136 is located on the bottom The first dielectric layer 135 is on the second dielectric layer 135 and is electrically connected to the bottom wiring layer 134 through the blind hole 1351; the interconnection structure layer 13 is flip-chip pressed on a preset area of ​​the substrate build-up layer 12 on the second surface 1112 side of the core board 111; the solder resist layer 2 is located on the opposite sides of the substrate structure layer 1 obtained after the interconnection structure layer 13 and the multiple layers of the substrate build-up layer 12 are pressed together, and contact holes 21 (not shown) are provided at preset positions of the solder resist layer 2, and at least one of the contact holes 21 exposes the conductive part of the interconnection structure layer 13.

[0238] As an example, the intermediate interconnect layer 136 includes a multi-layer intermediate line layer 1361 and a multi-layer intermediate dielectric layer 1362, and the intermediate line layer 1361 includes an intermediate conductive plug 13611 and an intermediate conductive line 13612 connected in sequence from bottom to top, wherein the intermediate conductive plug 13611 located at the bottom layer is filled with the blind hole 1351, and the intermediate conductive line 13612 located at the bottom layer is located on the bottom dielectric layer 135.

[0239] As an example, a top dielectric layer 137 is further provided above the middle circuit layer 1361 .

[0240] As an example, a film layer 3 is provided on the surface of the interconnection structure layer 13 , and the interconnection structure layer 13 is bonded to the substrate build-up layer 12 via the film layer 3 .

[0241] As an example, the package substrate structure further includes a conductive connection portion 4 , which is filled in the contact hole 21 on the second surface 1112 side of the core board 111 and extends to the surface of the solder resist layer 2 .

[0242] As an example, the conductive connection portion 4 is electrically connected to the circuit layer exposed by the contact hole 21 .

[0243] As an example, the package substrate structure further includes a first solder ball 5 , and the first solder ball 5 is electrically connected to the conductive connection part 4 .

[0244] As an example, the packaging substrate structure also includes a second solder ball 6, which is filled in the contact hole 21 on the first surface 1111 side of the core board 111, and the second solder ball 6 is electrically connected to the build-up circuit layer 122 located on the first surface 1111 side of the core board 111.

[0245] As an example, a metal connection layer (not shown) is further formed between the second solder ball 6 and the build-up circuit layer 122 .

[0246] The packaging substrate structure provided in this embodiment avoids the warping problem caused by the mismatch of thermal expansion coefficients between the silicon-based intermediate layer and the various layers of the packaging substrate materials and the process complexity problem in the preparation of the silicon-based intermediate layer by using a substrate-free interconnection structure layer, which significantly improves the reliability of the product and reduces the production complexity and production cost. In addition, this embodiment does not require the formation of grooves in the core layer, further simplifying the process flow. In addition, this embodiment is particularly suitable for the packaging of low-power and low-density (I / O pin count) chips, and can form a smaller number of circuit layers to obtain a compact and thin chip packaging structure.

[0247] Embodiment 5

[0248] like Fig.21 As shown, this embodiment provides a packaging substrate structure, which is obtained by the preparation method of Example 2, and the packaging substrate structure includes a groove 14, and the groove 14 is located in the multi-layer substrate build-up layer 12 on the side of the second surface 1112 of the core board 111, and the groove 14 opens from the top surface of the multi-layer substrate build-up layer 12 and extends downward to a preset depth to expose the build-up layer circuit layer 122.

[0249] As an example, the interconnection structure layer 13 is flip-chip pressed into the groove 14 , and a surface of the interconnection structure layer 13 away from the bottom surface of the groove 14 is not lower than the top surface of the groove 14 .

[0250] The package substrate structure provided in this embodiment realizes high-density interconnection of two or more chips by embedding the substrate-free interconnection structure layer in a groove in an inverted manner. At the same time, the risk of asymmetric package substrate structure is effectively reduced, the overall weight of the package substrate structure is reduced, and the chip packaging is promoted to be miniaturized and lightweight. In addition, the package substrate structure of this embodiment is suitable for high-power and high-density chip packaging, and can maintain the compactness and reliability of the package structure while ensuring the interconnection density. In addition, the design of the package substrate structure of this embodiment that directly forms a solder mask on the back of the interconnection structure layer effectively reduces dielectric loss and signal transmission delay, and significantly improves signal transmission efficiency and reliability.

[0251] Embodiment 6

[0252] like Fig. 27 As shown, this embodiment provides a packaging substrate structure, and the packaging substrate structure is obtained by the preparation method of embodiment three.

[0253] As an example, the interconnection structure layer 13 is flip-chip pressed into the groove 14 , and a surface of the interconnection structure layer 13 away from the bottom surface of the groove 14 is lower than the top surface of the groove 14 .

[0254] As an example, the package substrate structure further includes a dielectric material layer 15 , which is located on two opposite sides of the substrate structure layer 1 , and the dielectric material layer 15 fills the groove 14 and covers the interconnect structure layer 13 .

[0255] As an example, an opening 151 is provided in the dielectric material layer 15 , and the opening 151 exposes the bottom wiring layer 134 in the interconnection structure layer 13 and the build-up conductive circuit 1221 in the substrate structure layer.

[0256] As an example, the package substrate structure further includes a conductive interconnect 152 , a portion of which fills the opening 151 to be electrically connected to the bottom wiring layer 134 and the build-up conductive wiring 1221 .

[0257] As an example, the package substrate structure further includes an external conductive circuit 16 , and the external conductive circuit 16 is located on the dielectric material layer 15 away from the groove 14 .

[0258] Specifically, the external conductive circuit 16 is located on the dielectric material layer 15 on the first surface 1111 side of the core board 111 .

[0259] As an example, the conductive interconnection portion 152 is electrically connected to the conductive connection portion 4 .

[0260] The package substrate structure provided in this embodiment realizes high-density interconnection of two or more chips by completely burying the interconnection structure layer without substrate in the groove, which significantly improves the package integration. This structural design effectively enhances the electromagnetic shielding performance of the package substrate structure, reduces external signal interference, and ensures the efficiency and stability of signal transmission. In addition, the package substrate structure of this embodiment is particularly suitable for high-power and high-density chip packaging, which can meet the requirements of multiple line layers while obtaining a thin and light chip packaging structure.

[0261] In summary, the present invention provides a package substrate structure and a preparation method thereof, the preparation method comprising the following steps: providing a core board layer; forming a multilayer substrate build-up layer covering two opposite sides of the core board layer and electrically connected to the core board layer; providing an interconnection structure layer, the interconnection structure layer comprising a bottom line layer, a bottom dielectric layer and an intermediate interconnection layer, the bottom dielectric layer covers the bottom line layer, and a blind hole exposing the bottom line layer is formed in the bottom dielectric layer, the intermediate interconnection layer is located on the bottom dielectric layer and is electrically connected to the bottom line layer through the blind hole; flip-chip pressing the interconnection structure layer on a preset area of ​​the substrate build-up layer to obtain the required substrate structure layer; forming a solder mask layer on two opposite sides of the substrate structure layer, and forming contact holes at preset positions of the solder mask layer, at least one contact hole exposing the conductive part of the interconnection structure layer. The present invention provides a package substrate structure and a preparation method thereof, by flip-chip pressing / embedding / burying the substrate-free interconnection structure layer into the multilayer substrate build-up layer, a finer circuit, thinner and higher circuit density packaging is achieved, while significantly reducing signal transmission loss. The interconnection structure layer of the present invention effectively replaces the traditional silicon-based intermediate layer, and has the advantages of simple preparation process, easy independent preparation, low production cost, etc., and can effectively avoid the warping problem. At the same time, the interconnection structure layer adopts a board-level preparation method, and can be directly cut into unit sizes after preparation. Compared with the wafer-level preparation of the silicon-based intermediate layer, it effectively improves the material utilization rate. In addition, the packaging substrate structure of the present invention has a high degree of design flexibility. By adjusting the thickness, number of layers and circuit design of each dielectric layer and each circuit layer, the thickness and circuit density of the interconnection structure layer can be accurately controlled to meet specific packaging requirements. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0262] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging substrate structure, characterized in that: The following steps are involved: A core board layer is provided, the core board layer includes a core board and a core board circuit layer, the core board includes a first surface and a second surface arranged opposite to each other, a plurality of core board through holes are formed in the core board, the plurality of core board through holes are arranged at intervals and penetrate the core board, the core board circuit layer includes a core board conductive circuit located on the first surface and the second surface of the core board and a core board conductive column filled in the core board through hole; A multi-layer substrate build-up layer is formed covering two opposite sides of the core layer and electrically connected to the core layer, wherein the substrate build-up layer includes a build-up dielectric layer and a build-up circuit layer, a build-up blind hole is formed in the build-up dielectric layer, and the build-up circuit layer includes a build-up conductive circuit located on the upper surface of the build-up dielectric layer and a build-up conductive column filled in the build-up blind hole; Providing an interconnection structure layer, the interconnection structure layer comprising a bottom wiring layer, a bottom dielectric layer and an intermediate interconnection layer, the bottom dielectric layer covers the bottom wiring layer, a blind hole is formed in the bottom dielectric layer to expose the bottom wiring layer, the intermediate interconnection layer is located on the bottom dielectric layer and is electrically connected to the bottom wiring layer through the blind hole; Flip-chip pressing the interconnection structure layer onto a preset area of ​​the substrate build-up layer on the second surface side of the core board to obtain a desired substrate structure layer; A solder resist layer is formed on two opposite sides of the substrate structure layer, and contact holes are formed at preset positions of the solder resist layer, wherein at least one of the contact holes exposes the conductive portion of the interconnection structure layer.

2. The method for preparing a packaging substrate structure according to claim 1, characterized in that: Forming a multi-layer substrate build-up layer covering two opposite sides of the core layer comprises the following steps: Forming a build-up dielectric layer on two opposite sides of the core layer, and patterning the build-up dielectric layer to form the build-up blind hole penetrating the build-up dielectric layer; forming a build-up conductive layer, wherein the build-up conductive layer covers the build-up dielectric layer and fills the build-up blind hole; Patterning the build-up conductive layer to obtain the build-up conductive circuit, and the portion of the build-up conductive layer filled into the build-up blind hole serves as the build-up conductive column; The steps of preparing the build-up dielectric layer and the build-up circuit layer are repeated until the required number of build-up layers of the substrate are completed.

3. The method for preparing a packaging substrate structure according to claim 1, characterized in that: After forming a multi-layer substrate build-up layer covering two opposite sides of the core layer, the following steps are also included: A groove is formed in the multi-layer substrate build-up layer on the second surface side of the core board, the groove opens from the top surface of the multi-layer substrate build-up layer and extends downward to a preset depth to expose the build-up circuit layer.

4. The method for preparing a packaging substrate structure according to claim 3, characterized in that: The interconnection structure layer is flip-chip pressed into the groove, and a surface of the interconnection structure layer away from the bottom surface of the groove is not lower than the top surface of the groove.

5. The method for preparing a packaging substrate structure according to claim 3, characterized in that: The interconnection structure layer is flip-chip pressed into the groove, and a surface of the interconnection structure layer away from the bottom surface of the groove is lower than the top surface of the groove.

6. The method for preparing a packaging substrate structure according to claim 5, characterized in that: Before forming the solder resist layer, the following steps are also included: forming a dielectric material layer, wherein the dielectric material layer is located on two opposite sides of the substrate structure layer, and the dielectric material layer fills the groove and covers the interconnection structure layer; Forming an opening in the dielectric material layer, wherein the opening exposes the bottom wiring layer in the interconnection structure layer and the build-up conductive wiring in the substrate structure layer; A conductive interconnection is formed, a portion of which fills the opening to be electrically connected to the bottom wiring layer and the build-up conductive wiring.

7. The method for preparing a package substrate structure according to claim 1, wherein: The intermediate interconnection layer includes multiple intermediate line layers and multiple intermediate dielectric layers, and the intermediate line layer includes intermediate conductive plugs and intermediate conductive lines connected in sequence from bottom to top, wherein the intermediate conductive plugs located at the bottom layer are filled in the blind holes, and the intermediate conductive lines located at the bottom layer are located on the bottom dielectric layer.

8. The method for preparing a packaging substrate structure according to claim 7, characterized in that: Forming the interconnect structure layer comprises the following steps: Providing a supporting substrate, and forming a separation layer on the supporting substrate; forming the bottom wiring layer; forming the bottom dielectric layer covering the bottom wiring layer, and forming the blind hole in the bottom dielectric layer; forming a first intermediate conductive layer, wherein the first intermediate conductive layer covers the bottom dielectric layer and fills the blind hole; Graphically processing the first intermediate conductive layer to obtain the bottom intermediate conductive line, and the portion of the first intermediate conductive layer filled into the blind hole serves as the bottom intermediate conductive plug; forming a first intermediate dielectric layer on the intermediate conductive circuit; Forming a blind hole in the first intermediate dielectric layer to expose the bottom intermediate conductive line; forming a second intermediate conductive layer, wherein the second intermediate conductive layer covers the first intermediate dielectric layer and fills the blind holes in the first intermediate dielectric layer; The second intermediate conductive layer is patterned to obtain a second intermediate conductive line, and a portion of the second intermediate conductive layer filled into the blind hole serves as a second intermediate conductive plug.

9. The method for preparing a packaging substrate structure according to claim 7, wherein: The method also includes forming a top dielectric layer on the topmost intermediate circuit layer by vacuum pressing.

10. The method for preparing a package substrate structure according to claim 1, wherein: Before lamination, the method further includes forming an adhesive film layer on the surface of the interconnection structure layer by using a vacuum lamination method.

11. The method for preparing a package substrate structure according to claim 1, wherein: The method further includes the step of forming a conductive connection portion, wherein the conductive connection portion is filled in the contact hole on the second surface side of the core board and extends to the surface of the solder resist layer.

12. A packaging substrate structure, characterized in that: include: A core plate layer, wherein the core plate layer comprises a core plate and a core plate circuit layer, wherein the core plate comprises a first surface and a second surface arranged opposite to each other, wherein a plurality of core plate through holes are arranged in the core plate, wherein the plurality of core plate through holes are arranged at intervals and penetrate the core plate, and wherein the core plate circuit layer comprises a core plate conductive circuit located on the first surface and the second surface of the core plate and a core plate conductive column filled in the core plate through hole; A multi-layer substrate build-up layer, covering two opposite sides of the core layer and electrically connected to the core layer, the substrate build-up layer includes a build-up dielectric layer and a build-up circuit layer, the build-up dielectric layer is provided with a build-up blind hole, the build-up circuit layer includes a build-up conductive circuit located on the upper surface of the build-up dielectric layer and a build-up conductive column filled in the build-up blind hole; An interconnection structure layer, the interconnection structure layer comprising a bottom wiring layer, a bottom dielectric layer and an intermediate interconnection layer, the bottom dielectric layer covers the bottom wiring layer, and the bottom dielectric layer is provided with a blind hole exposing the bottom wiring layer, the intermediate interconnection layer is located on the bottom dielectric layer and is electrically connected to the bottom wiring layer through the blind hole; The interconnection structure layer is flip-chip pressed onto a preset area of ​​the substrate build-up layer on the second surface side of the core board; The solder resist layer is located on two opposite sides of the substrate structure layer obtained by laminating the interconnect structure layer and the multiple substrate build-up layers. Contact holes are arranged at preset positions of the solder resist layer, and at least one of the contact holes exposes the conductive part of the interconnect structure layer.

13. The packaging substrate structure according to claim 12, characterized in that: It also includes a groove, which is located in the multi-layer substrate build-up layer on the second surface side of the core board. The groove opens from the top surface of the multi-layer substrate build-up layer and extends downward to a preset depth to expose the build-up layer circuit layer.

14. The packaging substrate structure according to claim 13, characterized in that: The interconnection structure layer is flip-chip pressed into the groove, and a surface of the interconnection structure layer away from the bottom surface of the groove is not lower than the top surface of the groove.

15. The packaging substrate structure according to claim 13, characterized in that: The interconnection structure layer is flip-chip pressed into the groove, and a surface of the interconnection structure layer away from the bottom surface of the groove is lower than the top surface of the groove.

16. The packaging substrate structure according to claim 12, characterized in that: A glue film layer is provided on the surface of the interconnection structure layer, and the interconnection structure layer is bonded to the substrate build-up layer through the glue film layer.

17. The packaging substrate structure according to claim 12, characterized in that: It also includes a conductive connecting portion, which is filled in the contact hole on the second surface side of the core board and extends to the surface of the solder resist layer.

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