Manufacturing method of semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure, relates to the technical field of semiconductors, and is used for solving the technical problem of relatively low yield. The manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises an array region and a peripheral region; forming a plurality of first active regions arranged at intervals in the array region and a first filling groove surrounding each first active region; forming a first isolation layer covering the side wall and the bottom wall of the first filling groove and the top surface of the first active region, and a first supporting layer filling the remaining first filling groove; removing the first isolation layer on the top surface of the first active region, and reserving the first isolation layer on the side wall and the bottom wall of the first filling groove; and forming a second isolation layer, wherein the second isolation layer covers the top surface of the first active region, the top surface of the remaining first isolation layer and the top surface of the first supporting layer. By removing the first isolation layer, the defects of the first isolation layer are eliminated, the second isolation layer is formed again, and the surface quality of the second isolation layer is relatively good, so that the yield of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] With the development of semiconductor technology, there are more and more types of semiconductor structures and their applications are becoming more and more extensive. The semiconductor structure includes a substrate, in which a plurality of active areas (AA) are formed at intervals. In order to isolate each active area, an isolation structure is also provided in the substrate, and the isolation material forming the isolation structure is filled between adjacent active areas and covers the top surface of the active area. However, during the manufacturing process of the isolation structure, the isolation material formed on the active area is prone to defects, which affects the quality of the subsequently formed word line (WL) and other structures, resulting in a low yield of the semiconductor structure. Summary of the invention

[0003] In view of the above problems, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure to reduce defects in the film layer on the first active region and improve the yield of the semiconductor structure.

[0004] According to some embodiments, the present disclosure provides a method for manufacturing a semiconductor structure, which includes:

[0005] Providing a substrate, the substrate comprising an array region and a peripheral region;

[0006] forming a plurality of first active regions spaced apart from each other in the array region, and a first filling groove surrounding each of the first active regions;

[0007] forming a first isolation layer and a first supporting layer, wherein the first isolation layer covers the sidewalls and the bottom wall of the first filling groove and the top surface of the first active area, and the first supporting layer fills the remaining first filling groove;

[0008] removing the first isolation layer on the top surface of the first active region and retaining the first isolation layer on the sidewalls and bottom wall of the first filling groove to expose the top surface of the first active region;

[0009] A second isolation layer is formed, wherein the second isolation layer covers a top surface of the first active region, a top surface of the remaining first isolation layer, and a top surface of the first supporting layer.

[0010] In some possible embodiments, before removing the first isolation layer located on the first active region, the method further includes:

[0011] forming a third isolation layer, wherein the third isolation layer covers a top surface of the first isolation layer and a top surface of the first supporting layer opposite to the array region;

[0012] Removing the first isolation layer located on the first active region includes:

[0013] The third isolation layer opposite to the array region and the first isolation layer on the first active region are removed by wet cleaning with a hydrofluoric acid solution to expose a top surface of the first active region and a top surface of the first supporting layer.

[0014] In some possible embodiments, forming the second isolation layer includes:

[0015] The second isolation layer is deposited on the first active region, the first isolation layer opposite to the array region and the first support layer, and the thickness of the second isolation layer is greater than or equal to the sum of the thickness of the first isolation layer and the third isolation layer.

[0016] In some possible embodiments, forming a plurality of first active regions spaced apart from each other in the array region, and a first filling groove surrounding each of the first active regions, comprises:

[0017] The first active area and the first filling groove are formed in the array area; wherein the extension direction of each of the first active areas is the same, and there is a first gap or a second gap between adjacent first active areas, the size of the first gap in the first direction is smaller than the size of the second gap in the first direction, and the first direction is perpendicular to the extension direction of the first active area.

[0018] In some possible embodiments, forming the first isolation layer and the first support layer includes:

[0019] forming the first isolation layer on the sidewalls and bottom wall of the first filling groove and the first active area, wherein the first isolation layer fills the first gap, and the first isolation layer located in the second gap encloses the filling hole;

[0020] Depositing an initial first supporting layer, wherein the initial first supporting layer completely fills the filling hole and covers a top surface of the first isolation layer;

[0021] A portion of the initial first supporting layer is removed, and the remaining initial first supporting layer forms the first supporting layer, wherein a top surface of the first supporting layer is aligned with a top surface of the first active region.

[0022] In some possible embodiments, a plurality of first active regions spaced apart from each other are formed in the array region, and a first filling groove surrounding each of the first active regions is formed, further comprising:

[0023] forming a plurality of second active regions spaced apart from each other in the peripheral region, and a second filling groove surrounding each of the second active regions;

[0024] Forming a first isolation layer and a first support layer, comprising:

[0025] The first isolation layer is formed on the sidewalls and bottom wall of the first filling groove, the top surface of the first active area, the sidewalls and bottom wall of the second filling groove, and the top surface of the second active area, and the first isolation layer located in the second filling groove encloses a third filling groove;

[0026] Depositing an initial first supporting layer on the first isolation layer, wherein the initial first supporting layer opposite to the array region fills up the remaining first filling groove and covers the top surface of the first isolation layer opposite to the array region; the initial first supporting layer opposite to the peripheral region covers the sidewall and bottom wall of the third filling groove and the top surface of the first isolation layer opposite to the peripheral region;

[0027] The initial first supporting layer is etched back to remove the initial first supporting layer on the first isolation layer opposite to the array region and the initial first supporting layer in the peripheral region, and the remaining initial first supporting layer forms the first supporting layer.

[0028] In some possible embodiments, before removing the first isolation layer located on the first active region, the method further includes:

[0029] forming a third isolation layer, wherein the third isolation layer covers a top surface of the first isolation layer and a top surface of the first support layer opposite to the array region, and covers the first isolation layer opposite to the peripheral region, and the third isolation layer located in the third filling groove encloses a fourth filling groove;

[0030] A second supporting layer and a filling layer are formed, wherein the second supporting layer covers the sidewalls and the bottom wall of the fourth filling groove, and the filling layer fills the remaining fourth filling groove.

[0031] In some possible embodiments, forming a second supporting layer and a filling layer includes:

[0032] Depositing the second supporting layer, wherein the second supporting layer covers the top surface of the third isolation layer opposite to the array region and the top surface of the third isolation layer opposite to the peripheral region, and covers the sidewall and bottom wall of the fourth filling groove, and the second supporting layer located in the fourth filling groove encloses a fifth filling groove;

[0033] forming the filling layer, wherein the filling layer covers the top surface of the second supporting layer opposite to the array region and the peripheral region, and fills the fifth filling groove;

[0034] performing a planarization process on the filling layer, removing the filling layer on the second supporting layer opposite to the array region and the peripheral region, and exposing the second supporting layer;

[0035] The second supporting layer opposite to the array region and the second supporting layer on the third isolation layer opposite to the peripheral region are removed by etching, and the remaining second supporting layer, the filling layer and the third isolation layer are aligned.

[0036] In some possible embodiments, after forming the second supporting layer and the filling layer, the method further includes:

[0037] Each of the first active regions is doped to form a first source region and a first drain region.

[0038] In some possible embodiments, removing the first isolation layer on the first active region includes:

[0039] Using hydrofluoric acid wet cleaning to remove the third isolation layer opposite to the array region, the first isolation layer on the first active region, the third isolation layer opposite to the peripheral region, and the first isolation layer, the second supporting layer and the filling layer on the second active region;

[0040] Forming the second isolation layer includes:

[0041] The second isolation layer is deposited, and the second isolation layer covers the top surface of the first active area, the top surfaces of the first isolation layer and the first supporting layer opposite to the array area, the top surface of the second active area, the top surface of the filling layer, and the top surfaces of the first isolation layer, the second supporting layer and the third isolation layer opposite to the peripheral area.

[0042] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure has at least the following advantages:

[0043] In the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, a first active area and a first filling groove surrounding each first active area are formed in an array area, and a first isolation layer is formed on the top surface of the first active area, the side wall and the bottom wall of the first filling groove, and a first support layer is formed in the remaining first filling groove. The first isolation layer on the top surface of the first active area is then removed, and the first isolation layer located on the side wall and the bottom wall of the first filling groove is retained to eliminate the convex point defects of the first isolation layer. After the second isolation layer is formed on the top surface of the first active area, the top surface of the remaining first isolation layer and the top surface of the first support layer, the top surface of the second isolation layer is relatively flat and has fewer defects, thereby improving the quality of the subsequently formed word lines, reducing word line interconnections, and improving the yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of defects in the first isolation layer in the related art;

[0045] Figure 2 A schematic diagram of defects of a mask layer in the related art;

[0046] Figure 3 is a schematic diagram of defects in the first active region in the related art;

[0047] Figure 4 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present disclosure;

[0048] Figure 5 is a schematic structural diagram of a substrate in an embodiment of the present disclosure;

[0049] Figure 6 A diagram of a manufacturing process of a semiconductor structure in an embodiment of the present disclosure;

[0050] Figure 7 is another manufacturing process diagram of a semiconductor structure in an embodiment of the present disclosure;

[0051] Figure 8 is a top view of a first active region in an embodiment of the present disclosure;

[0052] Fig. 9 is a schematic diagram of a filling hole in an embodiment of the present disclosure;

[0053] Fig.10 is a schematic diagram of an initial first isolation layer in an embodiment of the present disclosure;

[0054] Fig.11 Schematic diagram of the first isolation layer and the first support layer in one embodiment of the present disclosure

[0055] Fig.12 It is a schematic diagram after forming a first active region in one embodiment of the present disclosure;

[0056] Fig.13 is a schematic diagram after forming a second active region in one embodiment of the present disclosure;

[0057] Fig.14 It is a schematic diagram after forming a first isolation layer opposite to the array region in one embodiment of the present disclosure;

[0058] Fig.15 It is a schematic diagram after forming a first isolation layer opposite to the peripheral region in one embodiment of the present disclosure;

[0059] Fig.16 It is a schematic diagram after forming an initial first supporting layer relative to the array area in one embodiment of the present disclosure;

[0060] Fig.17 It is a schematic diagram after forming an initial first supporting layer relative to the peripheral region in one embodiment of the present disclosure;

[0061] Fig.18It is a schematic diagram after forming a first supporting layer opposite to the array region in one embodiment of the present disclosure;

[0062] Fig.19 It is a schematic diagram of removing the first supporting layer relative to the peripheral area in one embodiment of the present disclosure;

[0063] Fig. 20 It is a schematic diagram after forming a third isolation layer opposite to the array region in one embodiment of the present disclosure;

[0064] Fig.21 It is a schematic diagram after forming a third isolation layer opposite to the peripheral region in one embodiment of the present disclosure;

[0065] Fig. 22 It is a schematic diagram after forming a second supporting layer opposite to the array region in one embodiment of the present disclosure;

[0066] Fig.23 It is a schematic diagram after forming a second supporting layer opposite to the peripheral region in one embodiment of the present disclosure;

[0067] Fig.24 It is a schematic diagram after forming a filling layer opposite to the array area in one embodiment of the present disclosure;

[0068] Fig.25 It is a schematic diagram after forming a filling layer relative to the peripheral area in one embodiment of the present disclosure;

[0069] Fig.26 It is a schematic diagram after removing the filling layer relative to the array area in one embodiment of the present disclosure;

[0070] Fig. 27 It is a schematic diagram of removing the filling layer corresponding to the peripheral area in one embodiment of the present disclosure;

[0071] Fig.28 It is a schematic diagram of removing the second supporting layer opposite to the array area in one embodiment of the present disclosure;

[0072] Fig.29 It is a schematic diagram of removing the second supporting layer opposite to the peripheral area in one embodiment of the present disclosure;

[0073] Fig.30 It is a schematic diagram of removing the third isolation layer opposite to the array region in one embodiment of the present disclosure;

[0074] Fig.31 It is a schematic diagram of removing the third isolation layer opposite to the peripheral region in one embodiment of the present disclosure;

[0075] Fig.32 It is a schematic diagram after forming a second isolation layer opposite to the array region in one embodiment of the present disclosure;

[0076] Fig.33FIG. 1 is a schematic diagram of a second isolation layer formed opposite to the peripheral region in an embodiment of the present disclosure.

[0077] Description of reference numerals:

[0078] 10-substrate; 11-first active region;

[0079] 12-first filling groove; 13-second active area;

[0080] 14-second filling slot; 15-third filling slot;

[0081] 16- fourth filling slot; 17- fifth filling slot;

[0082] 18-first gap; 19-second gap;

[0083] 21-first isolation layer; 22-second isolation layer;

[0084] 23-third isolation layer; 24-filling hole;

[0085] 31-initial first supporting layer; 32-first supporting layer;

[0086] 33-second supporting layer; 34-filling layer;

[0087] 40-Mask layer. DETAILED DESCRIPTION

[0088] The related art has the problem of low yield of semiconductor structure. The inventor has found that: Figures 1 to 3 In the process of manufacturing the semiconductor structure, the first isolation layer 21 is first formed on the first active area 11. Then, a mask layer 40 is formed on the first isolation layer 21 and the first active area 11, and the first isolation layer 21 and the first active area 11 are etched using the mask layer 40 as a mask to form a word line groove. However, in the process before the first isolation layer 21 and the process of the first isolation layer 21, the first isolation layer 21 is prone to bump defects. The mask layer 40 is prone to breakpoints, which makes it easy for pits and broken lines to appear when etching the first active area 11. After the word line grooves are formed, the word line grooves are easily interconnected, so that the word lines are interconnected, which reduces the yield of the semiconductor structure.

[0089] The disclosed embodiment provides a method for manufacturing a semiconductor structure, by forming a first active area and a first filling groove surrounding each first active area in an array area, and forming a first isolation layer on the top surface of the first active area, the side wall and the bottom wall of the first filling groove, and a first support layer in the remaining first filling groove. Then, the first isolation layer on the top surface of the first active area is removed, and the first isolation layer located on the side wall and the bottom wall of the first filling groove is retained to eliminate the convex point defects of the first isolation layer. A second isolation layer is formed on the top surface of the first active area, the top surface of the remaining first isolation layer and the top surface of the first support layer. The top surface of the second isolation layer is relatively flat and has fewer defects, thereby improving the quality of the subsequently formed word lines, reducing word line interconnections, and improving the yield of the semiconductor structure.

[0090] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0091] See also Figure 4 The present disclosure provides a method for manufacturing a semiconductor structure, which comprises the following steps:

[0092] Step S100: providing a substrate, wherein the substrate comprises an array region and a peripheral region.

[0093] See also Figure 5 The substrate 10 may be a semiconductor substrate such as a silicon substrate, a germanium substrate, a gallium nitride substrate, a silicon-on-insulator substrate (SOI for short). The substrate 10 includes an array region and a peripheral region, the array region is adjacent to the peripheral region, the array region is used to form a storage cell (Cell), and the peripheral region is used to form a peripheral circuit, etc. The array region is as shown in FIG. Figure 5 As shown in A, the peripheral area is Figure 5 As shown in B.

[0094] Step S200: forming a plurality of first active regions spaced apart from each other in the array region, and forming a first filling trench surrounding each of the first active regions.

[0095] See also Figure 6 , a plurality of first active regions 11 and first filling grooves 12 are formed in the array region. The plurality of first active regions 11 are arranged at intervals, and the plurality of first active regions 11 can be arranged in an array. The first filling grooves 12 surround the first active regions 11 to isolate the first active regions 11. Figure 6 As shown, a plurality of first active regions 11 independent of each other are formed in the first filling trench 12 .

[0096] Step S300: forming a first isolation layer and a first supporting layer, wherein the first isolation layer covers the sidewalls and the bottom wall of the first filling groove and the top surface of the first active area, and the first supporting layer fills the remaining first filling groove.

[0097] Continue reading Figure 6 A first isolation layer 21 is formed on the sidewalls and bottom wall of the first filling groove 12 and the top surface of the first active area 11, and a first supporting layer 32 is formed on the first isolation layer 21. The first isolation layer 21 fills part of the first filling groove 12, and the first supporting layer 32 fills the remaining first filling groove 12. The material of the first isolation layer 21 can be an oxide, such as silicon oxide; the material of the first supporting layer 32 can be a nitride, such as silicon nitride.

[0098] The first isolation layer 21 and the first supporting layer 32 can both be formed by deposition, and the first isolation layer 21 covers the sidewalls and the bottom wall of the first filling groove 12, and covers the top surface of the first active area 11. The top surface of the first isolation layer 21 can be higher than the top surface of the first supporting layer 32, for example, the top surface of the first supporting layer 32 can be flush with the top surface of the first active area 11.

[0099] Step S400: removing the first isolation layer on the top surface of the first active region, and retaining the first isolation layer on the sidewalls and the bottom wall of the first filling groove to expose the top surface of the first active region.

[0100] Continue reading Figure 6 , remove the first isolation layer 21 on the top surface of the first active area 11 to expose the top surface of the first active area 11, for example, by wet cleaning with a hydrofluoric acid (DHF) solution. By removing the first isolation layer 21 on the top surface of the first active area 11, the bump defects of the first isolation layer 21 can be eliminated, thereby avoiding the subsequent formation of word lines, especially buried word lines (BWL), and the occurrence of interconnection problems.

[0101] like Figure 6 As shown, the first isolation layer 21 located on the sidewall and bottom wall of the first filling groove 12 is retained, that is, the first isolation layer 21 in contact with the first support layer 32 is retained. The top surface of the remaining first isolation layer 21, the top surface of the first active region 11 and the top surface of the first support layer 32 are flush, so that the top surfaces of the three form a relatively flat surface.

[0102] Step S500: forming a second isolation layer, wherein the second isolation layer covers a top surface of the first active region, a top surface of the remaining first isolation layer, and a top surface of the first supporting layer.

[0103] Continue reading Figure 6A second isolation layer 22 is formed (e.g., deposited) on the top surface of the first active area 11, the top surface of the remaining first isolation layer 21, and the top surface of the first support layer 32. The top surface of the second isolation layer 22 is relatively flat and has fewer defects, thereby improving the quality of subsequently formed word lines, reducing word line interconnections, and improving the yield of the semiconductor structure.

[0104] In some examples, the thickness of the second isolation layer 22 is greater than the thickness of the first isolation layer 21 to compensate for the removal of the first isolation layer 21. In this way, the thickness of the second isolation layer 22 on the first active area 11 is relatively large, which prevents the word line from being turned on and off due to the hot electron effect, that is, improves the gate control capability to ensure the performance of the semiconductor structure. The material of the second isolation layer 22 can be the same as that of the first isolation layer 21.

[0105] In summary, in the method for manufacturing the semiconductor structure in the embodiment of the present disclosure, a first active area 11 and a first filling groove 12 surrounding each first active area 11 are formed in the array area, and a first isolation layer 21 is formed on the top surface of the first active area 11, the sidewall and the bottom wall of the first filling groove 12, and a first support layer 32 is formed in the remaining first filling groove 12. The first isolation layer 21 on the top surface of the first active area 11 is then removed, and the first isolation layer 21 located on the sidewall and the bottom wall of the first filling groove 12 is retained to eliminate the convex point defects of the first isolation layer 21. A second isolation layer 22 is formed on the top surface of the first active area 11, the top surface of the remaining first isolation layer 21, and the top surface of the first support layer 32. The top surface of the second isolation layer 22 is relatively flat and has fewer defects, thereby improving the quality of the word lines formed subsequently, reducing word line interconnections, and improving the yield of the semiconductor structure.

[0106] For some possible examples, see Figure 7 Before removing the first isolation layer 21 located on the first active area 11 (step S400), the method further includes: forming a third isolation layer 23, the third isolation layer 23 covering the top surface of the first isolation layer 21 opposite to the array area and the top surface of the first support layer 32.

[0107] Accordingly, the first isolation layer 21 located on the first active area 11 is removed (step S400), including: using a hydrofluoric acid solution to wet clean and remove the third isolation layer 23 opposite to the array area and the first isolation layer 21 on the first active area 11 to expose the top surface of the first active area 11 and the top surface of the first supporting layer 32.

[0108] See also Figure 7A third isolation layer 23 is formed on the first isolation layer 21 and the first support layer 32 corresponding to the array region, and the third isolation layer 23 covers the top surface of the first isolation layer 21 and the top surface of the first support layer 32. The third isolation layer 23 is provided, and the first active region 11 has a stacked structure formed by the first isolation layer 21 and the third isolation layer 23, and the thickness is relatively large to ensure the performance of the first active region 11 in the subsequent manufacturing process.

[0109] Continue reading Figure 7 , using a hydrofluoric acid solution, the third isolation layer 23 opposite to the array area and the first isolation layer 21 on the first active area 11 are etched away, that is, the first isolation layer 21 and the third isolation layer 23 on the first active area 11 and the third isolation layer 23 on the first supporting layer 32 are wet etched away to expose the top surface of the first active area 11 and the top surface of the first supporting layer 32.

[0110] Based on the above example, a second isolation layer 22 is formed (step S500), including: depositing a second isolation layer 22 on the first active area 11, the first isolation layer 21 opposite to the array area, and the first support layer 32, wherein the thickness of the second isolation layer 22 is greater than or equal to the sum of the thicknesses of the first isolation layer 21 and the third isolation layer 23.

[0111] like Figure 7 As shown, the second isolation layer 22 covers the top surface of the first active area 11, the top surface of the first isolation layer 21 opposite to the array area, and the top surface of the first support layer 32 opposite to the array area. The thickness of the second isolation layer 22 is greater than or equal to the sum of the thicknesses of the first isolation layer 21 and the third isolation layer 23 to ensure that after the second isolation layer 22 is formed, the gate control capability of the array area is at least maintained or even improved.

[0112] The materials of the first isolation layer 21, the second isolation layer 22 and the third isolation layer 23 can be the same, for example, all oxides. On the one hand, it is convenient to clean and remove the third isolation layer 23 and part of the first isolation layer 21, and on the other hand, the insulation performance of the second isolation layer 22 is consistent with the insulation performance of the third isolation layer 23 and the first isolation layer 21, thereby ensuring the insulation effect.

[0113] For some possible examples, see Figure 8 , forming a plurality of first active areas 11 spaced apart in the array area, and a first filling groove 12 surrounding each first active area 11 (step S200), including: forming the first active area 11 and the first filling groove 12 in the array area, the extension direction of each first active area 11 is the same, there is a first gap 18 or a second gap 19 between adjacent first active areas 11, the size of the first gap 18 in the first direction is smaller than the size of the second gap 19 in the first direction, and the first direction is perpendicular to the extension direction of the first active area 11.

[0114] See also Figure 8 , the extension directions of the plurality of first active regions 11 are the same, for example, all along the second direction ( Figure 8 The extension direction of the first active region 11 is consistent with the extension direction of the subsequently formed bit line ( Figure 8 The Y direction shown in FIG. 1 crosses the direction of the word line to be formed subsequently ( Figure 8 The plurality of first active regions 11 are arranged in an array, the column direction is the extension direction of the bit line, that is, the bit line passes through a column of first active regions 11 and the first active regions 11 of two adjacent columns; the row direction is the extension direction of the first active regions 11.

[0115] like Figure 8 As shown, there is a first gap 18 or a second gap 19 between adjacent first active regions 11. The first gap 18 is as shown in FIG. Figure 8 The area enclosed by the middle dotted line, the second gap 19 is as follows Figure 8 In the area enclosed by the middle dot, the first gap 18 is connected to the second gap 19. The size of the first gap 18 in the first direction is smaller than the size of the second gap 19 in the first direction, that is, along the first direction, the size of the first gap 18 is smaller than the size of the second gap 19. Figure 8 The N direction shown in FIG. 1 is perpendicular to the extension direction of the first active region 11 .

[0116] It is understandable that the first gap 18 is Figure 6 and Figure 7 As shown at K in the middle, the second gap 19 is as shown in FIG. Figure 6 and Figure 7 As shown at L in the figure. Since the size of the first gap 18 along the first direction is smaller than the size of the second gap 19 along the first direction, the exposed area in the second gap 19 is larger, and during the etching process, the depth at the first gap 18 is smaller than the depth at the second gap 19.

[0117] In some possible implementations, forming the first active area 11 and the first filling groove 12 in the array area includes: etching the array area to form a plurality of initial active areas spaced apart, and initial filling grooves isolating the initial active areas; forming a compensation layer conformally covering the side walls and bottom walls of the initial filling grooves, and the top surface of the initial active areas, the remaining initial filling grooves forming the first filling grooves 12, and the initial active areas and the compensation layer forming the first active area 11.

[0118] The compensation layer does not fill the initial filling groove, and the shape of the formed first filling groove 12 is adapted to the shape of the initial filling groove. The compensation layer can avoid the consumption of the initial active area when the first isolation layer 21 is subsequently formed, so as to ensure the critical size of the first active area 11. The material of the compensation layer is the same as that of the array area, for example, the material of the array area is silicon, and the material of the compensation layer is polysilicon, so that the first active area 11 is an integrated structure to avoid delamination.

[0119] For some possible examples, see Figures 6 to 10 , forming a first isolation layer 21 and a first support layer 32 (step S300), comprising:

[0120] Step S301 : forming a first isolation layer 21 on the sidewalls and bottom wall of the first filling groove 12 and the first active area 11 , the first isolation layer 21 fills the first gap 18 , and the first isolation layer 21 in the second gap 19 encloses the filling hole 24 .

[0121] See also Fig. 9 , the first isolation layer 21 covers the sidewalls and bottom wall of the first filling groove 12, and the top surface of the first active area 11. The first isolation layer 21 fills the first gap 18, but does not fill the second gap 19. The first isolation layer 21 located in the second gap 19 encloses a plurality of filling holes 24. The plurality of filling holes 24 are arranged at intervals and separated by the first isolation layer 21. The thickness of the first isolation layer 21 is greater than half of the size of the first gap 18 along the first direction, and less than half of the size of the second gap 19 along the first direction.

[0122] The first isolation layer 21 can be formed by a deposition process. For example, the first isolation layer 21 is formed in sequence by furnace-tube atmospheric pressure chemical vapor deposition (APCVD), inductively coupled plasma chemical vapor deposition (ICPCVD), and furnace-tube atmospheric pressure chemical vapor deposition.

[0123] Step S302 : depositing an initial first supporting layer 31 , wherein the initial first supporting layer 31 completely fills the filling hole 24 and covers the top surface of the first isolation layer 21 .

[0124] See also Fig. 9 and Fig.10 The initial first supporting layer 31 is deposited in the filling hole 24 and on the top surface of the first isolation layer 21, and the initial first supporting layer 31 fills the filling hole 24. The first isolation layer 21 fills the first gap 18, and the initial first supporting layer 31 and the first isolation layer 21 fill the second gap 19.

[0125] Step S303 : removing a portion of the initial first supporting layer 31 , and forming the remaining initial first supporting layer 31 into a first supporting layer 32 , wherein the top surface of the first supporting layer 32 is aligned with the top surface of the first active region 11 .

[0126] See also Fig.10 and Fig.11, retain the initial first supporting layer 31 in the second gap 19, and remove the rest of the initial first supporting layer 31. The remaining initial first supporting layer 31 forms a first supporting layer 32, and the top surface of the first supporting layer 32 is aligned with the top surface of the first active area 11 and is lower than the top surface of the first isolation layer 21. The partial area between the adjacent first active areas 11 forms a stack of the first isolation layer 21, the first supporting layer 32 and the first isolation layer 21, so as to improve the isolation performance between the first active areas 11.

[0127] For some possible examples, see Fig.12 and Fig.13 , forming a plurality of first active regions 11 spaced apart in the array region, and a first filling groove 12 surrounding each first active region 11 (step S200), and further comprising: forming a plurality of second active regions 13 spaced apart in the peripheral region, and a second filling groove 14 surrounding each second active region 13. The plurality of first active regions 11, the plurality of second active regions 13, the first filling groove 12, and the second filling groove 14 can be formed simultaneously, reducing the manufacturing steps, for example, etching the array region and the peripheral region simultaneously.

[0128] Accordingly, see Figures 14 to 19 , forming a first isolation layer 21 and a first support layer 32 (step S300), comprising:

[0129] Step S301 ′: forming a first isolation layer 21 on the sidewalls and bottom wall of the first filling groove 12 , the top surface of the first active area 11 , the sidewalls and bottom wall of the second filling groove 14 , and the top surface of the second active area 13 ; the first isolation layer 21 in the second filling groove 14 encloses the third filling groove 15 .

[0130] See also Fig.14 and Fig.15 , depositing a first isolation layer 21, the first isolation layer 21 covers the sidewalls and bottom wall of the first filling groove 12, the top surface of the first active area 11, the sidewalls and bottom wall of the second filling groove 14, and the top surface of the second active area 13. The first isolation layer 21 does not completely fill the first filling groove 12, nor does it completely fill the second filling groove 14. For example, the first isolation layer 21 in the second filling groove 14 encloses the third filling groove 15.

[0131] Step S302': depositing an initial first supporting layer 31 on the first isolation layer 21, the initial first supporting layer 31 opposite to the array region fills the remaining first filling grooves 12 and covers the top surface of the first isolation layer 21 opposite to the array region; the initial first supporting layer 31 opposite to the peripheral region covers the side walls and bottom walls of the third filling grooves 15, and the top surface of the first isolation layer 21 opposite to the peripheral region.

[0132] See also Fig.16 and Fig.17, depositing an initial first supporting layer 31, the initial first supporting layer 31 covers the top surface of the first isolation layer 21, fills the remaining first filling grooves 12, and conformally covers the second filling grooves 14. The initial first supporting layer 31 opposite to the array region fills the remaining first filling grooves 12 and covers the first isolation layer 21 above the first active region 11. The initial first supporting layer 31 opposite to the peripheral region covers the sidewalls and bottom wall of the third filling groove 15, and the first isolation layer 21 above the second active region 13, and the initial first supporting layer 31 opposite to the peripheral region does not fill the third filling groove 15.

[0133] Step S303 ′: etching back the initial first supporting layer 31 to remove the initial first supporting layer 31 on the first isolation layer 21 opposite to the array region and the initial first supporting layer 31 in the peripheral region, and the remaining initial first supporting layer 31 forms the first supporting layer 32 .

[0134] See also Fig.18 and Fig.19 , the initial first supporting layer 31 is etched back, the initial first supporting layer 31 in the first filling groove 12 is retained, and the remaining initial first supporting layer 31 opposite to the array area and the entire initial first supporting layer 31 opposite to the peripheral area are removed. The retained initial first supporting layer 31 forms the first supporting layer 32.

[0135] In order to ensure the gate control capability of the peripheral region and the performance of the second active region 13, in some examples, refer to Figure 20 to Figure 24 , before removing the first isolation layer 21 located on the first active region 11 (step S400), the method further includes:

[0136] A third isolation layer 23 is formed, and the third isolation layer 23 covers the top surface of the first isolation layer 21 and the top surface of the first supporting layer 32 opposite to the array area, and covers the first isolation layer 21 opposite to the peripheral area. The third isolation layer 23 located in the third filling groove 15 encloses the fourth filling groove 16; a second supporting layer 33 and a filling layer 34 are formed, and the second supporting layer 33 covers the side wall and the bottom wall of the fourth filling groove 16, and the filling layer 34 fills the remaining fourth filling groove 16.

[0137] The first isolation layer 21 relative to the array region is the first isolation layer 21 above the first active region 11, and the first isolation layer 21 on the sidewall and bottom wall of the first filling groove 12. The first isolation layer 21 relative to the peripheral region includes the first isolation layer 21 above the second active region 13, and the first isolation layer 21 on the sidewall and bottom wall of the second filling groove 14.

[0138] See also Fig. 20 and Fig.21, the third isolation layer 23 does not fill the third filling groove 15, and the third isolation layer 23 located in the third filling groove 15 encloses the fourth filling groove 16. By providing the third isolation layer 23, the thickness of the film layer above the first active area 11 and the thickness of the film layer above the second active area 13 are increased to ensure that the first active area 11 and the second active area 13 maintain their performance in the subsequent manufacturing process, and ensure the gate control capability of the array area and the peripheral area.

[0139] See also Figure 21 to Figure 24 A second supporting layer 33 is formed on the sidewall and bottom wall of the fourth filling groove 16. The second supporting layer 33 conformally covers the sidewall and bottom wall of the fourth filling groove 16, but does not fill the fourth filling groove 16. A filling layer 34 is formed in the remaining fourth filling groove 16. The filling layer 34 fills the remaining fourth filling groove 16, that is, the second supporting layer 33 and the filling layer 34 fill the fourth filling groove 16 together. The top surface of the second supporting layer 33 and the top surface of the filling layer 34 are flush with the top surface of the third isolation layer 23. The material of the second supporting layer 33 may include nitride, and the material of the filling layer 34 includes spin-on dielectrics (SOD) to facilitate filling of larger grooves.

[0140] For some possible implementations, see Figure 21 to Figure 29 , forming a second supporting layer 33 and a filling layer 34, including:

[0141] Step a: deposit a second supporting layer 33, the second supporting layer 33 covers the top surface of the third isolation layer 23 opposite to the array area and the top surface of the third isolation layer 23 opposite to the peripheral area, and covers the side wall and bottom wall of the fourth filling groove 16, and the second supporting layer 33 located in the fourth filling groove 16 encloses the fifth filling groove 17.

[0142] See also Fig.21 and Fig.23 , a second supporting layer 33 is deposited on the third isolation layer 23 opposite to the array region and the third isolation layer 23 opposite to the peripheral region, the second supporting layer 33 covers the third isolation layer 23 opposite to the array region and the third isolation layer 23 opposite to the peripheral region, and conformally covers the sidewalls and bottom walls of the fourth filling groove 16. The second supporting layer 33 does not fill the fourth filling groove 16, and the second supporting layer 33 located in the fourth filling groove 16 encloses the fifth filling groove 17. The material of the second supporting layer 33 can be nitride.

[0143] Step b: forming a filling layer 34, the filling layer 34 covers the top surface of the second supporting layer 33 opposite to the array region and the peripheral region, and fills the fifth filling groove.

[0144] See also Fig.24 and Fig.25A filling layer 34 is spin-coated on the second supporting layer 33 opposite to the array region and the second supporting layer 33 opposite to the peripheral region, and the filling layer 34 covers the second supporting layer 33 opposite to the array region and the second supporting layer 33 opposite to the peripheral region and fills the fifth filling groove 17 .

[0145] Step c: performing a planarization process on the filling layer 34 , removing the filling layer 34 on the second supporting layer 33 opposite to the array region and the peripheral region, and exposing the second supporting layer 33 .

[0146] See also Fig.26 and Fig. 27 , chemical mechanical polishing is used to remove part of the filling layer 34 until the second supporting layer 33 opposite to the array region and the second supporting layer 33 opposite to the peripheral region are exposed. That is, the second supporting layer 33 opposite to the array region is completely removed, and the second supporting layer 33 opposite to the peripheral region retains part of the second supporting layer 33 located in the fifth filling groove 17, so as to form an isolation structure of the second active region 13, and ensure that the second active regions 13 are insulated and isolated from each other.

[0147] Step d: etching and removing the second supporting layer 33 opposite to the array region and the second supporting layer 33 on the third isolation layer 23 opposite to the peripheral region, and aligning the remaining second supporting layer 33, the filling layer 34 and the third isolation layer 23.

[0148] See also Fig.28 and Fig.29 , the entire second support layer 33 opposite to the array region is etched away to expose the third isolation layer 23 opposite to the array region, and the second support layer 33 on the third isolation layer 23 opposite to the peripheral region is etched away to expose the third isolation layer 23 opposite to the peripheral region, and the second support layer 33 in the fourth filling groove 16 is retained. The remaining second support layer 33, the filling layer 34 and the third isolation layer 23 are aligned to form a relatively flat surface on the peripheral region.

[0149] In some possible examples, after forming the second support layer 33 and the filling layer 34, the process further includes: doping each first active region 11 to form a first source region and a first drain region. For example, each first active region 11 is doped by ion implantation or other processes to form a first source region and a first drain region. While doping each first active region 11, each second active region 13 may also be doped to form a second source region and a second drain region.

[0150] For some examples, see Figure 28 to Figure 31 , removing the first isolation layer 21 on the first active area 11 (step S400), including: using hydrofluoric acid wet cleaning to remove the third isolation layer 23 opposite to the array area, the first isolation layer 21 on the first active area 11, the third isolation layer 23 opposite to the peripheral area, and the first isolation layer 21 on the second active area 13, the second supporting layer 33 and the filling layer 34.

[0151] Accordingly, see Fig.32 and Fig.33 , forming a second isolation layer 22 (step S500), including: depositing the second isolation layer 22, the second isolation layer 22 covers the top surface of the first active area 11, the top surfaces of the first isolation layer 21 and the first support layer 32 opposite to the array area, the top surface of the second active area 13, the top surface of the filling layer 34, and the top surfaces of the first isolation layer 21, the second support layer 33 and the third isolation layer 23 opposite to the peripheral area.

[0152] The third isolation layer 23 opposite to the array region and the third isolation layer 23 opposite to the peripheral region are removed by hydrofluoric acid etching, and the first isolation layer 21 on the first active region 11 and the second active region 13 is removed by etching, the top surface of the first active region 11 is exposed, and the first isolation layer 21 and the first support layer 32 between the first active regions 11 are retained. The second support layer 33 and the filling layer 34 on the second active region 13 are also removed by etching, and the second support layer 33 and the filling layer 34 between the second active regions 13 are retained.

[0153] The second isolation layer 22 is deposited on the top surface of the first active area 11, the top surfaces of the first isolation layer 21 and the first support layer 32 opposite to the array area, the top surface of the second active area 13, the top surface of the filling layer 34, and the top surfaces of the first isolation layer 21, the second support layer 33 and the third isolation layer 23 opposite to the peripheral area. The top surface of the formed second isolation layer 22 is higher than the top surface of the first active area 11, the top surfaces of the first isolation layer 21 and the first support layer 32, the top surface of the second active area 13 and the top surface of the filling layer 34. By removing at least the first isolation layer 21 on the first active area 11 and the second active area 13, and re-forming the second isolation layer 22 on the first active area 11 and the second active area 13, the convex point defects generated in the first isolation layer 21 during the process of forming the first isolation layer 21, forming the first support layer 32, and removing part of the first support layer 32 can be eliminated. That is, when the first isolation layer 21 is removed, the bump defects of the first isolation layer 21 are also removed, and the top surface of the formed second isolation layer 22 is relatively flat, so as to ensure the quality of other structures, especially the continuity of the word line.

[0154] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array region and a peripheral region; forming a plurality of first active regions spaced apart from each other in the array region, and a first filling groove surrounding each of the first active regions; forming a first isolation layer and a first supporting layer, wherein the first isolation layer covers the sidewalls and the bottom wall of the first filling groove and the top surface of the first active area, and the first supporting layer fills the remaining first filling groove; removing the first isolation layer on the top surface of the first active region and retaining the first isolation layer on the sidewalls and bottom wall of the first filling groove to expose the top surface of the first active region; A second isolation layer is formed, wherein the second isolation layer covers a top surface of the first active region, a top surface of the remaining first isolation layer, and a top surface of the first supporting layer.

2. The method according to claim 1, characterized in that: Before removing the first isolation layer located on the first active region, the method further includes: forming a third isolation layer, wherein the third isolation layer covers a top surface of the first isolation layer and a top surface of the first supporting layer opposite to the array region; Removing the first isolation layer located on the first active region includes: The third isolation layer opposite to the array region and the first isolation layer on the first active region are removed by wet cleaning with a hydrofluoric acid solution to expose a top surface of the first active region and a top surface of the first supporting layer.

3. The method according to claim 2, characterized in that: Forming a second isolation layer, comprising: The second isolation layer is deposited on the first active region, the first isolation layer opposite to the array region and the first support layer, and the thickness of the second isolation layer is greater than or equal to the sum of the thickness of the first isolation layer and the third isolation layer.

4. The production method according to any one of claims 1 to 3, characterized in that: A plurality of first active regions spaced apart from each other are formed in the array region, and a first filling groove surrounding each of the first active regions is formed, comprising: The first active area and the first filling groove are formed in the array area; wherein the extension direction of each of the first active areas is the same, and there is a first gap or a second gap between adjacent first active areas, the size of the first gap in the first direction is smaller than the size of the second gap in the first direction, and the first direction is perpendicular to the extension direction of the first active area.

5. The method according to claim 4, characterized in that: The first isolation layer and the first support layer are formed, comprising: forming the first isolation layer on the sidewalls and bottom wall of the first filling groove and the first active area, wherein the first isolation layer fills the first gap, and the first isolation layer located in the second gap encloses the filling hole; Depositing an initial first supporting layer, wherein the initial first supporting layer completely fills the filling hole and covers a top surface of the first isolation layer; A portion of the initial first supporting layer is removed, and the remaining initial first supporting layer forms the first supporting layer, wherein a top surface of the first supporting layer is aligned with a top surface of the first active region.

6. The method according to claim 1, characterized in that: A plurality of first active regions are formed in the array region and a first filling groove surrounds each of the first active regions, and further comprises: forming a plurality of second active regions spaced apart from each other in the peripheral region, and a second filling groove surrounding each of the second active regions; Forming a first isolation layer and a first support layer, comprising: The first isolation layer is formed on the sidewalls and bottom wall of the first filling groove, the top surface of the first active area, the sidewalls and bottom wall of the second filling groove, and the top surface of the second active area, and the first isolation layer located in the second filling groove encloses a third filling groove; Depositing an initial first supporting layer on the first isolation layer, wherein the initial first supporting layer opposite to the array region fills up the remaining first filling groove and covers the top surface of the first isolation layer opposite to the array region; the initial first supporting layer opposite to the peripheral region covers the sidewall and bottom wall of the third filling groove and the top surface of the first isolation layer opposite to the peripheral region; The initial first supporting layer is etched back to remove the initial first supporting layer on the first isolation layer opposite to the array region and the initial first supporting layer in the peripheral region, and the remaining initial first supporting layer forms the first supporting layer.

7. The manufacturing method according to claim 6, characterized in that: Before removing the first isolation layer located on the first active region, the method further includes: forming a third isolation layer, wherein the third isolation layer covers a top surface of the first isolation layer and a top surface of the first support layer opposite to the array region, and covers the first isolation layer opposite to the peripheral region, and the third isolation layer located in the third filling groove encloses a fourth filling groove; A second supporting layer and a filling layer are formed, wherein the second supporting layer covers the sidewalls and the bottom wall of the fourth filling groove, and the filling layer fills the remaining fourth filling groove.

8. The method according to claim 7, characterized in that: Forming a second supporting layer and a filling layer, comprising: Depositing the second supporting layer, wherein the second supporting layer covers the top surface of the third isolation layer opposite to the array region and the top surface of the third isolation layer opposite to the peripheral region, and covers the sidewall and bottom wall of the fourth filling groove, and the second supporting layer located in the fourth filling groove encloses a fifth filling groove; forming the filling layer, wherein the filling layer covers the top surface of the second supporting layer opposite to the array region and the peripheral region, and fills the fifth filling groove; performing a planarization process on the filling layer, removing the filling layer on the second supporting layer opposite to the array region and the peripheral region, and exposing the second supporting layer; The second supporting layer opposite to the array region and the second supporting layer on the third isolation layer opposite to the peripheral region are removed by etching, and the remaining second supporting layer, the filling layer and the third isolation layer are aligned.

9. The manufacturing method according to claim 8, characterized in that: After forming the second supporting layer and the filling layer, the method further includes: Each of the first active regions is doped to form a first source region and a first drain region.

10. The production method according to any one of claims 7 to 9, characterized in that: Removing the first isolation layer on the first active region includes: Using hydrofluoric acid wet cleaning to remove the third isolation layer opposite to the array region, the first isolation layer on the first active region, the third isolation layer opposite to the peripheral region, and the first isolation layer, the second supporting layer and the filling layer on the second active region; The second isolation layer is formed, comprising: The second isolation layer is deposited, and the second isolation layer covers the top surface of the first active area, the top surfaces of the first isolation layer and the first supporting layer opposite to the array area, the top surface of the second active area, the top surface of the filling layer, and the top surfaces of the first isolation layer, the second supporting layer and the third isolation layer opposite to the peripheral area.

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