Wafer-scale system-in-package structure and forming method thereof

Abstract

The invention discloses a wafer-scale system-in-package structure and a forming method thereof. The wafer-scale system-in-package structure comprises a silicon substrate; the plurality of functional sub-modules are attached to the upper surface of the silicon substrate and are arranged in an array; the warping and stress adjusting structure is attached to the upper surface of the silicon substrate at the edge of the functional sub-module; the stress buffering flexible part structure is attached to the upper surface of the silicon substrate of the functional sub-module corner head; the edge false devices are attached to the upper surface of the edge area of the silicon substrate outside the functional sub-module array and are different in size; and the plastic packaging layer is positioned on the upper surface of the silicon substrate and wraps the functional sub-module, the warping and stress adjusting structure, the stress buffering flexible part structure and the edge false device. And the warping of the system packaging structure of the wafer-level super-large core particle module at room temperature or high temperature can be effectively regulated and controlled. According to the method, support of national key research and development plan projects (the project number is 2023YFB4404300, and the project number is 2023YFB4404305) is obtained.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a wafer-scale system-level packaging structure and a method for forming the same. Background Art

[0002] System in Package (SiP) integrates chips with various functions such as optoelectronics, digital / logic, radio frequency, storage, etc. into a package in the form of chip stacking or package stacking, thereby realizing a system that can realize the above multiple functions.

[0003] The demand for data computing in today's emerging fields (mobile devices, artificial intelligence, automotive electronics, data storage, etc.) is growing exponentially. In order to meet the needs of high-performance computing such as high density, high speed, high heat dissipation, low power consumption, and low latency, the existing system-level packaging is expanding towards wafer scale, that is, integrating multiple semiconductor chips with different functions on a silicon wafer to form a wafer-scale system-level packaging structure.

[0004] Correspondingly, as the chip modules of the existing wafer-scale system-level packaging structure are upgraded to ultra-large-sized (greater than or equal to 300 mm) chip modules, the warpage control of the wafer-scale system-level packaging structure has become an increasingly difficult challenge. Summary of the invention

[0005] The problem to be solved by the present application is to provide a wafer-scale system-level packaging structure and a method for forming the same, so as to prevent the wafer-scale system-level packaging structure from warping, thereby effectively regulating the warping of the system packaging structure of the wafer-level super-large core module at room temperature or high temperature.

[0006] This application belongs to the National Key R&D Program (Project No.: 2023YFB4404300, Subject No.: 2023YFB4404305). To solve the above problems, this application first provides a wafer-scale system-level packaging structure, including: a silicon substrate comprising an upper surface and a lower surface opposite to each other; A plurality of functional submodules arranged in an array and mounted on the upper surface of the silicon substrate, the plurality of functional submodules being electrically connected to the silicon substrate, and each of the functional submodules comprising four corners and edges between adjacent corners; a warping and stress regulating structure mounted on the upper surface of the silicon substrate at the edge of the functional submodule; A stress buffering flexible component structure mounted on the upper surface of the silicon substrate of the functional submodule corner head; Edge dummy devices of different sizes mounted on the upper surface of the edge region of the silicon substrate outside the functional submodule array; A plastic encapsulation layer is located on the upper surface of the silicon substrate and covers the functional sub-module, the warping and stress adjustment structure, the stress buffer flexible component structure and the edge dummy device, and the plastic encapsulation layer exposes the upper surface of the functional sub-module, the warping and stress adjustment structure, the stress buffer flexible component structure and the edge dummy device.

[0007] In an optional embodiment, the warping and stress adjustment structure includes a flexible layer and a rigid layer located on an upper surface of the flexible layer, and the rigidity of the flexible layer is less than the rigidity of the rigid layer.

[0008] In an optional embodiment, the material of the rigid layer of the warping and stress regulation structure is silicon, silicon germanium or silicon carbide, and the material of the flexible layer is one or more of filler and / or fiber-filled polymer composite materials.

[0009] In an optional embodiment, the warping and stress regulation structure is mounted on the upper surface of the silicon substrate, including: the warping and stress regulation structure is directly mounted on the upper surface of the silicon substrate, or the warping and stress regulation structure is suspended and mounted on the upper surface of the silicon substrate.

[0010] In an optional embodiment, the warping and stress adjustment structure is one or more of a flip chip, a surface mount device, a functional device, a structural dummy sheet, and a heat dissipation dummy sheet.

[0011] In an optional embodiment, the number of warping and stress adjustment structures mounted on the surface of the silicon substrate at each edge of the functional submodule is at least two, and the plurality of warping and stress adjustment structures are arranged in a direction parallel to the edge of the functional submodule.

[0012] In an optional embodiment, the silicon substrate includes a middle area and an edge area surrounding the middle area, and several functional sub-modules are mounted on the upper surface of the middle area of ​​the silicon substrate; and several dummy devices are mounted on the upper surface of the edge area of ​​the silicon substrate.

[0013] In an optional embodiment, the edge dummy component is one or more of a passive component, a heat dissipation discrete component or a dummy piece.

[0014] In an optional embodiment, a size of the edge dummy device away from the middle area is smaller than a size of the edge dummy device close to the middle area.

[0015] In an optional embodiment, the silicon substrate in the edge region further has a groove, the groove may penetrate through the silicon substrate or not, and the plastic sealing layer further fills the groove.

[0016] In an optional embodiment, it also includes: a heat dissipation cover mounted on the upper surfaces of the plastic encapsulation layer, the functional sub-module, the warping and stress adjustment structure and the stress buffer flexible component structure, and the outer side surfaces of the plastic encapsulation layer and the silicon substrate, the heat dissipation cover includes a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top, the lower surface of the horizontal cover top is horizontal or has an optional downward protrusion in the corresponding area of ​​the functional sub-module, the warping and stress adjustment structure and the stress buffer flexible component structure, the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surfaces of the plastic encapsulation layer, the functional sub-module, the warping and stress adjustment structure and the stress buffer flexible component structure, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surface of the plastic encapsulation layer and the silicon substrate.

[0017] In an optional embodiment, the stress buffering flexible member structure is a flexible structure, and the rigidity of the stress buffering flexible member structure is less than the rigidity of the plastic packaging layer.

[0018] In an optional embodiment, the stress buffer flexible part structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, the second buffer layer and the core layer have blind holes penetrating the second buffer layer and the core layer, and the plastic encapsulation layer exposes the blind holes.

[0019] In an optional embodiment, the lower surface of the horizontal cover top of the heat dissipation cover has a plurality of anchoring protrusions protruding downward, and the anchoring protrusions are mounted in corresponding blind holes by adhesive.

[0020] In an optional embodiment, the stress buffer flexible part structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, the core layer has a blind hole, and a portion of the lower surface of the horizontal cover top of the heat dissipation cover is attached to the upper surface of the second buffer layer by an adhesive.

[0021] In an optional embodiment, the blind hole is a cavity, or the blind hole is filled with a filling material.

[0022] In an optional embodiment, the side wall surface of the blind hole also has a metal layer.

[0023] In an optional embodiment, it also includes: a reinforcing frame mounted on the lower surface of the silicon substrate, and the upper surface of the edge area of ​​the reinforcing frame is mounted together with the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side of the silicon substrate.

[0024] In an optional embodiment, the silicon substrate includes a silicon wafer body, a first redistribution layer located on the upper surface of the silicon wafer body, and a second redistribution layer located on the lower surface of the silicon wafer body, and the reinforcement frame has a plurality of holes, and the holes expose a portion of the second redistribution layer.

[0025] In an optional embodiment, the upper surface of the edge area of ​​the reinforcing frame has a protruding structure, and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate has a groove structure. When the upper surface of the edge area of ​​the reinforcing frame and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate are mounted together, the protruding structure on the upper surface of the edge area of ​​the reinforcing frame is mounted in the corresponding groove structure on the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate by adhesive.

[0026] In an optional embodiment, the upper surface of the edge area of ​​the reinforcing frame has a groove structure, and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate has a convex structure. When the upper surface of the edge area of ​​the reinforcing frame and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate are mounted together, the convex structure on the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate is mounted in the corresponding groove structure on the upper surface of the edge area of ​​the reinforcing frame by adhesive.

[0027] In an optional embodiment, each of the functional sub-modules has the same structure, and the functional sub-modules include at least two semiconductor chips, which are mounted on the upper surface of the silicon substrate in a flip-chip manner; each functional sub-module also includes a bottom filling layer filled between the lower surface of the semiconductor chip in each functional sub-module and the upper surface of the silicon substrate and covering the side surfaces of the semiconductor chip.

[0028] In an optional embodiment, the diagonal dimension of the silicon substrate is 300 or 450±10 mm, or the diameter of the silicon substrate is 300 mm or 450±5 mm.

[0029] The present application also provides a method for forming a wafer-scale system-level packaging structure, comprising: providing a silicon substrate, wherein the silicon substrate comprises an upper surface and a lower surface opposite to each other; Mounting a plurality of functional submodules arranged in an array on the surface of the silicon substrate, the plurality of functional submodules being electrically connected to the silicon substrate, and each of the functional submodules comprising four corners and edges between adjacent corners; Mounting a warpage and stress adjustment structure on the silicon substrate at the edge of the functional submodule; Mounting a stress buffering flexible component structure on the surface of the silicon substrate of the corner head of the functional submodule; Mounting dummy edge devices of different sizes on the surface of the edge area of ​​the silicon substrate outside the functional submodule array; A plastic encapsulation layer covering the functional sub-module, the warping and stress regulating structure, the stress buffering flexible component structure and the edge dummy device is formed on the upper surface of the silicon substrate, and the plastic encapsulation layer exposes the upper surface of the functional sub-module, the warping and stress regulating structure, the stress buffering flexible component structure and the edge dummy device.

[0030] In an optional embodiment, the warping and stress adjustment structure includes a flexible layer and a rigid layer located on an upper surface of the flexible layer, and the rigidity of the flexible layer is less than the rigidity of the rigid layer.

[0031] In an optional embodiment, mounting the warp and stress regulation structure on the upper surface of the silicon substrate includes: mounting the warp and stress regulation structure on the upper surface of the silicon substrate in direct contact, or mounting the warp and stress regulation structure in suspension on the upper surface of the silicon substrate.

[0032] In an optional embodiment, the warping and stress adjustment structure is one or more of a flip chip, a surface mount device, a functional device, a structural dummy sheet, and a heat dissipation dummy sheet.

[0033] In an optional embodiment, the silicon substrate includes a middle area and an edge area surrounding the middle area, and several functional sub-modules are mounted on the upper surface of the middle area of ​​the silicon substrate; and several dummy devices are mounted on the upper surface of the edge area of ​​the silicon substrate.

[0034] In an optional embodiment, a groove is formed in the silicon substrate in the edge region, and the groove passes through or does not pass through the silicon substrate; when the plastic encapsulation layer is formed, the plastic encapsulation layer also fills the groove.

[0035] In an optional embodiment, it also includes: a heat dissipation cover is mounted on the upper surfaces of the plastic encapsulation layer, the functional sub-module, the warping and stress adjustment structure and the stress buffer flexible component structure, and the outer side surfaces of the plastic encapsulation layer and the silicon substrate, the heat dissipation cover includes a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top, the lower surface of the horizontal cover top is horizontal or has an optional downward protrusion in the corresponding area of ​​the functional sub-module, the warping and stress adjustment structure and the stress buffer flexible component structure, the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surfaces of the plastic encapsulation layer, the functional sub-module, the warping and stress adjustment structure and the stress buffer flexible component structure, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surface of the plastic encapsulation layer and the silicon substrate.

[0036] In an optional embodiment, the stress buffer flexible part structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, the second buffer layer and the core layer have blind holes penetrating the second buffer layer and the core layer, and the plastic encapsulation layer exposes the blind holes.

[0037] In an optional embodiment, the lower surface of the horizontal cover top of the heat dissipation cover has a plurality of raised anchoring protrusions, and when the heat dissipation cover is mounted, the anchoring protrusions are mounted in corresponding blind holes by adhesive.

[0038] In an optional embodiment, the stress buffer flexible part structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, the core layer has a blind hole, and when the heat dissipation cover is mounted, a portion of the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surface of the second buffer layer by an adhesive.

[0039] In an optional embodiment, the method further includes: mounting a reinforcement frame on the lower surface of the silicon substrate, and mounting an upper surface of an edge region of the reinforcement frame and a bottom surface of a cover edge of a heat dissipation cover on the outer side of the silicon substrate together.

[0040] In an optional embodiment, the silicon substrate includes a silicon wafer body, a first redistribution layer located on the upper surface of the silicon wafer body, and a second redistribution layer located on the lower surface of the silicon wafer body, and the reinforcement frame has a plurality of holes, and when the reinforcement frame is mounted, the holes expose a portion of the second redistribution layer.

[0041] In an optional embodiment, the upper surface of the edge area of ​​the reinforcing frame has a protruding structure, and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate has a groove structure. When the upper surface of the edge area of ​​the reinforcing frame and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate are mounted together, the protruding structure on the upper surface of the edge area of ​​the reinforcing frame is mounted in the corresponding groove structure on the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate by adhesive.

[0042] In an optional embodiment, the upper surface of the edge area of ​​the reinforcing frame has a groove structure, and the bottom lower surface of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate has a convex structure. When the upper surface of the edge area of ​​the reinforcing frame and the bottom lower surface of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate are mounted together, the convex structure on the bottom lower surface of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate is mounted in the corresponding groove structure on the upper surface of the edge area of ​​the reinforcing frame by adhesive.

[0043] The flexible layer and the rigid layer located on the upper surface of the flexible layer are the outer side of the silicon substrate. The outer side of the silicon substrate. The outer side of the silicon substrate. The outer side of the silicon substrate. The outer side of the silicon substrate. The outer side of the silicon substrate. The outer side of the silicon substrate. The outer side of the silicon substrate. The flexible layer and the rigid layer located on the upper surface of the flexible layer are the outer side of the silicon substrate.

[0044] The advantages of the technical solution of this application are: The wafer-scale system-level packaging structure and its forming method in the aforementioned embodiment of the present application, the packaging structure includes a silicon substrate; a plurality of functional sub-modules arranged in an array mounted on the upper surface of the silicon substrate, the plurality of functional sub-modules are electrically connected to the silicon substrate, and each of the functional sub-modules includes four corners and edges located between adjacent corners; a warping and stress adjustment structure mounted on the upper surface of the silicon substrate at the edge of the functional sub-module; a stress buffering flexible component structure mounted on the upper surface of the silicon substrate at the corner of the functional sub-module; edge dummy devices of different sizes mounted on the upper surface of the edge area of ​​the silicon substrate outside the functional sub-module array; a plastic sealing layer located on the upper surface of the silicon substrate covering the functional sub-module, the warping and stress adjustment structure, the stress buffering flexible component structure and the edge dummy device, the plastic sealing layer exposing the upper surface of the functional sub-module, the warping and stress adjustment structure, the stress buffering flexible component structure and the edge chip. The warping and stress adjustment structure is used to increase the Si / EMC ratio in the wafer-scale system-level packaging structure, thereby reducing the overall warping of the wafer caused by the small Si / EMC ratio in the wafer-scale system-level packaging structure. Furthermore, the stress buffering flexible component structure can buffer and balance the large stress existing at and near the corners of adjacent functional submodules, thereby reducing the warping of the wafer-scale system-level packaging structure caused by the large stress existing at the corners of the functional submodules. Furthermore, a number of edge dummy devices can be mounted on the upper surface of the edge area of ​​the silicon substrate, thereby increasing the Si / EMC ratio of the edge area of ​​the wafer-scale system-level packaging structure, thereby reducing the difference between the Si / EMC ratio of the edge area and the Si / EMC ratio of the middle area, thereby effectively regulating the warping of the system packaging structure of the wafer-level super-large core module at room temperature or high temperature.

[0045] Furthermore, in one embodiment, the warping and stress regulating structure includes a flexible layer and a rigid layer located on the upper surface of the flexible layer, and the rigidity of the flexible layer is less than that of the rigid layer. The warping and stress regulating structure adopts a rigid-flexible double-layer stacking structure. On the one hand, the rigid-flexible double-layer stacking structure can increase the Si / EMC ratio in the wafer-scale system-level packaging structure, and on the other hand, the rigid-flexible double-layer stacking structure can broaden the application range of the warping and stress regulating structure.

[0046] Furthermore, in one embodiment, at least two of the warping and stress regulating structures are arranged on the upper surface of the silicon substrate at each edge of the functional submodule, which can avoid the aspect ratio of the warping and stress regulating structure being too large, thereby reducing the difficulty of making a suction nozzle (the suction nozzle is used to adsorb the warping and stress regulating structure during mounting) and the difficulty of the mounting process when the warping and stress regulating structure is mounted, while avoiding the stress and warping problems introduced by the excessive aspect ratio of the warping and stress regulating structure.

[0047] Furthermore, in one embodiment, when the warping and stress regulation structure is suspended and mounted on the upper surface of the silicon substrate, on the one hand, the warping and stress regulation structure can increase the Si / EMC ratio in the wafer-scale system-level packaging structure, and on the other hand, there is a gap between the lower surface of the suspended warping and stress regulation structure and the upper surface of the silicon substrate, and the height of the gap can be achieved by adjusting the spacing between adjacent functional sub-modules, thereby adjusting the height difference of the upper and lower surfaces of the warping and stress regulation structure that can be filled with plastic packaging materials, further expanding the application scope of the warping and stress regulation structure.

[0048] Furthermore, in one embodiment, the stress buffering flexible component structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, and the second buffer layer and the core layer have blind holes penetrating the second buffer layer and the core layer. On the one hand, the rigidity of the stress buffering flexible component structure of the structure is relatively small, so as to more effectively buffer and balance the larger stress existing at and near the corners of adjacent functional sub-modules. On the other hand, when a heat dissipation cover is mounted on the upper surface of the plastic encapsulation layer, the functional sub-module, the warping and stress adjustment structure, and the stress buffering flexible component structure, and the outer side surface of the plastic encapsulation layer and the silicon substrate, the stress buffering flexible component structure is The punched flexible component structure provides support and cushioning pads for the lower surface of the heat dissipation cover, and provides a mounting interface for the anchoring protrusions on the lower surface of the horizontal cover top of the heat dissipation cover. At the same time, when the heat dissipation cover is mounted, the anchoring protrusions on the lower surface of the horizontal cover top of the heat dissipation cover are correspondingly mounted in the corresponding blind holes, that is, the blind holes also provide limiting spaces for the anchoring protrusions on the lower surface of the horizontal cover top of the heat dissipation cover, thereby improving the positioning accuracy when mounting the heat dissipation cover, and limiting the mounting accuracy of the heat dissipation cover during the mounting process and the bonding process of the heat dissipation cover. When the anchoring protrusions on the lower surface of the horizontal cover top of the heat dissipation cover are correspondingly mounted in the corresponding blind holes, the anchoring protrusions are locked in the blind holes, thereby improving the firmness of the mounting of the heat dissipation cover.

[0049] Furthermore, in one embodiment, the packaging structure further includes: a reinforcing frame mounted on the lower surface of the silicon substrate, and the upper surface of the edge region of the reinforcing frame is mounted together with the lower surface of the bottom end of the heat dissipation cover edge of the outer side surface of the silicon substrate. The reinforcing frame has a plurality of holes, and the holes expose a portion of the second redistribution layer. The reinforcing frame, on the one hand, plays a role in protecting the lower surface of the silicon substrate, and on the other hand, cooperates with the heat dissipation cover on the upper surface and side of the silicon substrate from the lower surface of the silicon substrate to further adjust and control the warping of the wafer-scale system-level packaging structure. On the other hand, the holes provide limit slots for the next level of packaging and assembly to improve the accuracy of mounting and alignment of the next level of packaging and assembly. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of a top view of a wafer-scale system-level packaging structure in one embodiment of the present application; Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the cutting line AA1; Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure along the cutting line BB1; Figure 4 It is a schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Figure 5 It is a schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Figure 6 A schematic top view of a wafer-scale system-in-package structure in another embodiment of the present application; Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along the cutting line AA1; Figure 8 for Figure 6 Schematic diagram of the cross-sectional structure after the edge is removed; Figure 9-Figure 17 Schematic diagram of the formation process of a wafer-scale system-level packaging structure in one embodiment of the present application. DETAILED DESCRIPTION

[0051] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0052] An embodiment of the present application first provides a system-level packaging structure. Figure 1-Figure 3 ,in Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 3 for Figure 1 The schematic diagram of the cross-sectional structure along the cutting line BB1 ​​includes: A silicon substrate 103, wherein the silicon substrate 103 includes an upper surface and a lower surface opposite to each other; A plurality of functional submodules 20 arranged in an array and mounted on the upper surface of the silicon substrate 103, wherein the plurality of functional submodules 20 are electrically connected to the silicon substrate 103, and each of the functional submodules 20 includes four corners and edges between adjacent corners; The warping and stress adjustment structure 401 on the upper surface of the silicon substrate 103 mounted on the edge of the functional submodule 20; A stress buffering flexible member structure 402 mounted on the upper surface of the silicon substrate 103 at the corner of the functional submodule 20; Edge dummy devices 301 of different sizes mounted on the upper surface of the edge region of the silicon substrate 103 outside the functional submodule array 20; The plastic encapsulation layer 111 is located on the upper surface of the silicon substrate 103 and covers the functional sub-module 20, the warping and stress adjustment structure 401, the stress buffer flexible component structure 402 and the edge dummy device 301, and the plastic encapsulation layer 111 exposes the upper surface of the functional sub-module 20, the warping and stress adjustment structure 401, the stress buffer flexible component structure 402 and the edge dummy device 301.

[0053] Specifically, the silicon substrate 103 includes a silicon wafer body 100 , a first redistribution layer 101 located on an upper surface of the silicon wafer body 100 , and a second redistribution layer 102 located on a lower surface of the silicon wafer body 100 .

[0054] The material of the silicon wafer body 100 is silicon, and the silicon wafer body 100 can be round or square, and the shape of the silicon substrate 103 is also round or square accordingly. In this embodiment, the packaging structure is a wafer-scale system-level packaging structure. The size of the wafer-scale system-level packaging structure is relatively large, and the corresponding sizes of the silicon wafer body 100 and the silicon substrate 103 are also relatively large. In a specific embodiment, when the silicon wafer body 100 and the silicon substrate 103 are round, the diameter size of the silicon wafer body 100 and the silicon substrate 103 can be 300mm, 450±5mm, and when the silicon wafer body 100 and the silicon substrate 103 are square, the diagonal size of the silicon wafer body 100 and the silicon substrate 103 can be 300mm, 450±10mm.

[0055] In one embodiment, the silicon wafer body 100 has a through silicon via 104 and a micro device (not shown in the figure), and the through silicon via 104 is electrically connected to the first redistribution layer 101 and the second redistribution layer 102. In a specific embodiment, the through silicon via 104 is located in the silicon wafer body, and the through silicon via 104 passes through the upper surface and the lower surface of the silicon wafer body 100, the upper end of the through silicon via 104 is electrically connected to the first redistribution layer 101, and the lower end of the through silicon via 104 is electrically connected to the second redistribution layer 102. The material of the through silicon via 104 is metal, which can be one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. The micro-device can be electrically connected to the first redistribution layer 101, and the micro-device can cooperate with the first redistribution layer 101 (and the second redistribution layer 102) to form a circuit with a specific function, and the specific function can be one or more of signal decoupling and voltage stabilization, anti-static and overvoltage protection, or signal filtering, and the specific function can also include other suitable functions. The micro-device can be formed inside the silicon wafer body 100 and / or on the upper surface of the silicon wafer body through a semiconductor integrated manufacturing process. In one embodiment, the micro-device is one or more of a deep trench silicon capacitor (Deep Trench Capacitor, DTC), a protective diode, and a grounding inductor. The high-density trench silicon capacitor can be used for decoupling and voltage stabilization, the protective diode can be used for anti-static and overvoltage protection, and the grounding inductor can be used for signal filtering or isolation.

[0056] The first redistribution layer 101 is located on the upper surface of the silicon wafer body 100. In one embodiment, the first redistribution layer 101 includes a first passivation layer 106 located on the upper surface of the silicon wafer body 100 and a first circuit 105 located in the first passivation layer 106. When the through silicon via 104 is electrically connected to the first redistribution layer 101 and the functional submodule 20 is electrically connected to the silicon substrate 103, the through silicon via 104 and the functional submodule 20 are both electrically connected to the corresponding first circuit 105 in the first redistribution layer 101. In a specific embodiment, the first passivation layer 106 may be a single-layer or multi-layer stacked structure, and the corresponding first circuit 105 may also be a single-layer or multi-layer circuit structure. The material of the first passivation layer 106 may be an inorganic material or an organic material. The inorganic material may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The organic material may be a polymer resin material, and may specifically include epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin. The material of the first circuit 105 is a metal, and may specifically be one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. In a specific embodiment, the first passivation layer 106 is a double-layer stacked structure, including an inorganic material passivation layer located on the upper surface of the silicon wafer body 100 and an organic material passivation layer located on the upper surface of the inorganic material passivation layer.

[0057] The second redistribution layer 102 is located on the lower surface of the silicon wafer body 100. In one embodiment, the second redistribution layer 102 includes a second passivation layer 108 located on the lower surface of the silicon wafer body 100 and a second circuit 107 located in the second passivation layer 108. When the through silicon via 104 is electrically connected to the second redistribution layer 102, the through silicon via 104 is electrically connected to the corresponding second circuit 107 in the second redistribution layer 102. In a specific embodiment, the second passivation layer 108 can be a single-layer or multi-layer stacked structure, and the corresponding second circuit 107 can also be a single-layer or multi-layer circuit structure. The material of the second passivation layer 108 can be an inorganic material or an organic material. The inorganic material can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The organic material can be a polymer resin material, which can specifically include epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin. The material of the second line 107 is metal, specifically, one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. In a specific embodiment, the second passivation layer 108 is a double-layer stacked structure, including an inorganic material passivation layer located on the lower surface of the silicon wafer body 100 and an organic material passivation layer located on the surface of the inorganic material passivation layer.

[0058] In one embodiment, the silicon substrate 103 may include a middle region 11 and an edge region 12 surrounding the middle region 11 , and the functional sub-modules 20 , the warping and stress adjustment structure 401 and the stress buffering flexible component structure 402 are all mounted on the upper surface of the middle region 11 .

[0059] The edge region 12 of the silicon substrate 103 is too narrow to mount the functional submodule 20. When the upper surface of the edge region 12 is completely covered by the plastic layer 111, there is no silicon material on the upper surface of the edge region 12, and the Si / EMC ratio is small (Si is silicon, EMC is plastic material), while the upper surface of the middle region 11 is mounted with a functional submodule, that is, most of the middle region is silicon material, a small part is plastic layer material, and the Si / EMC ratio of the middle region 11 is large, which will cause a large difference in the Si / EMC ratio of the edge region 12 and the middle region 11, resulting in the formation of warpage of the wafer-scale system-level packaging structure. Therefore, in one embodiment, a number of edge dummy devices 301 can be mounted on the upper surface of the edge region 12, thereby increasing the Si / EMC ratio of the edge region 12 of the wafer-scale system-level packaging structure, thereby reducing the difference between the Si / EMC ratio of the edge region 12 and the Si / EMC ratio of the middle region 11, thereby effectively regulating the warpage of the system packaging structure of the wafer-level super-large core module at room temperature or high temperature.

[0060] In one embodiment, the edge dummy device 301 may be one or more of a passive device, a heat dissipation discrete component or a dummy piece. In a specific embodiment, when the edge dummy device 301 mounted on the upper surface of the edge region of the silicon substrate 103 is a passive device, the passive device may be electrically connected to the silicon substrate 103, and the passive device may be one or more of a resistor, a capacitor, and an inductor. In another specific embodiment, when the edge dummy device 301 mounted on the upper surface of the edge region of the silicon substrate 103 is a heat dissipation discrete component, such as a heat dissipation metal block, the lower surface of the heat dissipation discrete component is adhered to the upper surface of the edge region 12 of the silicon substrate 103 by a heat dissipation adhesive, the heat dissipation discrete component may be used for heat dissipation of the packaging structure, and the material of the heat dissipation discrete component is a metal material for heat dissipation. In another specific embodiment, when the edge dummy device 301 mounted on the upper surface of the edge region of the silicon substrate 103 is a dummy piece, the lower surface of the dummy piece is adhered to the upper surface of the edge region 12 of the silicon substrate 103 by an adhesive, and the dummy piece is a silicon particle without a circuit.

[0061] In one embodiment, the size of the edge dummy device 301 away from the middle area 11 is smaller than the size of the edge dummy device 301 close to the middle area 11. The upper surface of the edge area 12 is fully mounted with the edge chip 301, thereby further improving the Si / EMC ratio of the edge area 12 of the wafer-scale system-level packaging structure, thereby further reducing the difference between the Si / EMC ratio of the edge area 12 and the Si / EMC ratio of the middle area 11, which is conducive to better suppressing the warping of the wafer-scale system-level packaging structure.

[0062] In one embodiment, the edge dummy device 301 mounted on the upper surface of the edge region 12 close to the middle region 11 is a passive device or a dummy chip, and the edge dummy device 301 mounted on the upper surface of the edge region 12 away from the middle region 11 is a heat dissipation discrete component or a dummy chip; on the one hand, the mounting method of the passive device or dummy chip (edge ​​dummy device 301) close to the middle region 11 can be the same as the mounting method of the functional sub-module 20 to maintain the consistency of the mounting method; on the other hand, the space between the passive device or dummy chip (edge ​​dummy device 301) close to the middle region 11 and the upper surface of the silicon substrate 103 and the side wall of the passive device or dummy chip (edge ​​dummy device 301) can be covered with a bottom filling layer 302 (refer to Figure 2 or Figure 3 ), when the warping and stress regulating structure 401 is mounted on the upper surface of the silicon substrate 103 outside the edge of the outermost functional submodule 20, the warping and stress regulating structure 401 can be suspended and mounted on the inclined side wall surface (such as the side wall surface of the bottom filling layer 302) of the edge side wall surface of the outermost functional submodule 20 and the side wall surface of the passive device or dummy chip (edge ​​dummy device 301) Figure 2The two warping and stress adjustment structures 401 located on both sides are shown in FIG.

[0063] In one embodiment, when a plurality of dummy edge devices 301 are mounted on the upper surface of the edge region 12 of the silicon substrate 103 , the edge devices may be arranged in rows or columns.

[0064] The functional submodules 20 are chip modules with specific functions. Several functional submodules 20 are arranged in an array and mounted on the upper surface of the silicon substrate 103. The number of the functional submodules 20 is at least 2, and can be 2, 4, 9, 16, 25 or more (for example, N 2 , N is greater than 5), several functional sub-modules 20 can be arranged in AXB arrays such as 1X1, 2X2, 3X3, 4X4, 5X5 (A does not have to be equal to B) or more arrays and mounted on the upper surface of the silicon substrate 103. Figure 1 As shown, nine functional sub-modules 20 are arranged in a 3×3 array and mounted on the upper surface of the silicon substrate 103 as an example.

[0065] In one embodiment, each of the functional submodules 20 has the same structure and function. The plane layout of each of the functional submodules 20 may be rectangular or square. Each of the functional submodules 20 includes four corners and edges between adjacent corners, that is, four corners and four edges. In other embodiments, the plane layout of the functional submodule 20 may be in other shapes, such as a quasi-rectangular, quasi-square, parallelogram or other regular shapes. In one embodiment, each of the submodules 20 includes at least two (≥2) semiconductor chips 201. In a specific embodiment, when each of the submodules 20 includes multiple semiconductor chips 201, the sizes and / or functions of the multiple semiconductor chips 201 are different. In another specific embodiment, when each of the submodules 20 includes multiple semiconductor chips 201, the sizes and / or functions of some of the semiconductor chips 201 may be the same, and the sizes and / or functions of some of the semiconductor chips 201 may be different. In one embodiment, the semiconductor chips 201 include but are not limited to signal processing chips, logic control chips, storage chips, sensor chips, power chips or radio frequency chips.

[0066] The semiconductor chip 201 in each functional submodule 20 is mounted on the upper surface of the silicon substrate 103 by flip-chip method. In one embodiment, the semiconductor chip 201 includes an active surface and a back surface opposite to each other, and the active surface has a welding protrusion 203. An integrated circuit with a specific function (not shown in the figure) is formed in the semiconductor chip 201, and the welding protrusion 203 is electrically connected to the integrated circuit. When the semiconductor chip 201 is mounted on the upper surface of the silicon substrate 103 by flip-chip method, the active surface of the semiconductor chip 201 faces downward, and the welding protrusion 203 on the active surface is welded together with the corresponding first line 105 in the first redistribution layer 101 of the silicon substrate 103. In one embodiment, the welding protrusion 203 may include a welding pad and a solder layer located on the surface of the welding pad. In another embodiment, the welding protrusion 203 may also include a welding pad, a metal column located on the surface of the welding pad, and a solder layer located on the top surface of the metal column. The material of the pad and the metal column is metal, which can be one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The material of the solder layer is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony.

[0067] In one embodiment, each functional submodule 20 further includes an underfill layer 205 filled between the lower surface (active surface) of the semiconductor chip 201 in each functional submodule 20 and the upper surface of the silicon substrate 103 and covering the side of the semiconductor chip 201. In one embodiment, the underfill layer 205 may cover part or all of the sidewalls of the semiconductor chip 201. The underfill layer 205 on the sidewall surface of the semiconductor chip 201 has an inclined sidewall. In one embodiment, the warpage and stress adjustment structure 401 may be suspended and mounted on the sidewall surface (such as the sidewall surface) of the functional submodule 20 by means of adhesive. Figure 2 The warping and stress adjustment structure 401 shown in the middle) (the side wall of the functional sub-module 20 is the inclined side wall of the bottom filling layer 205 of the functional sub-module 20), so that the warping and stress adjustment structure 401 can be suspended and mounted above the upper surface of the silicon substrate 103.

[0068] In the present application, on the upper surface of the silicon substrate 103 at the edge of the functional submodule 20, the Si / EMC ratio in the wafer-scale system-level packaging structure is increased through the warping and stress adjustment structure 401, thereby reducing the overall warping of the wafer caused by the small Si / EMC ratio in the wafer-scale system-level packaging structure. At the same time, a stress buffering flexible component structure 402 is mounted on the upper surface of the silicon substrate 103 between the corner heads of the adjacent functional submodules 20 and outside the corner heads of the outermost functional submodules 20. The stress buffering flexible component structure 402 can buffer and balance the large stress existing at and near the corner heads of the adjacent functional submodules 20, thereby reducing the warping of the wafer-scale system-level packaging structure caused by the large stress existing at the corner heads of the functional submodules 20.

[0069] The number of the warping and stress adjustment structures 401 is several, some of which are mounted on the upper surface of the silicon substrate 103 between the edges of adjacent functional submodules 20, and some of which are mounted on the upper surface of the silicon substrate 103 outside the edge of the outermost functional submodule 20. In one embodiment, the number of the warping and stress adjustment structures 401 mounted on the upper surface of the silicon substrate 103 at each edge of the functional submodule 20 is at least two, and the plurality of the warping and stress adjustment structures 401 are arranged in a direction parallel to the edge of the functional submodule 20, such as Figure 1 Two of the warping and stress regulating structures 401 are mounted on the upper surface of the silicon substrate 103 at each edge of the functional submodule 20. At least two of the warping and stress regulating structures 401 are arranged on the upper surface of the silicon substrate 103 at each edge of the functional submodule 20, which can avoid the warping and stress regulating structure 401 from having an excessively large aspect ratio, thereby reducing the difficulty of making a suction nozzle (the suction nozzle is used to absorb the warping and stress regulating structure 401 during mounting) and the difficulty of mounting the warping and stress regulating structure 401 during mounting, while avoiding the stress and warping problems introduced by the excessive aspect ratio of the warping and stress regulating structure 401.

[0070] In one embodiment, reference Figure 2 or Figure 3 The warpage and stress adjustment structure 401 includes a flexible layer 404 and a rigid layer 403 located on the upper surface of the flexible layer 404, and the rigidity of the flexible layer 404 is less than that of the rigid layer 403. The warpage and stress adjustment structure 401 adopts a rigid-flexible double-layer stacking structure. On the one hand, the rigid-flexible double-layer stacking structure can increase the Si / EMC ratio in the wafer-scale system-level packaging structure, and on the other hand, the rigid-flexible double-layer stacking structure can broaden the application range of the warpage and stress adjustment structure 401.

[0071] In one embodiment, the material of the rigid layer 403 is silicon, silicon germanium or silicon carbide, and the material of the flexible layer 404 is one or more of filler and / or fiber-filled polymer composite materials, specifically epoxy resin molding compound, thermosetting epoxy resin film, semi-cured laminated epoxy resin sheet.

[0072] The warping and stress adjustment structure 401 of the rigid-flexible double-layer stacked structure is mounted on the upper surface of the silicon substrate 103 in two ways: directly contacting and mounting on the upper surface of the silicon substrate 103 and floating mounting on the upper surface of the silicon substrate 103. Figure 2 When performing suspension mounting, part of the warping and stress adjustment structure 401 is suspended and mounted on the side wall surface of the adjacent functional submodule 20 through the adhesive 405. Specifically, the warping and stress adjustment structure 401 is suspended and mounted on the inclined side wall side of the bottom filling layer 205 on the side of the adjacent functional submodule 20 through the adhesive 405 (such as Figure 3 The warping and stress adjustment structure 401 in the middle is shown in FIG. Figure 2 The stress adjustment structure 401 is partially suspended and mounted on the edge sidewall surface of the outermost functional submodule 20 and the inclined sidewall surface of the bottom filling layer 302 of the sidewall surface of the edge dummy device 301 near the middle area 11 by means of adhesive 405 (such as Figure 2 ). When the warping and stress regulating structure 401 is suspended and mounted, on the one hand, the warping and stress regulating structure 401 can increase the Si / EMC ratio in the wafer-scale system-level packaging structure, and on the other hand, there is a gap between the lower surface of the suspended warping and stress regulating structure 401 and the upper surface of the silicon substrate 103, and the height of the gap can be achieved by adjusting the spacing between adjacent functional sub-modules 20, thereby adjusting the height difference of the upper and lower surfaces of the warping and stress regulating structure that can be filled with plastic packaging materials, further expanding the application scope of the warping and stress regulating structure 401.

[0073] In another embodiment, when direct contact mounting is performed, the warping and stress adjustment structure 401 is directly mounted on the upper surface of the silicon substrate 103 between the edges of adjacent functional sub-modules 20 and on the upper surface of the silicon substrate 103 outside the edges of the outermost functional sub-modules 20 through the adhesive 405.

[0074] In another embodiment, the warping and stress adjustment structure 401 may be other structures, please refer to Figure 4, the warping and stress regulating structure 401 can be one or more of a flip chip, a surface mount device, a functional device, a structural dummy sheet, and a heat dissipation dummy sheet. The surface mount device can be a surface mounted passive device. The functional device can be an integrated passive device (IPD), a deep trench silicon capacitor (DTC), a bridge input / output chip (BridgeI / ODie), a logic chip or a multilayer ceramic capacitor (MLCC). The warping and stress regulating structure 401 is welded to the upper surface of the silicon substrate 103 through a solder layer, and the warping and stress regulating structure 401 is electrically connected to the silicon substrate 103. When the warping and stress regulating structure 401 is a structural dummy sheet or a heat dissipation dummy sheet, the lower surface of the warping and stress regulating structure 401 is adhered and mounted on the upper surface of the silicon substrate 103 by an adhesive.

[0075] Continue to refer Figure 1 and Figure 3 The stress buffering flexible component structure 402 has a relatively low rigidity, so that the stress buffering flexible component structure 402 can effectively buffer and balance the large stress existing at and near the corners of adjacent functional sub-modules 20, thereby effectively reducing the warping of the wafer-scale system-level packaging structure caused by the large stress existing at the corners of the functional sub-modules 20.

[0076] In one embodiment, the stress buffering flexible component structure 402 includes a first buffer layer 406, a core layer 408 located on the upper surface of the first buffer layer 406, and a second buffer layer 407 located on the upper surface of the core layer 408. The second buffer layer 407 and the core layer 408 have blind holes 409 that penetrate the second buffer layer 407 and the core layer 408. On the one hand, the rigidity of the stress buffering flexible component structure 402 of the structure is relatively small, so as to more effectively buffer and balance the large stress existing at and near the corners of the adjacent functional sub-modules 20. On the other hand, a heat dissipation cover 501 is mounted on the upper surfaces of the plastic encapsulation layer 111, the functional sub-module 20, the warping and stress adjustment structure 401, and the stress buffering flexible component structure 402, as well as on the outer side surfaces of the plastic encapsulation layer 111 and the silicon substrate 103 (reference Fig.15), the stress buffering flexible member structure 402 provides support and buffering pads for the lower surface of the horizontal cover top of the heat dissipation cover 501, and provides a mounting interface for the anchoring protrusions 506 on the lower surface of the horizontal cover top of the heat dissipation cover 501. At the same time, when the heat dissipation cover 501 is mounted, the anchoring protrusions 506 on the lower surface of the horizontal cover top of the heat dissipation cover 501 are correspondingly mounted in the corresponding blind holes 409, that is, the blind holes 409 also provide limiting spaces for the anchoring protrusions 506 on the lower surface of the horizontal cover top of the heat dissipation cover 501, thereby improving the alignment accuracy of the heat dissipation cover 501 during mounting, and limiting the mounting accuracy of the heat dissipation cover 501 during the mounting process and the bonding process of the heat dissipation cover 501. Moreover, when the anchoring protrusions 506 on the lower surface of the horizontal cover top of the heat dissipation cover 501 are correspondingly mounted in the corresponding blind holes 409, the anchoring protrusions 506 are locked in the blind holes, thereby improving the mounting firmness of the heat dissipation cover 501.

[0077] In one embodiment, the first buffer layer 406 and the second buffer layer 407 are used for stress buffering between the upper and lower surfaces of the stress buffering flexible member structure 402 and other structures. The material of the first buffer layer 406 and the second buffer layer 407 is organic or inorganic buffer material, and the material of the core layer 408 is PCB or substrate material.

[0078] In another embodiment, reference Figure 5 The stress buffer flexible member structure 402 includes a first buffer layer 406, a core layer 408 located on the surface of the first buffer layer 406, and a second buffer layer 407 located on the surface of the core layer 408. The core layer 408 has a blind hole 409. A portion of the lower surface of the heat dissipation cover 501 is attached to the surface of the second buffer layer 407 by adhesive. The blind hole 409 is a cavity, or the blind hole 409 is filled with a filling material 411 (refer to Figure 5 ), when the heat dissipation cover 501 is subsequently mounted, part of the lower surface of the horizontal cover top of the heat dissipation cover 501 is mounted on the upper surface of the second buffer layer 407 in the stress buffering flexible component structure 402 by adhesive. In addition to being able to more effectively buffer and balance the larger stress existing at and near the corners of the adjacent functional submodules 20, the stress buffering flexible component structure 402 also provides support and buffering pads for the lower surface of the horizontal cover top of the heat dissipation cover 501.

[0079] In one embodiment, reference Figure 3 or Figure 5 , the sidewall surface of the blind hole 409 also has a metal layer 410. In one embodiment, reference Figure 5 When the blind hole 409 is filled with a filling material 411 , in addition to the metal layer 410 on the sidewall surface of the blind hole 409 , the top and bottom of the filling material 411 also have metal layers.

[0080] There are multiple stress buffering flexible member structures 402 , and a stress buffering flexible member structure 402 is mounted on the upper surface of the silicon substrate 103 at the corner of each chip sub-module 20 .

[0081] Continue to refer Figure 1-Figure 3 , and also includes: a plastic encapsulation layer 111 located on the upper surface of the silicon substrate 103 and covering the functional sub-module 20, the warping and stress adjustment structure 401, the stress buffer flexible component structure 402 and the edge dummy device 301, the plastic encapsulation layer 111 exposes the upper surface of the functional sub-module 20, the warping and stress adjustment structure 401, the stress buffer flexible component structure 402 and the edge dummy device 301.

[0082] The material of the plastic encapsulation layer 111 may be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin containing fillers; or may be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol containing fillers. In some embodiments, the filler may be an inorganic filler or an organic filler. In some embodiments, the process for forming the plastic encapsulation layer 111 includes compression molding or transfer molding.

[0083] In one embodiment, reference Figure 6 and Figure 7 , Figure 7 for Figure 6 The schematic cross-sectional structure diagram along the cutting line AA1 direction shows that the silicon substrate 103 in the edge region 12 also has a groove 109, which may or may not penetrate the silicon substrate 103, and the plastic encapsulation layer 111 also fills the groove 109. The warping and stress in the edge region 12 of the silicon substrate 103 can be released through the groove 109, thereby reducing the warping of the wafer-scale system-level packaging structure. The depth of the groove 109 can be different according to different process requirements.

[0084] In one embodiment, the groove 109 is formed in the silicon substrate 103 between adjacent edge dummy devices 301. In one embodiment, for a circular silicon substrate 103, the number of the grooves 109 may be four, which are respectively located in the four edge regions 12 around the middle region 11 of the silicon substrate 103. In the edge regions 12 on the left and right sides of the middle region 11, the grooves 109 extend in the longitudinal direction, and in the edge regions 12 on the upper and lower sides of the middle region 11, the grooves 109 extend in the transverse direction. Subsequently, the four sides of the packaged structure may be cut along the four grooves 109 to form a square wafer-scale system-level packaging structure (refer to Figure 8 ).

[0085] In one embodiment, reference Fig.14 and Fig.15 , Fig.14 and Fig.15 Respectively in Figure 2 and Figure 3 The packaging structure further comprises: a heat dissipation cover 501 mounted on the upper surfaces of the plastic encapsulation layer 111, the functional sub-module 20, the warping and stress adjustment structure 401 and the stress buffering flexible component structure 402, and the outer side surfaces of the plastic encapsulation layer 111 and the silicon substrate 103.

[0086] The heat dissipation cover 501 is used to dissipate heat for a wafer-scale system-level packaging structure. The heat dissipation cover 501 includes a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top. The lower surface of the horizontal cover top is horizontal or has an optional downward protrusion in the corresponding area of ​​the functional submodule, the warping and stress adjustment structure, and the stress buffer flexible component structure. The lower surface of the horizontal cover top of the heat dissipation cover 501 is attached to the upper surface of the plastic encapsulation layer 111, the functional submodule 20, the warping and stress adjustment structure 401, and the stress buffer flexible component structure 402, and the inner side wall surface of the cover edge of the heat dissipation cover 501 is attached to the outer side surface of the plastic encapsulation layer 111 and the silicon substrate 103. In a specific embodiment, part of the lower surface of the horizontal cover top of the heat dissipation cover 501 is attached to the upper surface of the plastic sealing layer 111 and the stress buffer flexible part structure 402 through adhesive 503, part of the lower surface of the horizontal cover top of the heat dissipation cover 501 is attached to the upper surface of the functional sub-module 20 through heat dissipation adhesive 502, part of the lower surface of the horizontal cover top of the heat dissipation cover 501 is attached to the upper surface of the warping and stress adjustment structure 401 through adhesive 503 or heat dissipation adhesive 504, and the vertical inner wall surface of the cover edge of the heat dissipation cover 501 is attached to the plastic sealing layer 111 and the outer side surface of the silicon substrate 103 through adhesive 503.

[0087] In one embodiment, reference Fig.15The lower surface of the horizontal cover top of the heat dissipation cover 501 has a plurality of anchoring protrusions 506 protruding downward, and the anchoring protrusions 506 are mounted in the corresponding blind holes 409 through adhesive 503. In one embodiment, the heat dissipation cover 501 is made of a material with high thermal conductivity including metal (such as copper, aluminum, gold, nickel, steel or stainless steel) or a carbon-containing material (such as graphite, graphene or carbon nanotubes).

[0088] In one embodiment, reference Fig.16 and Fig.17 , Fig.16 and Fig.17 Respectively in Fig.14 and Fig.15 The structure obtained on the basis of the above-mentioned packaging structure further includes: a reinforcing frame 601 mounted on the lower surface of the silicon substrate 103, and the upper surface of the edge area of ​​the reinforcing frame 601 is mounted together with the lower surface of the bottom end of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103. The reinforcing frame 601 has a plurality of holes 603, and the holes 603 expose part of the second redistribution layer 102. The reinforcing frame 601 plays a role in protecting the lower surface of the silicon substrate 103 on the one hand, and on the other hand, the lower surface of the silicon substrate 103 cooperates with the heat dissipation cover 501 on the upper surface and side of the silicon substrate 103 to further adjust and control the warpage of the wafer-scale system-level packaging structure. On the other hand, the holes 603 provide limit slots for the next level of packaging and assembly to improve the mounting and alignment accuracy of the next level of packaging and assembly.

[0089] The reinforcing frame 601 includes a middle frame and an edge frame surrounding the middle frame, the edge frame is connected to the middle frame, the edge frame is the edge region of the reinforcing frame 601, the middle frame is in a "grid shape" with a plurality of holes 603, after the reinforcing frame 601 is mounted on the lower surface of the silicon substrate 103, each hole 603 corresponds to exposing a portion of the lower surface of the silicon substrate 103 directly below a corresponding functional submodule 20. The edge frame of the reinforcing frame 601 is mounted together with a portion of the lower surface of the edge region of the silicon substrate 103 and the bottom lower surface of the cover edge of the heat dissipation cover 501 on the outer side surface of the silicon substrate 103, and the middle frame of the reinforcing frame 601 is mounted together with a portion of the lower surface of the middle region of the silicon substrate 103.

[0090] The reinforcing frame 601 is made of metal and is attached to a portion of the lower surface of the silicon substrate 103 and the lower surface of the bottom end of the cover edge of the heat dissipation cover 501 on the outer side surface of the silicon substrate 103 by means of adhesive 604 .

[0091] In one embodiment, the upper surface of the edge area of ​​the reinforcing frame 601 has a protruding structure 602, and the lower surface of the bottom end of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 has a groove structure 505. When the upper surface of the edge area of ​​the reinforcing frame 601 and the lower surface of the bottom end of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 are mounted together, the protruding structure 602 on the upper surface of the edge area of ​​the reinforcing frame 601 is mounted in the corresponding groove structure 505 on the lower surface of the bottom end of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 through adhesive 604. The groove structure 505 on the bottom lower surface of the cover edge of the heat dissipation cover 501 on the outer side surface of the silicon substrate 103 plays a role in anchoring and aligning the reinforcement frame 601 for mounting, and when the raised structure 602 on the edge area of ​​the reinforcement frame 601 is correspondingly mounted in the groove structure 505 on the bottom lower surface of the cover edge of the heat dissipation cover 501, the raised structure 602 is limited in the groove structure 505, which can improve the mounting firmness of the reinforcement frame 601.

[0092] In another embodiment, the upper surface of the edge region of the reinforcing frame 601 has a groove structure, and the lower surface of the bottom end of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 has a convex structure. When the upper surface of the edge region of the reinforcing frame 601 and the lower surface of the bottom end of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 are attached together, the convex structure on the lower surface of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 is attached to the corresponding groove structure on the upper surface of the edge region of the reinforcing frame 601 through adhesive. The convex structure on the lower surface of the bottom end of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 plays the role of anchoring and aligning for attaching the reinforcing frame 601, and when the convex structure on the lower surface of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 is attached to the groove structure on the upper surface of the edge region of the reinforcing frame 601, the convex structure is locked in the groove structure, which can improve the mounting firmness of the reinforcing frame 601.

[0093] Another embodiment of the present application further provides a method for forming a wafer-scale system-level packaging structure, which is described below in conjunction with the accompanying drawings (it should be noted that the same or similar parts of this embodiment (the method for forming a wafer-scale system-level packaging structure) and the aforementioned embodiment (the wafer-scale system-level packaging structure) are not repeated in this embodiment, and please refer to the definitions or descriptions of the corresponding parts in the aforementioned embodiment for details).

[0094] refer to Fig. 9 , providing a silicon substrate 103, wherein the silicon substrate 103 includes an upper surface and a lower surface opposite to each other.

[0095] The silicon substrate 103 includes a silicon wafer body 100 , a first redistribution layer 101 located on an upper surface of the silicon wafer body 100 , and a second redistribution layer 102 located on a lower surface of the silicon wafer body 100 .

[0096] In one embodiment, the silicon substrate 103 includes a middle area 11 and an edge area 12 surrounding the middle area 11 , and subsequent functional sub-modules 20 , a warping and stress adjustment structure 401 , and a stress buffering flexible component structure 402 are all mounted on the upper surface of the middle area of ​​the silicon substrate 103 .

[0097] refer to Fig.10 and Fig.11 A plurality of functional sub-modules 20 arranged in an array are surface mounted on the silicon substrate 103, the plurality of functional sub-modules 20 are electrically connected to the silicon substrate 103, and each of the functional sub-modules 20 includes four corners and edges between adjacent corners.

[0098] In one embodiment, before mounting the functional submodule 20, a protective layer 110 is formed on the lower surface of the silicon substrate 103, and the protective layer 110 is used to protect the second redistribution layer 102 on the lower surface of the silicon substrate 103 in the subsequent process. The material of the protective layer 110 can be metal (such as Al, Ti, TiW) or inorganic material (such as silicon oxide or silicon nitride). After the protective layer 110 is formed, a temporary carrier 113 is bonded to the lower surface of the protective layer 110 through a bonding layer 112, and the temporary carrier 113 can be removed after the subsequent related process steps are completed.

[0099] In one embodiment, it further includes: mounting a plurality of edge dummy devices 301 on the upper surface of the edge region of the silicon substrate 103. The edge dummy devices 301 are one or more of passive devices, heat dissipation discrete components or dummy chips. In one embodiment, the space between the edge dummy devices 301 near the middle region 11 and the upper surface of the silicon substrate 103 and the sidewalls of the edge dummy devices 301 can be covered with a bottom filling layer 302.

[0100] In one embodiment, each of the submodules 20 includes at least two semiconductor chips 201, and the semiconductor chips 201 are flip-chip mounted on the upper surface of the silicon substrate 103. Each functional submodule 20 also includes an underfill layer 205 filled between the semiconductor chip 201 in each functional submodule 20 and the upper surface of the silicon substrate 103 and covering the side surfaces of the semiconductor chip 201.

[0101] Continue to refer Fig.10, a warping and stress adjustment structure 401 is mounted on the surface of the silicon substrate 103 at the edge of the functional submodule 20; a stress buffering flexible component structure 402 is mounted on the surface of the silicon substrate 103 at the corner of the functional submodule 20 (refer to Figure 2 or Figure 3 ).

[0102] In one embodiment, the warping and stress adjustment structure 401 includes a flexible layer 404 and a rigid layer 403 located on an upper surface of the flexible layer 404 , and the rigidity of the flexible layer 404 is less than that of the rigid layer 403 .

[0103] In one embodiment, mounting the warp and stress adjustment structure 401 on the upper surface of the silicon substrate 103 includes: directly mounting the warp and stress adjustment structure 401 on the upper surface of the silicon substrate 103 through an adhesive, or suspending the warp and stress adjustment structure 401 through an adhesive (such as Fig.11 As shown in FIG. 1 , the inclined side wall side of the bottom filling layer 205 on the side adjacent to the functional sub-module 20 is provided.

[0104] In another embodiment, the warpage and stress adjustment structure 401 is one or more of a flip chip, a surface mount device, a functional device, a structural dummy sheet, and a heat dissipation dummy sheet (see Figure 4 ).

[0105] In one embodiment, the stress buffering flexible member structure 402 includes a first buffer layer 406, a core layer 408 located on the upper surface of the first buffer layer 406, and a second buffer layer 407 located on the upper surface of the core layer 408. The second buffer layer 407 and the core layer 408 have blind holes 409, and the openings of the blind holes 409 are partially closed by the second buffer layer 407. When the plastic encapsulation layer 111 is subsequently formed (refer to Fig.12 ), when the plastic encapsulation layer is thinned, a portion of the second buffer layer 407 is removed to expose the blind hole 409. When the heat dissipation cover 501 is subsequently mounted, the anchoring protrusion 506 on the lower surface of the heat dissipation cover 501 is mounted in the corresponding blind hole 409 by adhesive (refer to Fig.15 ).

[0106] In another embodiment, the stress buffering flexible member structure 402 includes a first buffer layer 406, a core layer 408 located on the upper surface of the first buffer layer 406, and a second buffer layer 407 located on the upper surface of the core layer 408, wherein the core layer 408 has a blind hole 409, and the blind hole 409 is a cavity or filled with a filling material 411 (refer to Figure 5 ), when the heat dissipation cover 501 is subsequently mounted, part of the lower surface of the heat dissipation cover 501 is mounted on the surface of the second buffer layer 407 by adhesive.

[0107] refer to Fig.12 A plastic encapsulation layer 111 is formed on the upper surface of the silicon substrate 103 to cover the functional sub-module 20, the warping and stress adjustment structure 401, the stress buffer flexible component structure 402 and the edge dummy device 301, and the plastic encapsulation layer 111 exposes the upper surfaces of the functional sub-module 20, the warping and stress adjustment structure 401, the stress buffer flexible component structure 402 and the edge dummy device 301.

[0108] In one embodiment, before forming the plastic encapsulation layer 111, the method further includes: forming a groove 109 in the silicon substrate 103 in the edge region 12 (see Figure 6 and Figure 7 ), the groove 109 may or may not penetrate the silicon substrate 103; when the plastic encapsulation layer 111 is formed, the plastic encapsulation layer 111 also fills the groove 109. Before attaching the heat dissipation cover, the edge area is cut and removed along the groove 109 to form a wafer-scale system-level packaging structure (refer to Figure 8 ).

[0109] In one embodiment, before attaching the heat dissipation cover 501, refer to Fig.13 and Fig.14 , remove the carrier 113, form a flexible detachable protective film 114 on the lower surface of the silicon substrate 103, and remove the detachable protective film 114 after the subsequent mounting of the heat dissipation cover 501. The detachable protective film 114 provides a flat mounting surface for the subsequent mounting of the heat dissipation cover 501, and the mounting surface needs to be directly adsorbed on the vacuum platform of the mounting equipment. Since the mounting process of the heat dissipation cover 501 needs to be hot-pressed at about 150°C to ensure that the heat dissipation cover 501 is hot-pressed and mounted with less warpage in the wafer-scale system-level packaging structure, the detachable protective film 114 needs to be flexible and able to withstand a hot pressing process of about 150°C and 10 minutes.

[0110] In one embodiment, reference Fig.14 and Fig.15 , further comprising: mounting a heat dissipation cover 501 on the upper surfaces of the plastic encapsulation layer 111 , the functional sub-module 20 , the warping and stress adjustment structure 401 and the stress buffering flexible component structure 402 , and on the outer side surfaces of the plastic encapsulation layer 111 and the silicon substrate 103 .

[0111] In one embodiment, the heat dissipation cover 501 includes a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top, the lower surface of the horizontal cover top of the heat dissipation cover 501 is attached to the upper surface of the plastic packaging layer 111, the functional sub-module 20, the warping and stress adjustment structure 401 and the stress buffer flexible part structure 402, and the inner side wall surface of the cover edge of the heat dissipation cover 501 is attached to the outer side surface of the plastic packaging layer 111 and the silicon substrate 103.

[0112] In one embodiment, the lower surface of the horizontal cover top of the heat dissipation cover 501 has a plurality of anchoring protrusions 506 protruding downwards, and the anchoring protrusions 506 are mounted in corresponding blind holes 409 by adhesive 503 .

[0113] In one embodiment, reference Fig.16 and Fig.17 , further comprising: mounting a reinforcing frame 601 on the lower surface of the silicon substrate 103, and mounting the upper surface of the edge region of the reinforcing frame 601 together with the lower surface of the bottom end of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103. The reinforcing frame 601 has a plurality of holes 603, and when the reinforcing frame 601 is mounted, the holes 603 expose a portion of the second redistribution layer 102.

[0114] In one embodiment, the upper surface of the edge area of ​​the reinforcing frame 601 has a protruding structure 602, and the bottom lower surface of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 has a groove structure 505. When the upper surface of the edge area of ​​the reinforcing frame 601 and the bottom lower surface of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 are mounted together, the protruding structure 602 on the upper surface of the edge area of ​​the reinforcing frame 601 is mounted in the corresponding groove structure 505 on the bottom lower surface of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 through adhesive 604.

[0115] In another embodiment, the upper surface of the edge area of ​​the reinforcing frame 601 has a groove structure, and the bottom lower surface of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 has a convex structure. When the upper surface of the edge area of ​​the reinforcing frame 601 and the bottom lower surface of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 are mounted together, the convex structure on the bottom lower surface of the cover edge of the heat dissipation cover 501 on the outer side of the silicon substrate 103 is mounted in the corresponding groove structure on the upper surface of the edge area of ​​the reinforcing frame 601 by adhesive.

[0116] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A wafer-scale system-level packaging structure, characterized in that: include: a silicon substrate comprising an upper surface and a lower surface opposite to each other; A plurality of functional submodules arranged in an array and mounted on the upper surface of the silicon substrate, the plurality of functional submodules being electrically connected to the silicon substrate, and each of the functional submodules comprising four corners and edges between adjacent corners; a warping and stress regulating structure mounted on the upper surface of the silicon substrate at the edge of the functional submodule; A stress buffering flexible component structure mounted on the upper surface of the silicon substrate of the functional submodule corner head; Edge dummy devices of different sizes mounted on the upper surface of the edge region of the silicon substrate outside the functional submodule array; A plastic encapsulation layer is located on the upper surface of the silicon substrate and covers the functional sub-module, the warping and stress adjustment structure, the stress buffer flexible component structure and the edge dummy device, and the plastic encapsulation layer exposes the upper surface of the functional sub-module, the warping and stress adjustment structure, the stress buffer flexible component structure and the edge dummy device.

2. The wafer-scale system-in-package structure according to claim 1, wherein: The warping and stress adjustment structure includes a flexible layer and a rigid layer located on an upper surface of the flexible layer, and the rigidity of the flexible layer is less than that of the rigid layer.

3. The wafer-scale system-in-package structure according to claim 2, wherein: The material of the rigid layer of the warping and stress adjustment structure is silicon, silicon germanium or silicon carbide, and the material of the flexible layer is one or more of filler and / or fiber-filled polymer composite materials.

4. The wafer-scale system-in-package structure according to claim 2, wherein: The warping and stress regulating structure is mounted on the upper surface of the silicon substrate, including: the warping and stress regulating structure is mounted on the upper surface of the silicon substrate in direct contact, or the warping and stress regulating structure is mounted in a suspended manner on the upper surface of the silicon substrate.

5. The wafer-scale system-in-package structure according to claim 1, wherein: The warping and stress adjustment structure is one or more of a flip chip, a surface mount device, a functional device, a structural dummy sheet, and a heat dissipation dummy sheet.

6. The wafer-scale system-in-package structure according to claim 2 or 5, characterized in that: The number of the warping and stress regulating structures mounted on the surface of the silicon substrate at each edge of the functional submodule is at least two, and the plurality of warping and stress regulating structures are arranged in a direction parallel to the edge of the functional submodule.

7. The wafer-scale system-in-package structure according to claim 1, wherein: The silicon substrate comprises a middle area and an edge area surrounding the middle area, and a plurality of functional submodules are mounted on the upper surface of the middle area of ​​the silicon substrate; and a plurality of dummy devices are mounted on the upper surface of the edge area of ​​the silicon substrate.

8. The wafer-scale system-in-package structure according to claim 7, wherein: The dummy device is one or more of a passive device, a heat dissipation discrete component or a dummy chip.

9. The wafer-scale system-in-package structure according to claim 7, wherein: The size of the dummy device far from the middle area is smaller than the size of the dummy device near the middle area.

10. The wafer-scale system-in-package structure according to claim 7, wherein: The silicon substrate in the edge region also has a groove, which may or may not penetrate the silicon substrate, and the plastic sealing layer also fills the groove.

11. The wafer-scale system-in-package structure according to claim 1 or 7, characterized in that: Also includes: A heat dissipation cover mounted on the upper surfaces of the plastic encapsulation layer, the functional submodules, the warping and stress regulating structure and the stress buffering flexible component structure, and the outer side surfaces of the plastic encapsulation layer and the silicon substrate, the heat dissipation cover comprising a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top, the lower surface of the horizontal cover top is horizontal or has an optional downward protrusion in the corresponding area of ​​the functional submodule, the warping and stress regulating structure and the stress buffering flexible component structure, the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surfaces of the plastic encapsulation layer, the functional submodule, the warping and stress regulating structure and the stress buffering flexible component structure, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surfaces of the plastic encapsulation layer and the silicon substrate.

12. The wafer-scale system-in-package structure according to claim 11, wherein: The stress buffering flexible member structure is a flexible structure, and the rigidity of the stress buffering flexible member structure is less than the rigidity of the plastic packaging layer.

13. The wafer-scale system-in-package structure according to claim 11, wherein: The stress buffer flexible component structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer. The second buffer layer and the core layer have blind holes that penetrate the second buffer layer and the core layer, and the plastic packaging layer exposes the blind holes.

14. The wafer-scale system-in-package structure according to claim 13, wherein: The lower surface of the horizontal cover top of the heat dissipation cover is provided with a plurality of anchoring protrusions protruding downwards, and the anchoring protrusions are mounted in corresponding blind holes by adhesive.

15. The wafer-scale system-in-package structure according to claim 11, wherein: The stress buffer flexible component structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer. The core layer has a blind hole, and a portion of the lower surface of the horizontal cover top of the heat dissipation cover is attached to the upper surface of the second buffer layer by adhesive.

16. The wafer-scale system-in-package structure according to claim 15, wherein: The blind hole is a cavity, or the blind hole is filled with filling material.

17. The wafer-scale system-in-package structure according to claim 13 or 15, characterized in that: The side wall surface of the blind hole also has a metal layer.

18. The wafer-scale system-in-package structure according to claim 11, wherein: Also includes: A reinforcing frame is mounted on the lower surface of the silicon substrate, and the upper surface of the edge region of the reinforcing frame is mounted together with the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side of the silicon substrate.

19. The wafer-scale system-in-package structure according to claim 18, wherein: The silicon substrate includes a silicon wafer body, a first redistribution layer located on the upper surface of the silicon wafer body and a second redistribution layer located on the lower surface of the silicon wafer body. The reinforcement frame has a plurality of holes, and the holes expose part of the second redistribution layer.

20. The wafer-scale system-in-package structure according to claim 18, wherein: The upper surface of the edge area of ​​the reinforcing frame has a convex structure, and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side of the silicon substrate has a groove structure. When the upper surface of the edge area of ​​the reinforcing frame and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side of the silicon substrate are mounted together, the convex structure on the upper surface of the edge area of ​​the reinforcing frame is mounted in the corresponding groove structure on the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side of the silicon substrate through adhesive.

21. The wafer-scale system-in-package structure according to claim 11, wherein: The upper surface of the edge area of ​​the reinforcing frame has a groove structure, and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate has a convex structure. When the upper surface of the edge area of ​​the reinforcing frame and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate are mounted together, the convex structure on the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate is mounted in the corresponding groove structure on the upper surface of the edge area of ​​the reinforcing frame by adhesive.

22. The wafer-scale system-in-package structure according to claim 1, wherein: Each of the functional submodules has the same structure, and the functional submodule comprises at least two semiconductor chips, and the at least two semiconductor chips are mounted on the upper surface of the silicon substrate in a flip-chip manner; Each functional submodule further includes an underfill layer which is filled between the lower surface of the semiconductor chip in each functional submodule and the upper surface of the silicon substrate and covers the side surfaces of the semiconductor chip.

23. The wafer-scale system-in-package structure according to claim 1, wherein: The diagonal dimension of the silicon substrate is 300 or 450±10 mm, or the diameter of the silicon substrate is 300 mm or 450±5 mm.

24. A method for forming a wafer-scale system-level packaging structure, characterized in that: include: Providing a silicon substrate, the silicon substrate comprising an upper surface and a lower surface opposite to each other; Mounting a plurality of functional submodules arranged in an array on the surface of the silicon substrate, the plurality of functional submodules being electrically connected to the silicon substrate, and each of the functional submodules comprising four corners and edges between adjacent corners; Mounting a warpage and stress adjustment structure on the silicon substrate at the edge of the functional submodule; Mounting a stress buffering flexible component structure on the surface of the silicon substrate of the corner of the functional submodule; Mounting dummy edge devices of different sizes on the surface of the edge area of ​​the silicon substrate outside the functional submodule array; A plastic encapsulation layer covering the functional sub-module, the warping and stress regulating structure, the stress buffering flexible component structure and the edge dummy device is formed on the upper surface of the silicon substrate, and the plastic encapsulation layer exposes the upper surface of the functional sub-module, the warping and stress regulating structure, the stress buffering flexible component structure and the edge dummy device.

25. The method for forming a wafer-scale system-in-package structure according to claim 24, wherein: The warping and stress adjustment structure includes a flexible layer and a rigid layer located on an upper surface of the flexible layer, and the rigidity of the flexible layer is less than that of the rigid layer.

26. The method for forming a wafer-scale system-in-package structure according to claim 25, wherein: Mounting the warp and stress adjustment structure on the upper surface of the silicon substrate includes: mounting the warp and stress adjustment structure on the upper surface of the silicon substrate in direct contact, or mounting the warp and stress adjustment structure in a suspended manner on the upper surface of the silicon substrate.

27. The method for forming a wafer-scale system-in-package structure according to claim 24, wherein: The warping and stress adjustment structure is one or more of a flip chip, a surface mount device, a functional device, a structural dummy sheet, and a heat dissipation dummy sheet.

28. The method for forming a wafer-scale system-in-package structure according to claim 24, wherein: The silicon substrate comprises a middle area and an edge area surrounding the middle area, and a plurality of functional submodules are mounted on the upper surface of the middle area of ​​the silicon substrate; and a plurality of dummy devices are mounted on the upper surface of the edge area of ​​the silicon substrate.

29. The method for forming a wafer-scale system-in-package structure according to claim 28, wherein: Also includes: forming a groove in the silicon substrate in the edge region, wherein the groove penetrates or does not penetrate the silicon substrate; When the plastic encapsulation layer is formed, the plastic encapsulation layer also fills the groove.

30. The method for forming a wafer-scale system-in-package structure according to claim 24 or 28, wherein: Also includes: A heat dissipation cover is mounted on the upper surfaces of the plastic encapsulation layer, the functional sub-modules, the warping and stress regulating structure and the stress buffering flexible component structure, as well as the outer side surfaces of the plastic encapsulation layer and the silicon substrate. The heat dissipation cover includes a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top. The lower surface of the horizontal cover top is horizontal or has an optional downward protrusion in the corresponding area of ​​the functional sub-module, the warping and stress regulating structure and the stress buffering flexible component structure. The lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surfaces of the plastic encapsulation layer, the functional sub-module, the warping and stress regulating structure and the stress buffering flexible component structure, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surfaces of the plastic encapsulation layer and the silicon substrate.

31. The method for forming a wafer-scale system-in-package structure according to claim 30, wherein: The stress buffer flexible component structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer. The second buffer layer and the core layer have blind holes that penetrate the second buffer layer and the core layer, and the plastic packaging layer exposes the blind holes.

32. The method for forming a wafer-scale system-in-package structure as claimed in claim 31, characterized in that: The lower surface of the horizontal cover top of the heat dissipation cover is provided with a plurality of protruding anchoring protrusions. When the heat dissipation cover is mounted, the anchoring protrusions are mounted in corresponding blind holes by adhesive.

33. The method for forming a wafer-scale system-in-package structure as claimed in claim 30, wherein: The stress buffer flexible component structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer. The core layer has a blind hole. When the heat dissipation cover is mounted, a portion of the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the surface of the second buffer layer by adhesive.

34. The method for forming a wafer-scale system-in-package structure as claimed in claim 30, wherein: Also includes: A reinforcing frame is mounted on the lower surface of the silicon substrate, and the upper surface of the edge region of the reinforcing frame is mounted together with the bottom end surface of the cover edge of the heat dissipation cover on the outer side of the silicon substrate.

35. The method for forming a wafer-scale system-in-package structure as claimed in claim 34, characterized in that: The silicon substrate includes a silicon wafer body, a first redistribution layer located on the upper surface of the silicon wafer body, and a second redistribution layer located on the lower surface of the silicon wafer body. The reinforcement frame has a plurality of holes. When the reinforcement frame is mounted, the holes expose part of the second redistribution layer.

36. The method for forming a wafer-scale system-in-package structure as claimed in claim 34, wherein: The upper surface of the edge area of ​​the reinforcing frame has a convex structure, and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side of the silicon substrate has a groove structure. When the upper surface of the edge area of ​​the reinforcing frame and the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side of the silicon substrate are mounted together, the convex structure on the upper surface of the edge area of ​​the reinforcing frame is mounted in the corresponding groove structure on the lower surface of the bottom end of the cover edge of the heat dissipation cover on the outer side of the silicon substrate through adhesive.

37. The method for forming a wafer-scale system-in-package structure as claimed in claim 34, characterized in that: The upper surface of the edge area of ​​the reinforcing frame has a groove structure, and the bottom lower surface of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate has a convex structure. When the upper surface of the edge area of ​​the reinforcing frame and the bottom lower surface of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate are attached together, the convex structure on the bottom lower surface of the cover edge of the heat dissipation cover on the outer side surface of the silicon substrate is attached to the corresponding groove structure on the upper surface of the edge area of ​​the reinforcing frame by adhesive.

Images