Capacitor device and manufacturing method thereof

Abstract

The invention provides a capacitor device and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate in which a first metal wire, a second metal wire and an insulating layer are formed; forming a plurality of grooves in the insulating layer; sequentially forming a first electrode material layer, a first dielectric material layer and a second electrode material layer to cover the insulating layer and the groove; executing a patterning process to cover the first electrode, the first dielectric layer and the second electrode, and exposing the second electrode and a part of the surface of the first electrode; forming a second dielectric layer; and forming a plurality of through holes in the second dielectric layer and the insulating layer, forming a third metal wire electrically connected with the first metal wire and the second electrode, and forming a fourth metal wire electrically connected with the second metal wire and the first electrode. According to the invention, the two electrodes of the capacitor are led out downwards by using the first metal wire and the second metal wire in the substrate, so that the process integration difficulty is reduced, and the design freedom degree of the capacitor is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a capacitor device and a manufacturing method thereof. Background Art

[0002] Capacitors are a common passive component widely used in the field of integrated circuits. In some special applications, capacitors with large unit capacitance are needed to improve product performance, such as storing signals, reducing noise, and reducing coupling. Planar capacitors need to occupy a large area to obtain large capacitance, which will sacrifice design area. For this reason, trench capacitors become the best choice for large capacitors.

[0003] In the related art, the electrodes of the capacitors in the capacitor device are usually electrically led upward, and the trenches thereof need to be filled with metal, which results in the structure and process of electrically leading the trench capacitors to be more complicated and is not conducive to the design of the trench capacitors. Summary of the invention

[0004] The object of the present invention is to provide a capacitor device and a manufacturing method thereof, so as to optimize the structure and manufacturing process of a trench capacitor.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a capacitor device, comprising:

[0006] Providing a substrate, wherein a first metal line and a second metal line arranged in the same layer and an insulating layer covering the first metal line and the second metal line are formed in the substrate;

[0007] forming a plurality of grooves in the insulating layer between the first metal line and the second metal line;

[0008] forming a first electrode material layer, a first dielectric material layer and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the groove;

[0009] Performing a patterning process on the second electrode material layer, the first dielectric material layer and the first electrode material layer to form a first electrode, a first dielectric layer and a second electrode covering the trench and the insulating layer around the trench, and exposing the second electrode and a portion of the first electrode;

[0010] forming a second dielectric layer to cover the insulating layer, the first electrode, the second electrode and the trench;

[0011] A plurality of through holes are formed in the second dielectric layer and the insulating layer to expose the first electrode, the second electrode, the first metal wire and the second metal wire respectively, and a third metal wire is formed to electrically connect the first metal wire and the second electrode, and a fourth metal wire is formed to electrically connect the second metal wire and the first electrode.

[0012] Optionally, a dielectric barrier layer is further provided between the first metal wire, the second metal wire and the insulating layer.

[0013] Optionally, a capacitor region is provided on the insulating layer between the first metal line and the second metal line, and the step of forming a plurality of the grooves in the capacitor region includes:

[0014] forming a first mask to cover the surface of the insulating layer and to form a plurality of openings in the capacitor region;

[0015] Using the first mask and the dielectric barrier layer as an etching stop layer, dry etching the insulating layer to form a plurality of the grooves in the capacitor region;

[0016] The first mask is removed.

[0017] Optionally, the capacitor region has a first side and a second side respectively close to the first metal line and the second metal line, and the step of forming the second electrode and the first dielectric layer includes:

[0018] forming a second mask to cover the second electrode material layer in the capacitor region, wherein the second mask extends to cover the second electrode material layer close to the first side;

[0019] Using the second mask, etching the second electrode material layer and the first dielectric material layer to expose the surface of the first electrode material layer, and using the remaining second electrode material layer as the second electrode, and using the remaining first dielectric material layer as the first dielectric layer;

[0020] The second mask is removed.

[0021] Optionally, the step of forming the first electrode includes:

[0022] forming a third mask to cover the second electrode, wherein the third mask extends to cover the first electrode material layer close to the second side;

[0023] Using the third mask, etching the first electrode material layer to expose the surface of the insulating layer, and using the remaining first electrode material layer as the first electrode;

[0024] The third mask is removed.

[0025] Optionally, the step of forming a plurality of through holes includes:

[0026] Forming a plurality of first through holes in the second dielectric layer to expose the first electrode and the second electrode respectively;

[0027] A plurality of second through holes are formed in the insulating layer and the second dielectric layer to expose the first metal line and the second metal line respectively.

[0028] Optionally, the step of forming the third metal line and the fourth metal line includes:

[0029] forming a metal material layer to cover the surface of the second dielectric layer, the first through hole and the inner wall of the second through hole;

[0030] A patterning process is performed on the metal material layer to form the third metal line electrically connecting the first metal line and the second electrode, and to form the fourth metal line electrically connecting the second metal line and the first electrode.

[0031] Optionally, when the patterning process is performed on the metal material layer, a metal pad is also simultaneously formed on the surface of the insulating layer for connection with an external circuit.

[0032] Optionally, the material of the first electrode material layer and the second electrode material layer includes one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

[0033] According to another aspect of the present invention, there is also provided a capacitor device, comprising:

[0034] substrate;

[0035] A first metal line and a second metal line are arranged in the substrate in the same layer;

[0036] an insulating layer covering the first metal line and the second metal line, wherein a plurality of grooves are formed in the insulating layer between the first metal line and the second metal line, and a plurality of second through holes are formed in the insulating layer on the first metal line and the second metal line to expose the first metal line and the second metal line respectively;

[0037] A capacitor formed in the trench and on the insulating layer around it, comprising a first electrode, a first dielectric layer and a second electrode formed conformally in sequence;

[0038] A second dielectric layer covers the capacitor, and a plurality of first through holes are formed in the second dielectric layer to expose the first electrode and the second electrode respectively;

[0039] The third metal wire and the fourth metal wire utilize the first through hole and the second through hole. The third metal wire electrically connects the first metal wire and the second electrode, and the fourth metal wire electrically connects the third metal wire and the first electrode.

[0040] In summary, the present invention has a plurality of grooves in the insulating layer between the first metal wire and the second metal wire, and forms a capacitor in the groove and on the insulating layer around the groove, the capacitor includes a first electrode, a first dielectric layer and a second electrode which are formed conformally in sequence, the first electrode and the second electrode respectively extend to both sides of the capacitor and are both exposed upward, then a second dielectric layer is formed to cover the capacitor and the insulating layer, and through holes are formed in the second dielectric layer and the insulating layer to expose the first metal wire, the second metal wire, the first electrode and the second electrode respectively, then a third metal wire is formed by the through hole to electrically connect the first electrode and the first metal wire, and a fourth metal wire is formed to electrically connect the second electrode and the second metal wire, thereby the two electrodes of the capacitor are led downward by the first metal wire and the second metal wire in the substrate, and the lead-out of the capacitor in the capacitor device and the wiring of the metal wire on the insulating layer are completed without adding additional process steps, so that it has a simple lead-out structure, reduces the difficulty of process integration, and is conducive to improving the capacitance density and design freedom of the capacitor in the capacitor device. In addition, compared with the related art where trench capacitors require metal to fill the trenches, the two electrodes of the trench capacitor in this embodiment extend to both sides to achieve electrical lead-out and do not need to be filled with metal, that is, voids are allowed to exist, which is beneficial to improving the freedom of capacitor design in capacitor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0042] Figure 1 is a flow chart of a method for manufacturing a capacitor device provided in Example 1;

[0043] Figure 2a to Figure 2l This is a schematic structural diagram corresponding to the corresponding steps of the method for manufacturing a capacitor device provided in the first embodiment.

[0044] In the attached figure:

[0045] 10-substrate; 11-first metal wire; 12-second metal wire; AA-capacitor area; A1-first side; A2-second side; 21-dielectric barrier layer; 22-insulating layer; 23-groove; 24-first electrode material layer; 24a-first electrode; 25-first dielectric material layer; 25a-first dielectric layer; 26-second electrode material layer; 26a-second electrode; 27-second mask; 28-third mask; 31-second dielectric layer; 32-first through hole; 33-second through hole; 34-metal material layer; 35-third metal wire; 36-fourth metal wire. DETAILED DESCRIPTION

[0046] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0047] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0048] Embodiment 1

[0049] Figure 1 4 is a flow chart of a method for manufacturing a capacitor device provided in the first embodiment.

[0050] like Figure 1 As shown, the manufacturing method of the capacitor device provided in this embodiment includes:

[0051] S01: providing a substrate, wherein a first metal wire and a second metal wire arranged in the same layer and an insulating layer covering the first metal wire and the second metal wire are formed on the substrate;

[0052] S02: forming a plurality of grooves in the insulating layer between the first metal line and the second metal line;

[0053] S03: forming a first electrode material layer, a first dielectric material layer and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the groove;

[0054] S04: performing a patterning process on the second electrode material layer, the first dielectric material layer and the first electrode material layer to form a second electrode covering the trench and the insulating layer around the trench, a first dielectric layer and a first electrode, and exposing the surfaces of the second electrode and a portion of the first electrode;

[0055] S05: forming a second dielectric layer to cover the insulating layer, the first electrode, the second electrode and the trench;

[0056] S06: forming a plurality of through holes in the second dielectric layer and the insulating layer to expose the first electrode, the second electrode, the first metal wire and the second metal wire respectively, forming a third metal wire to electrically connect the first metal wire and the second electrode, and forming a fourth metal wire to electrically connect the second metal wire and the first electrode.

[0057] Figure 2a to Figure 2l The structural schematic diagram corresponding to the corresponding steps of the manufacturing method of the capacitor device provided in this embodiment, next, Figure 2a to Figure 2l A method for manufacturing the capacitive device is described in detail.

[0058] First, please refer to Figure 2a , perform step S01, provide a substrate 10, and form a first metal wire 11 and a second metal wire 12 arranged in the same layer and an insulating layer 22 covering the first metal wire 11 and the second metal wire 12 in the substrate 10.

[0059] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator, and germanium on insulator, etc. In this embodiment, the material of the substrate 10 is described by taking silicon (silicon substrate) as an example.

[0060] A device layer and an interconnection layer electrically connected to the device layer are formed in the substrate 10. The interconnection layer is located above the device layer and can be formed by a Damascus process. The first metal wire 11 and the second metal wire 12 can be two metal wirings arranged at intervals in the Nth layer (N is greater than or equal to 1) in the interconnection layer, and the material thereof can include, for example, copper. In the present embodiment, the first metal wire 11 and the second metal wire 12 can be two top-layer metal wirings arranged at intervals. A dielectric barrier layer 21 and an insulating layer 22 are sequentially formed on the first metal wire 11 and the second metal wire 12. The material of the dielectric barrier layer 21 is used to block the escape of metal ions and serve as an etching stop layer during etching. The material thereof can include, for example, silicon nitride or silicon carbonitride, and the material of the insulating layer 22 is different from that of the dielectric barrier layer 21, and can include, for example, silicon oxide or silicon oxynitride.

[0061] In addition, in other examples of this embodiment, as needed, multiple (at least two) first metal wires 11 and multiple second metal wires 12 can be set, and multiple identical metal wires are connected in parallel; other metal wires can also be arranged between the first metal wire 11 and the second metal wire 12.

[0062] Next, please refer to Figure 2b , performing step S02 to form a plurality of trenches 23 in the insulating layer 22 between the first metal line 11 and the second metal line 12 .

[0063] A capacitor area AA is provided on the insulating layer 22 between the first metal line 11 and the second metal line 12, and a plurality of grooves 23 are formed in the grooves 23 for subsequently forming a single-layer capacitor thereon. Specifically, a first mask (not shown) may be first formed to cover the surface of the insulating layer 22, and the first mask may be formed with a plurality of openings in the capacitor area AA; the first mask may be used to dry-etch the insulating layer 22 using the dielectric barrier layer 21 as an etching stop layer to form a plurality of grooves 23 in the capacitor area AA; and then the first mask may be removed. The capacitor area AA may include a plurality of grooves 23 and a portion of the insulating layer 22 surrounding them. Of course, in other examples of the present embodiment, the grooves 23 may not penetrate the insulating layer 22.

[0064] In addition, as required, the capacitor area AA may also extend into the insulating layer 22 on the first metal line 11 and / or the second metal line 12 , that is, a groove 23 may be formed in the insulating layer 22 on the first metal line 11 and / or the second metal line 12 .

[0065] Next, please refer to Figure 2c , perform step S03, and sequentially form a first electrode material layer 24, a first dielectric material layer 25, and a second electrode material layer 26 to conformally cover the surface of the insulating layer 22 and the inner wall of the groove 23. Among them, any suitable process can be used to form a thin film conductive layer as the first electrode material layer 24, which may include one or more thin film conductive layers, and its material may include, for example, one or more of titanium, titanium nitride, tantalum, or tantalum nitride. Its formation process may include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The thickness of the first electrode material layer 24 may be, for example, 100 angstroms to 400 angstroms. The material of the first dielectric material layer 25 may be a dielectric material with a relatively high dielectric constant, and its dielectric constant may be, for example, greater than or equal to 3.9. Its material may be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide; the material of the second electrode material layer 26 may be similar to that of the first electrode material layer 24.

[0066] Next, step S04 is performed to perform a patterning process on the second electrode material layer 26, the first dielectric material layer 25 and the first electrode material layer 24 to form a first electrode 24a, a first dielectric layer 25a and a second electrode 26a covering the trench 23 and the insulating layer 22 around the trench 23, and exposing the surfaces of the second electrode 26a and a portion of the first electrode 24a.

[0067] For details, please refer to Figure 2d, the capacitor area AA has a first side A1 and a second side A2 respectively close to the first metal line 11 and the second metal line 12 (opposite), forming a second mask 27 to cover the second electrode material layer 26 of the capacitor area AA, and the second mask 27 may also preferably extend to cover the second electrode material layer 26 close to the first side A1, so as to facilitate subsequent electrical lead-out. However, it should be noted that the second mask should avoid extending above the first metal line 11 or the second metal line 12 as much as possible to prevent short circuit. In this embodiment, the first side A1 of the capacitor area AA is close to the first metal line 11, and the second mask 27 may cover the second electrode material layer 26 of the capacitor area AA and the second electrode material layer 26 between the capacitor area AA and the first metal line 11.

[0068] Please refer to Figure 2e , using the second mask 27, the second electrode material layer 26 and the first dielectric material layer 25 are etched in sequence to expose the surface of the first electrode material layer 24, and the remaining second electrode material layer 26 is used as the second electrode 26a, and the remaining first dielectric material layer 25 is used as the first dielectric layer 25a, and then the second mask 27 is removed. The second electrode 26a and the first dielectric layer 25a have a covering area as close as possible, and both cover the capacitor area AA and the area close to the first side A1.

[0069] Please refer to Figure 2f , a third mask 28 is formed to cover the second electrode 26a, and the third mask 28 extends to cover the first electrode material layer 24 near the second side A2. Preferably, the edge of the third mask 28 near the first side A1 can be aligned with the second electrode 26a as much as possible, and the edge of the third mask 28 on the other side of the capacitor area AA (near the second side A2) can extend to the first electrode material layer 24, that is, the third mask 28 can extend to cover the first electrode material layer 24 near the second side A2.

[0070] Please refer to Figure 2g , the first electrode material layer 24 is etched using the third mask 28 to expose the surface of the insulating layer 22, and the remaining first electrode material layer 24 is used as the first electrode 24a, and then the third mask 28 is removed. The first electrode 24a includes the first electrode material layer 24 located under the second electrode 26a (or the first dielectric layer 25a), and the remaining first electrode material layer 24 on the insulating layer 22 close to the second side A2.

[0071] Thus, a trench capacitor consisting of the first electrode 24a, the first dielectric layer 25a and the second electrode 26a is formed on the insulating layer 22 in the trench 23 and on the periphery of the trench 23 (capacitor region AA), so as to increase the capacitance value (capacitance density) on the same substrate 10 area. Moreover, the first electrode 24a and the second electrode 26a extend from the capacitor region AA to the first metal line 11 and the second metal line 12 respectively and are exposed to facilitate subsequent electrical extraction.

[0072] Next, please refer to Figure 2h , perform step S05 to form a second dielectric layer 31 covering the insulating layer 22, the first electrode 24a, the second electrode 26a and the groove 23. Among them, the second dielectric layer 31 may include a single-layer dielectric or a multi-layer dielectric, and its material may include suitable insulating materials such as silicon oxide, silicon nitride, silicon carbonitride or silicon oxynitride, and may be formed by a suitable process including chemical vapor deposition or atomic layer deposition. In addition to covering the insulating layer 22, the first electrode 24a and the second electrode 26a, the second dielectric layer 31 also fills the groove 23. Compared with the use of electrode materials to fill the groove 23 used to form the capacitor in the related art, the second dielectric layer 31 is used to fill the groove 23 in this embodiment, which is not only conducive to saving electrode materials, but also provides greater freedom for the design of the trench capacitor. It should be understood that the trench capacitor in this embodiment does not lead the electrode out of the trench 23, so it is not necessary to use electrode materials to fill the trench 23, that is, in this embodiment, it is allowed to have a void in the trench capacitor (the second dielectric layer can be used to fill the void later).

[0073] Next, step S06 is performed to form a plurality of through holes in the second dielectric layer 31 and the insulating layer 22 to expose the first electrode 24a, the second electrode 26a, the first metal wire 11 and the second metal wire 12 respectively, and to form a third metal wire 35 to electrically connect the first metal wire 11 and the first electrode 24a, and to form a fourth metal wire 36 to electrically connect the second metal wire 12 and the second electrode 26a.

[0074] Please refer to Figure 2i , a plurality of first through holes 32 are formed in the second dielectric layer 31 to expose the first electrode 24a and the second electrode 26a respectively. Part of the first through holes 32 are located in the second dielectric layer 31 near the first side A1 to expose one of the first electrode 24a and the second electrode 26a, and another part of the first through holes 32 are located in the second dielectric layer 31 near the second side A2 to expose the other of the first electrode 24a and the second electrode 26a. In this embodiment, the first through holes 32 near the first side A1 can expose the first electrode 24a, and the first through holes 32 near the second side A2 can expose the second electrode 26a.

[0075] Please refer to Figure 2j, a plurality of second through holes 33 are formed in the insulating layer 22 and the second dielectric layer 31 to expose the first metal line 11 and the second metal line 12 respectively. Part of the second through holes 33 may be located above the first metal line 11 to expose the first metal line 11, and another part of the second through holes 33 may be located above the second metal line 12 to expose the second metal line 12. In this embodiment, the second through holes 33 also penetrate the dielectric barrier layer 21 under the insulating layer 22, and when etching to form the second through holes 33, the dielectric barrier layer 21 may also serve as an etching stop layer for etching the second dielectric layer 31 and the insulating layer 22 to reduce damage to the metal lines.

[0076] Please refer to Figure 2k , forming a metal material layer 34 to cover the surface of the second dielectric layer 31, the inner wall of the first through hole 32 and the second through hole 33. The metal material layer 34 may be a metal material suitable for connection with an external circuit, such as aluminum or an aluminum alloy. In the present embodiment, the material of the first metal wire 11 and the second metal wire 12 includes copper, and the metal material layer 34 includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer and a titanium nitride layer formed in sequence conformally. In practice, since the size (depth and opening width) of the first through hole 32 is small and the size of the second through hole 33 is large, the metal material layer 34 may fill the first through hole 32, and the metal material layer 34 may only cover the inner wall of the second through hole 33 without filling the second through hole 33.

[0077] Please refer to Figure 2l , a patterning process is performed on the metal material layer 34 to form a third metal line 35 connecting the first metal line 11 and the second electrode 26a and a fourth metal line 36 connecting the second metal line 12 and the first electrode 24a. Specifically, the patterning process of the metal material layer 34 includes disconnecting the metal material layer 34 connecting the two sides of the capacitor area AA, using the metal material layer 34 covering the second through hole 33 on the first metal line 11 to the first through hole 32 close to the first side A1 as the third metal line 35, and using the metal material layer 34 covering the second through hole 33 on the second metal line 12 to the first through hole 32 close to the second side A2 as the fourth metal line 36.

[0078] In addition, during the process of performing the patterning process on the metal material layer 34, the metal material layer 34 can also be used to simultaneously form a metal pad on the second dielectric layer 31, and other top-layer metal lines can be electrically led out to the metal pad for connection with an external circuit. In other words, the electrical lead-out (downward lead-out) of the trench capacitor of this embodiment can be achieved in the step of forming the metal pad, and no additional device structure and process steps are required.

[0079] It is worth mentioning that in other examples of this embodiment, the first electrode in the trench capacitor can also extend a portion of its length from the capacitor area to the first metal wire, and the second electrode can extend a portion of its length from the capacitor area to the second metal wire, so that the third metal wire formed is electrically connected to the first metal wire and the first electrode, and the fourth metal wire is electrically connected to the second metal wire and the second electrode.

[0080] Embodiment 2

[0081] Embodiment 2 provides a capacitor device.

[0082] Figure 2l This is a schematic structural diagram of a capacitor device provided in Example 2.

[0083] The capacitor device provided in this embodiment can be formed by the method provided in the first embodiment. Figure 2l As shown, the capacitor device may include a substrate 10, a first metal line 11 and a second metal line 12, an insulating layer 22, a capacitor, a second dielectric layer 31, a third metal line 35 and a fourth metal line 36. The first metal line 11 and the second metal line 12 are arranged in the same layer in the substrate 10. The insulating layer 22 covers the first metal line 11 and the second metal line 12, and a plurality of grooves 23 are formed in the insulating layer 22 between the first metal line 11 and the second metal line 12. The capacitor is formed in the insulating layer 22 (capacitor region AA) in and around the groove 23, including a first electrode 24a, a first dielectric layer 25a and a second electrode 26a formed conformally in sequence, the first electrode 24a extends a portion of the length from the capacitor region AA to the second metal line 12 (i.e., the second side A2), and the second electrode 26a and the first dielectric layer 25a extend a portion of the length from the capacitor region AA to the first metal line 11 (i.e., the first side A1). The second dielectric layer 31 covers the surface of the capacitor and the insulating layer 22, and a plurality of first through holes 32 are formed in the second dielectric layer 31 to expose the first electrode 24a and the second electrode 26a respectively. A plurality of second through holes 33 are formed in the second dielectric layer 31 and the insulating layer 22 on the first metal wire 11 and the second metal wire 12 to expose the first metal wire 11 and the second metal wire 12 respectively. The third metal wire 35 uses the first through hole 32 and the second through hole 33 close to the first metal wire 11 to electrically connect the first metal wire 11 and the first electrode 24a, and the fourth metal wire 36 uses the first through hole 32 and the second through hole 33 close to the second metal wire 12 to electrically connect the second metal wire 12 and the second electrode 26a.

[0084] In summary, the present invention has a plurality of grooves in the insulating layer between the first metal wire and the second metal wire, and forms a capacitor in the groove and on the insulating layer around the groove, the capacitor includes a first electrode, a first dielectric layer and a second electrode which are formed conformally in sequence, the first electrode and the second electrode respectively extend to both sides of the capacitor and are both exposed upward, then a second dielectric layer is formed to cover the capacitor and the insulating layer, and through holes are formed in the second dielectric layer and the insulating layer to expose the first metal wire, the second metal wire, the first electrode and the second electrode respectively, then a third metal wire is formed by the through hole to electrically connect the first electrode and the first metal wire, and a fourth metal wire is formed to electrically connect the second electrode and the second metal wire, thereby the two electrodes of the capacitor are led downward by the first metal wire and the second metal wire in the substrate, and the lead-out of the capacitor in the capacitor device and the wiring of the metal wire on the insulating layer are completed without adding additional process steps, so that it has a simple lead-out structure, reduces the difficulty of process integration, and is conducive to improving the capacitance density and design freedom of the capacitor in the capacitor device. In addition, compared with the related art where trench capacitors require metal to fill the trenches, the two electrodes of the capacitor in this embodiment extend to both sides to achieve electrical lead-out and do not need to be filled with metal, that is, voids are allowed to exist, which is beneficial to improving the freedom of capacitor design in capacitor devices.

[0085] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a capacitor device, characterized in that: include: Providing a substrate, wherein a first metal line and a second metal line arranged in the same layer and an insulating layer covering the first metal line and the second metal line are formed in the substrate; forming a plurality of grooves in the insulating layer between the first metal line and the second metal line; forming a first electrode material layer, a first dielectric material layer and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the groove; Performing a patterning process on the second electrode material layer, the first dielectric material layer and the first electrode material layer to form a first electrode, a first dielectric layer and a second electrode covering the trench and the insulating layer around the trench, and exposing the second electrode and a portion of the first electrode; forming a second dielectric layer to cover the insulating layer, the first electrode, the second electrode and the trench; A plurality of through holes are formed in the second dielectric layer and the insulating layer to expose the first electrode, the second electrode, the first metal wire and the second metal wire respectively, and a third metal wire is formed to electrically connect the first metal wire and the second electrode, and a fourth metal wire is formed to electrically connect the second metal wire and the first electrode.

2. The method for manufacturing a capacitive device according to claim 1, wherein: A dielectric barrier layer is further provided between the first metal wire, the second metal wire and the insulating layer.

3. The method for manufacturing a capacitive device according to claim 2, wherein: A capacitor region is provided on the insulating layer between the first metal line and the second metal line, and the step of forming a plurality of grooves in the capacitor region comprises: forming a first mask to cover the surface of the insulating layer and to form a plurality of openings in the capacitor region; Using the first mask and the dielectric barrier layer as an etching stop layer, dry etching the insulating layer to form a plurality of the grooves in the capacitor region; The first mask is removed.

4. The method for manufacturing a capacitive device according to claim 3, characterized in that: The capacitor region has a first side and a second side respectively close to the first metal line and the second metal line, and the steps of forming the second electrode and the first dielectric layer include: forming a second mask to cover the second electrode material layer in the capacitor region, wherein the second mask extends to cover the second electrode material layer close to the first side; Using the second mask, etching the second electrode material layer and the first dielectric material layer to expose the surface of the first electrode material layer, and using the remaining second electrode material layer as the second electrode, and using the remaining first dielectric material layer as the first dielectric layer; The second mask is removed.

5. The method for manufacturing a capacitive device according to claim 4, characterized in that: The step of forming the first electrode comprises: forming a third mask to cover the second electrode, wherein the third mask extends to cover the first electrode material layer close to the second side; Using the third mask, etching the first electrode material layer to expose the surface of the insulating layer, and using the remaining first electrode material layer as the first electrode; The third mask is removed.

6. The method for manufacturing a capacitive device according to claim 1, characterized in that: The steps of forming a plurality of the through holes include: Forming a plurality of first through holes in the second dielectric layer to expose the first electrode and the second electrode respectively; A plurality of second through holes are formed in the insulating layer and the second dielectric layer to expose the first metal line and the second metal line respectively.

7. The method for manufacturing a capacitive device according to claim 6, characterized in that: The steps of forming the third metal line and the fourth metal line include: forming a metal material layer to cover the surface of the second dielectric layer, the first through hole and the inner wall of the second through hole; A patterning process is performed on the metal material layer to form the third metal line electrically connecting the first metal line and the second electrode, and to form the fourth metal line electrically connecting the second metal line and the first electrode.

8. The method for manufacturing a capacitive device according to claim 1, characterized in that: When the metal material layer is patterned, a metal pad is also formed on the surface of the insulating layer for connection with an external circuit.

9. The method for manufacturing a capacitive device according to claim 1, characterized in that: The materials of the first electrode material layer and the second electrode material layer include one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

10. A capacitor device, characterized in that: include: substrate; A first metal line and a second metal line are arranged in the substrate in the same layer; an insulating layer covering the first metal line and the second metal line, wherein a plurality of grooves are formed in the insulating layer between the first metal line and the second metal line, and a plurality of second through holes are formed in the insulating layer on the first metal line and the second metal line to expose the first metal line and the second metal line respectively; A capacitor formed in the trench and on the insulating layer around it, comprising a first electrode, a first dielectric layer and a second electrode formed conformally in sequence; A second dielectric layer covers the capacitor, and a plurality of first through holes are formed in the second dielectric layer to expose the first electrode and the second electrode respectively; The third metal wire and the fourth metal wire utilize the first through hole and the second through hole. The third metal wire electrically connects the first metal wire and the second electrode, and the fourth metal wire electrically connects the third metal wire and the first electrode.

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